WO1999039474A1 - Procede et dispositif permettant d'augmenter le debit dans un bus de donnees - Google Patents

Procede et dispositif permettant d'augmenter le debit dans un bus de donnees Download PDF

Info

Publication number
WO1999039474A1
WO1999039474A1 PCT/US1999/002124 US9902124W WO9939474A1 WO 1999039474 A1 WO1999039474 A1 WO 1999039474A1 US 9902124 W US9902124 W US 9902124W WO 9939474 A1 WO9939474 A1 WO 9939474A1
Authority
WO
WIPO (PCT)
Prior art keywords
parallel data
data
lines
bus
values
Prior art date
Application number
PCT/US1999/002124
Other languages
English (en)
Inventor
David C. Robb
Original Assignee
Spectraplex, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spectraplex, Inc. filed Critical Spectraplex, Inc.
Priority to AU24897/99A priority Critical patent/AU2489799A/en
Publication of WO1999039474A1 publication Critical patent/WO1999039474A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/20—Arrangements affording multiple use of the transmission path using different combinations of lines, e.g. phantom working
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Definitions

  • the present invention relates to the field of data transmission and more specifically to a method and apparatus for utilizing available bandwidth to increase the effective throughput in a data communications device.
  • the predominant current usage of the present inventive throughput expansion method and apparatus is for the communication of data on a data bus wherein, it is desirable to effectively increase throughput within the fixed limitations of the transmission means.
  • a preferred embodiment of the present invention is method and apparatus whereby data in the form of a parallel data stream is combined (by summing in this embodiment) into a quantity of physical channels (physical leads or traces over which an electric signal can be transmitted) such that each of the physical channels will carry a some, but not all, of the parallel data streams.
  • each of the parallel data streams is recovered by processing the outputs of the combined data as it appears at the output end of the physical channels.
  • each of the parallel data streams will be emphasized by correlation processing within its respective assigned set, while information relating to other of the data streams in each of the individual outputs will tend to be random, and therefore de-emphasized, in that particular set.
  • Alternate embodiments of the invention combine information derived from subgroupings of output channels with additional limitations based on the system structure to produce an output generally equivalent to the input data. It will be noted that, irrespective of the general embodiment of the invention, the inventive method can be accomplished in any of several general manners, including through the use of analog type circuitry, logic circuitry, or by computational methods, each of which will be disclosed herein.
  • An advantage of the present invention is that throughput is effectively increased relative to a fixed number of data transmission paths.
  • a further advantage of the present invention is fewer transmission paths are required to transmit a given quantity of data. Yet another advantage of the present invention is that it does not require a great deal of processor overhead.
  • Still another advantage of the present invention is that it is relatively easy and inexpensive to implement.
  • Yet another advantage of the present invention is that it will work well with multilevel memory devices, and the like. Still another advantage of the present invention is that it will permit wide parallel data transmission in integrated circuits where there might otherwise be insufficient space to provide the necessary number of data transmission leads and pins.
  • Fig. 1 is a flow diagram depicting some basic operations of the inventive throughput data bus communication method
  • Fig. 2 is a block diagram of a portion of a computer showing a data bus and related components
  • Fig. 3 is a chart showing the relationship of data ordered sets and unique solutions therefor, according to the present invention.
  • Fig. 4 is a schematic diagram showing a circuit suitable for accomplishing the method described in relation to Fig. 1 ;
  • Fig. 5 is a block diagram, similar to the view of Fig. 2, showing another embodiment of the invention;
  • Fig. 6 is a chart showing an example of usage of physical channels in relation to virtual channels, according to the present invention.
  • Fig. 1 is a diagrammatic illustration of a computer 12 having a data bus 14 configured to be used according to the best presently known embodiment 10 of the present invention.
  • Fig. 2 is a diagrammatic illustration of a computer 12 having a data bus 14 configured to be used according to the best presently known embodiment 10 of the present invention.
  • the computer 12 as illustrated in the example of Fig. 2, is not complete in all detail. Rather, in order to best illustrate the present invention, only those portions of the computer 12 which are useful in understanding the operation of the invention are shown in the view of Fig. 2.
  • each of a plurality (six, in the example of Fig. 2) of output data lines 16 is connected to a plurality (four, in the example of Fig. 2) of summing circuits 18.
  • each of the output data lines 16 is summed into two of the summing circuits 18, such that each of the summing circuits 18 receives its input from three of the output data lines 16.
  • the bus lines 20 are generally the physical electrical paths over which data is transmitted in the parallel data bus 14, although it is within the scope of the invention that the data bus communication method 10 could also be used in other types of data busses or other communications means.
  • the inventive method could be applied to the parallel data before it is serialized and after it is deserialized.
  • the data bus is terminated in a receiving circuit 22, which will be discussed in more detail hereinafter, which provides a plurality (equal in quantity to the plurality of output data lines 16 - which is six in the present example) of input data lines 24.
  • the output data lines 16 could be from essentially any component or device in the computer 12 (or from an external device communicating with the computer 12) which outputs parallel data, such as a memory chip, a CPU, or a specialized card communicating through the data bus 14, such as a video card, or the like.
  • the input data lines 24 represent the data input to essentially any device within or external to the computer 12 which is intended to receive parallel data through the data bus 14.
  • a sum data onto bus lines operation 26 sums data from the output data lines 16 onto the bus lines 20.
  • a transmit data operation 28 is merely the providing of the output of the summing circuits to the bus lines 20.
  • the summing circuits 18 are simple summing circuits with which one skilled in the art will be readily familiar. It can be appreciated then, that the output of the summing circuits will be of a multilevel nature. For example, if the data on the output data lines 16 is characterized by zero volts for a "0" bit and one volt for a "1" bit, then the corresponding voltage present on each of the bus lines 20 could be Ov, 1v, 2v or 3v, depending upon whether zero, one, two or three of the inputs is high. Indeed, there are now appearing on the market memory devices which make use of such multilevel value schemes. It is important to note that the present invention may be readily applied to memory devices, and the like, which already store information in the form of multilevel values.
  • such devices receive a binary input which is "encoded" to an appropriate level in a multilevel set.
  • Such a scheme allows storage of more than one bit at a single location in the memory.
  • the multilevel value is decoded into the appropriate binary values for output.
  • the multilevel data on the physical channels can be directly stored in the memory without encoding.
  • the data will, according to the present invention, inherently be provided in a multilevel format suitable for storage in the multilevel storage device. That is, such memory device will be inherently store and output data in the form discussed herein as being provided to and/or received from the bus lines 20.
  • the present inventive method and apparatus will be used on the end of the data stream which is communicating with such memory device.
  • the "receiving" end of the data bus 14 is the receiving circuit 22 which takes its input from the (four, in the present example) bus lines 20 and outputs a parallel data byte having (six, in the present example) bits on the corresponding number of input data lines 24.
  • the receiving circuit will have a simple multilevel comparitor circuit 30 for each of the bus lines 20 for providing, in binary form, the value of each of the bus lines 20 to a logic unit 32. This operation is illustrated in the flow diagram of Fig. 1 by a determine value for each bus line operation 34.
  • the logic unit 32 accomplishes a determine derived equation operation 36.
  • S represents the values present on each of the bus lines 20 (which will, as discussed previously, be the sum of the values provided to the summing circuit 18 feeding each respective bus line 20) and N is the total number of the bus lines 20 which are used to carry the signal of any particular bit (two, in this example).
  • N is the total number of the bus lines 20 which are used to carry the signal of any particular bit (two, in this example).
  • a unique set of values for most (but not all) ordered sets of values originally provided on the output data lines 16 can be determined.
  • Fig. 3 is data chart 39 illustrating the possible ordered sets 40 of data which might be present on the output data lines 16. As can be see in the chart of Fig.
  • the value B provides an integrity check for the data, since any value of B that is not an integer will indicate invalid data. It is important to note that the example related herein in relation to Figs. 2 and 3 are not intended to limit the scope of the invention to the quantities of output data lines 16 and bus lines 20 used in the example. Indeed, larger combinations numbers of output data lines 16 and bus lines 20 often result in there being totally unique solutions for each of the ordered sets 40 of data such that there is no resultant data loss, in the sense discussed above.
  • each of coordinates in the matrix can be represented by an integer Hx,y where x is the row and y is the column of the two dimensional matrix.
  • each of the bus lines 20 provides signal to three comparitors 46. (Three being the quantity of output data lines 16 which have been summed into each of the bus lines 20). There are two of the comparitors 46 for each of the input values A through F. (Two being the quantity of different bus lines 20 to which data from each of the output data lines 16 is provided).
  • Each of the outputs of the AND gates 48 can, therefore, be considered to be an estimate of the values A through F, which are labeled in the schematic of Fig. 4 as A' through F' respectively.
  • Each of the comparitors 46 is also provided with the inverted output of a summing amplifier 50.
  • the inputs of each of the summing amplifiers 50 are two of the values A' through F' (the derivation of which is discussed above) which correspond to the two values to be found on the bus line 20 of concern and which are not the specific value A through F of concern.
  • the two inputs to the summing amplifier 50a are C and E'.
  • the summing circuit 18 "SO" has inputs A, C and E.
  • the comparitor 46 Since the comparitor 46 is intended to provide an output referenced to A, then the summing amplifier 50a has as its inputs C and E', thereby subtracting the current estimates for C and E' from the summed estimates for A, C and E, initially provided to the comparitor 46a. 13
  • the operation of the above described circuit will generally be essentially asynchronous.
  • the logic unit 32 of Fig. 4 will have a settling time, which could be accounted for by clocking the output of the circuit at a rate sufficiently slow to insure that the required settling will occur.
  • the settling could be monitored and the output of the logic circuit 32 latched out when it is detected that settling has occurred.
  • Fig. 5 is a block diagram, similar to the view of Fig. 2, showing an another embodiment 414 of the inventive data bus.
  • a plurality of output sets 450 are sets of those bus lines 20 into which each of the output data lines 16 have been summed. Therefore, the output sets 450 will be equal in quantity to the output data lines 16 (17 in the present example), and each of the output sets 450 will have input from N of the bus lines 20.
  • Fig. 6 is a table showing how many times each of the bus lines 20 is used, and into which of the bus lines 20 each of the output data lines is summed.
  • the rows represent the output data lines 16 and the columns represent the bus lines 20. 14
  • Yet another example of an application of the present invention would be to provide the same principles to essentially any parallel data (or data that could be put into a parallel format) whether or not such data is to be transmitted on a bus of a computer.
  • the data bus communication method 10 of the present invention may be readily produced into existing data communications systems and devices, and since the advantages as described herein are provided, it is expected that it will be readily accepted in the industry, especially considering the above discussed problems with real estate in many digital integrated circuits, particularly at the perimeter where input and output lines and pins are located. For these and other reasons, it is expected that the utility and industrial applicability of the invention will be both significant in scope and long lasting in duration.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un procédé permettant le transport d'une quantité accrue de données dans une ligne (20) de transmission de données dans un bus (14) de données etc. Les données provenant d'une pluralité de lignes (16) de données de sortie sont combinées dans des circuits (28) de totalisation et le résultat est envoyé à une quantité plus petite de lignes (20) de bus et transmis par ces dernières. Les données combinées sont traitées à une extrémité de réception de manière à corréler des ensembles (40) ordonnés de données qui, dans un mode de fonctionnement (42) à détermination de solutions uniques, est utilisé pour reproduire les données d'origine provenant des lignes (16) de sortie du bus (14) de données.
PCT/US1999/002124 1998-01-29 1999-01-29 Procede et dispositif permettant d'augmenter le debit dans un bus de donnees WO1999039474A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU24897/99A AU2489799A (en) 1998-01-29 1999-01-29 Method and apparatus for increasing throughput in a data bus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1573298A 1998-01-29 1998-01-29
US09/015,732 1998-01-29

Publications (1)

Publication Number Publication Date
WO1999039474A1 true WO1999039474A1 (fr) 1999-08-05

Family

ID=21773271

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/002124 WO1999039474A1 (fr) 1998-01-29 1999-01-29 Procede et dispositif permettant d'augmenter le debit dans un bus de donnees

Country Status (2)

Country Link
AU (1) AU2489799A (fr)
WO (1) WO1999039474A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10234720A1 (de) * 2002-07-30 2004-02-12 Infineon Technologies Ag Schnittstellen-Schaltanordnung
EP2141821A1 (fr) * 2008-07-03 2010-01-06 Oki Electric Industry Co., Ltd. Transmetteur de signal CDM avec des modulateurs réduits en nombre et procédé associé

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4370745A (en) * 1980-11-14 1983-01-25 Bell Telephone Laboratories, Incorporated Fail-safe transmission system
US5548819A (en) * 1991-12-02 1996-08-20 Spectraplex, Inc. Method and apparatus for communication of information
US5553097A (en) * 1994-06-01 1996-09-03 International Business Machines Corporation System and method for transporting high-bandwidth signals over electrically conducting transmission lines
US5598406A (en) * 1992-11-06 1997-01-28 Hewlett-Packard Company High speed data transfer over twisted pair cabling

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4370745A (en) * 1980-11-14 1983-01-25 Bell Telephone Laboratories, Incorporated Fail-safe transmission system
US5548819A (en) * 1991-12-02 1996-08-20 Spectraplex, Inc. Method and apparatus for communication of information
US5598406A (en) * 1992-11-06 1997-01-28 Hewlett-Packard Company High speed data transfer over twisted pair cabling
US5553097A (en) * 1994-06-01 1996-09-03 International Business Machines Corporation System and method for transporting high-bandwidth signals over electrically conducting transmission lines

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10234720A1 (de) * 2002-07-30 2004-02-12 Infineon Technologies Ag Schnittstellen-Schaltanordnung
EP2141821A1 (fr) * 2008-07-03 2010-01-06 Oki Electric Industry Co., Ltd. Transmetteur de signal CDM avec des modulateurs réduits en nombre et procédé associé
US8279967B2 (en) 2008-07-03 2012-10-02 Oki Electric Industry Co., Ltd. CDM signal transmitter with modulators reduced in number and a method therefor

Also Published As

Publication number Publication date
AU2489799A (en) 1999-08-16

Similar Documents

Publication Publication Date Title
US3757306A (en) Computing systems cpu
US4860353A (en) Dynamic feedback arrangement scrambling technique keystream generator
US5130991A (en) Method and apparatus for crc computation
JP2000165375A5 (fr)
KR100308723B1 (ko) 올림수-보존 가산기회로 및 복수의 이진 데이터 비트 합산 방법
EP0074401A4 (fr) Procede et dispositif de mise en sequence des adresses d'une rangee de transformations rapides de fourier.
ATE223105T1 (de) Mehrpegeldaten durch eine einzige eingangs- /ausgangspinne
EP0953175B1 (fr) Procede et dispositif de calcul de tfr
US6721918B2 (en) Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
WO1999039474A1 (fr) Procede et dispositif permettant d'augmenter le debit dans un bus de donnees
JPH04362759A (ja) 中央処理装置
JPH0228764A (ja) 記憶アクセス制御装置
US4789852A (en) Method and apparatus for converting data in a binary format
US6609142B1 (en) Method of performing multiplication with accumulation in a Galois body
CN101809638A (zh) 运算方法和运算装置
CN111177142A (zh) 一种数据转换方法及装置、设备和存储介质
US20210132909A1 (en) Processing-in-memory (pim) devices and methods of testing the pim devices
CN114217858B (zh) 一种数据处理电路、系统及数据处理方法
US6076098A (en) Adder for generating sum and sum plus one in parallel
US20220222045A1 (en) Processing-in-memory devices having multiplication-and-accumulation circuits
US6981206B1 (en) Method and apparatus for generating parity values
KR920005094Y1 (ko) 프로그래머블 콘트롤러의 입출력 랙 및 카드 선택장치
JPH044612B2 (fr)
JPS5821299B2 (ja) メモリ
SU744731A1 (ru) Посто нное запоминающее устройство

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase