WO1999035689A1 - Semiconductor package converter module - Google Patents

Semiconductor package converter module Download PDF

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Publication number
WO1999035689A1
WO1999035689A1 PCT/JP1999/000005 JP9900005W WO9935689A1 WO 1999035689 A1 WO1999035689 A1 WO 1999035689A1 JP 9900005 W JP9900005 W JP 9900005W WO 9935689 A1 WO9935689 A1 WO 9935689A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
board
pins
pin
semiconductor package
Prior art date
Application number
PCT/JP1999/000005
Other languages
French (fr)
Japanese (ja)
Inventor
Kunio Nagaya
Original Assignee
Ibiden Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co., Ltd. filed Critical Ibiden Co., Ltd.
Priority to AU16932/99A priority Critical patent/AU1693299A/en
Publication of WO1999035689A1 publication Critical patent/WO1999035689A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/32Holders for supporting the complete device in operation, i.e. detachable fixtures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04Assemblies of printed circuits
    • H05K2201/049PCB for one component, e.g. for mounting onto mother PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10333Individual female type metallic connector elements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10704Pin grid array [PGA]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447Lead-in-hole components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Definitions

  • the present invention relates to a semiconductor package conversion module used, for example, when upgrading a semiconductor package having a CPU (central S position) function mounted on a motherboard.
  • a semiconductor package having a function as a CPU is mounted on a mother board of the personal computer via a socket.
  • a PGA pin grid array
  • a conversion module having a socket S3 ⁇ 4 on which a semiconductor package is mounted and a conversion S «having a circuit for inputting I / O pins as main components has been proposed.
  • a plurality of snow holes are provided on the transformer, and external connection pins are inserted into the openings on the lower surface. These external pins are ⁇ 1 ⁇ for the socket on the motherboard.
  • Socket II has multiple IZO pins. These I / O pins are provided at locations corresponding to the multiple plated through holes in the back of the socket. Each pin is inserted into each of the plated through holes and soldered, so that electrical conduction between the socket side and the conversion side is achieved.
  • these IZO pins are socket-like pins having through holes on the upper end surface of which the I / O pins of the package are fitted.
  • a common technique for soldering lead wires involves a series of complicated operations (cutting a covered lead wire to a predetermined length, peeling off the coating of the soldered part, pre-soldering, positioning and positioning). Soldering) is required, resulting in poor properties. In particular, as the semiconductor package becomes finer and the number of pins increases, it is expected that the positioning operation itself will become difficult, and that it will also lead to a decrease in connectivity.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a relatively simple semiconductor package conversion module used for, for example, upgrading a package mounted on a motherboard. It is an object of the present invention to provide a semiconductor and package conversion module having a structure that allows connection of I / O pins easily and without increasing cost, and that has excellent connectivity.
  • the first connection board is formed with a replacement connection circuit and has an external connection conductor pin on the lower surface side, and a semiconductor package is mounted on the upper surface side, and corresponds to the external connection conductor pin.
  • a second 3 ⁇ 4K having an I ZO terminal which protrudes downward at the position, and a flB disposed between the first and the second S3 ⁇ 4, and a connection circuit and identification of the I ⁇ terminal
  • a conductor having a conductor pattern connected to the I ⁇ terminal of the ir, and the conductor pin for connecting the tirts ⁇ section and the ia specific I / o terminal are electrically connected via the replacement connection circuit.
  • Semiconductor package conversion module It is.
  • a second invention is the double-sided board according to the first invention, having a through hole fitted with the first board, wherein the external connection conductor pin is located at an opening on the lower surface side of the through hole.
  • the IB-specific I / O terminal is a semiconductor package conversion module located at the opening on the upper surface side of the through hole via the insulating base material of the daughter board.
  • the position of the daughter board on the first board is regulated in a vertical direction by the specific IZO terminal, and the position of the child substrate is controlled by the specific IZO terminal.
  • This is a semiconductor package conversion module that is restricted in the horizontal direction by the side of the Izo terminal, which has a relatively large protruding length.
  • the thickness of the child board is 0.8 mm or less, and the fffE conduction is turned from the outer edge of the child board to a specific I.
  • This is a ⁇ package conversion module having a primary side pad formed by Sim and a secondary side pad formed at an outer edge of a ⁇ -element board which is a 515 connection circuit side.
  • the first substrate-side replacement connection circuit and the specific IZO3 ⁇ 4fr which require the replacement connection are provided via a lead turn provided in a child disposed between the first and second elements.
  • connection to a specific I / O terminal is performed. Since the child S3 ⁇ 4 has pre-formed turns, it does not require any troublesome work such as cutting to a predetermined length or stripping the insulation coating, unlike ⁇ using lead wires. Becomes
  • a specific one of the signals on the semiconductor package side flows through the specific IZO terminal and is converted by a signal modulator or the like that has been changed. Supplied to one board.
  • the first S ⁇ ⁇ ⁇ g it is sufficient for the first S ⁇ ⁇ ⁇ g to have a simple structure such as ⁇ ⁇ ⁇ on both sides, and it is not necessary to rely on an expensive and cumbersome multilayer board or a build-up layer for connection. . Therefore, ⁇ cost reduction is surely avoided.
  • the element can be a single-sided S «having a ⁇ turn formed by the subtractive method on one side of the element, it can be relatively easily manufactured. However, this does not lead to higher costs.
  • the tip of the specific IZO terminal requiring connection in which a child is arranged between the conversion and the socket board, can be positioned while being placed on the pad of the rfB conductive turn. Therefore, a specific I / O terminal and a pad can be easily and reliably connected.
  • conduction is established with the corresponding through hole that is inserted into the corresponding through hole and the same through hole.
  • the I5 specific IZO pin is not inserted into the corresponding through-hole opening, and is in a non-conducting state because it intersects with the through-hole. .
  • the same substrate is held by the IZO terminal so as not to be displaced, so that the positioning itself becomes extremely easy. From the above, according to the present invention, the connection can be simply performed, and the connection ft reliability is excellent.
  • the pad at the insertable portion is positioned with respect to the specific I / O terminal at this time, the two can be easily and reliably connected.
  • the primary pad is formed at a position axax from the outer end of the child ⁇ K, there is a danger that molten solder will flow out at the time of contact with the IZO terminal and short-circuit with the first upper conductor pattern. Less is. Since the thickness of the sub-board is 0.8 mm or less and the secondary pad is formed at the outer edge of the sub-board, the electric conduction to the conductive and Connection is easy.
  • FIG. 1 is a schematic diagram for explaining a use state of a conversion module according to an embodiment of the present invention.
  • FIG. 2 is a plan view of a child used in the same embodiment
  • FIG. 3 is a plan view showing a state where the child of the same embodiment is arranged
  • FIG. 4 is a partially enlarged cross-sectional view of the conversion module of the same embodiment.
  • FIG. 5 and FIG. 5 are plan views showing a sub-substrate before being divided according to the same embodiment, and FIG.
  • FIGS. 1 to 5 the semiconductor ⁇ Kkeji conversion module 1 of the PGA type having a function as embodying CPU of one embodiment form ⁇ .
  • the conversion module 1 of this embodiment converts the PGA 2 into a signal.
  • This is a device for mounting on the motherboard MB after performing the above.
  • the conversion module 1 has a plurality of boards, that is, a conversion board 3 and a socket board 4 as its main components.
  • the first transformation S3 ⁇ 4 3 is a rectangular, rigid, double-sided S ⁇ .
  • the variation m3 ⁇ 43 ⁇ 43 includes a plated through hole group in which a plurality of plated through holes 5 are arranged in a substantially square shape. As shown in FIG. 3, each plated through-hole 5 is arranged in a staggered pattern with a fixed pitch. As shown in FIG. 4, the base end of the external connection pin 6 is inserted into the opening on the lower surface side of each of the attached through holes 5. This pin 6 may be joined by soldering.
  • One die pad 7 and a plurality of pads 8 surrounding the die pad 7 are formed in a substantially square region surrounded by the plated holes.
  • a signal conversion QFP (quad flat package) 9 as a signal element is surface-mounted on the die pad 7.
  • Each lead of Q FP 9 is joined to each pad 8 using solder S 1 that is a conductive material.
  • solder S 1 that is a conductive material.
  • One of the return pads 8 is assigned as a replacement pad 8a as a connection circuit.
  • a pad 10 for electrical connection is formed in the region.
  • DIP dual in-line package
  • the electronic component ⁇ ⁇ pad 12 is also formed on the lower surface side of the conversion 3, and the tip 13 is formed on the surface.
  • These electronic components 11 and 13 are also joined to the pads 10 and 12 using solder S 1.
  • a conductor pattern (not shown) is formed on the upper surface and the lower surface of the modification 3. The conductor pattern described above electrically connects the lands 5 a and 5 b of the plated through hole 5, the Q FP 9, and the electronic components 11 and 13 to each other.
  • the minor hole has a smaller diameter (several ⁇ ⁇ ⁇ ) than a normal plated snow-hole for pin conduction and front-to-back conduction.
  • the pad 8 (8b in FIG. 1) corresponding to the side on which the ffirie conversion signal is output is electrically connected to the upper end of the mini-via hole penetrating the upper and lower surfaces of the conversion board 3.
  • the absolute shape of the sockets 2-4 as the second substrate is square and frame-shaped, and the size of the outer shape is not limited to the load. Approximately equal to the size of PGA 2. «3 ⁇ 4 ⁇ 2 1 ⁇ A central hole 22 is provided. The reason for providing the central hole 22 is to secure a space for accommodating the QFP 9, facilitate soldering, and efficiently dissipate the heat generated by the QFP 9. Therefore, the central hole 22 is preferably formed slightly larger than the QFP9 at a position corresponding to the QFP9.
  • Each socket-like pin 24 has a through hole 25 extending in the axial direction.
  • the I / O pins 26 on the PGA2 side can be inserted into and removed from the through holes 25. That is, the socket board 4 has a structure on the front side (upper side) on which the PGA 2 can be attached and detached.
  • a specific IZO pin requiring connection is represented by 24 A to distinguish it from other I / O pins 24 that do not require replacement connection.
  • the plated through-holes corresponding to the specific IZO pins 24 A are represented by 5 A to distinguish them from other plated through-holes 5.
  • the land 5 Ab at the opening on the lower surface side of the plated snow hole 5 A and the lower end of the above-mentioned mini via hole are electrically connected by a conductor pattern (not shown). Therefore, the output side of QFP9 and the land 5 Ab are electrically connected, and this is schematically indicated by the arrow A1 in FIG.
  • the small-diameter portion of the specific I / O pin 24A is formed to be somewhat shorter than the small-diameter portions of the other 10 pins 24. Therefore, even if another I / O pin 24 that does not need to be inserted is inserted into the opening on the top side of the plated through hole 5, the corresponding one pin It is not inserted into the opening on the upper surface side of the through hole 5A.
  • the specific IZO pin 24A is separated from the land 5Aa of the upper opening of the snug hole 5A. That is, there is a gap between the modulation S plate 3 and the specific IZO pin 24A, into which a child substrate 36 described later can be inserted.
  • ⁇ 5 specific I pin 24 ⁇ can be obtained, for example, by cutting a small-diameter portion of the other I 0 pin 24 that does not require replacement connection by a predetermined length.
  • two types of IZO pins 24, 24 mm with different lengths may be prepared in advance and used. It is also possible to bend the / h # part of the I / O pin 24 and use it as a specific I / O pin 24A.
  • a socket 30 is fixed to the motherboard MB in advance so that it cannot be removed by soldering, and the conversion module 1 is mounted on the upper surface side of the socket 30. Used in. At this time, the external connection pin 6 is inserted into the insertion hole of the socket-shaped pin 31 of the socket 30. Note that, for the sake of convenience when replacing parts, soldering is not performed on the connection site.
  • the conversion module 1 of the present embodiment includes a sub board 36 in addition to the conversion 3 and the socket 4.
  • a sub board 36 in addition to the conversion 3 and the socket 4.
  • the sub-substrate 36 of the present embodiment is provided with a conductor 38 on one side of an insulating base material 37.
  • the conductor pattern 38 is preferably formed by a conventionally known subtractive method.
  • the absolute 37 used here is rectangular and rigid, and has a thickness of 0.8 ran.
  • the width W1 of the pin 37 is set to be slightly smaller than the pitch of the I / O pins 24 (for example, 2.54 mm, 1.27 plane). Therefore, a part of ⁇ & ⁇ 3 ⁇ 43 ⁇ 4 ⁇ 37 (that is, the insertable element P 1) can be inserted between the I / O pins 24 of a number that does not require insertion.
  • the conductor pattern 38 is formed so as to extend along the longitudinal direction of the insulating material 37.
  • a primary pad 39 is formed at one end of the conductor pattern 38, and a secondary pad 40 is formed at the other end.
  • the primary side pad 39 has a circular shape and is located substantially at the center of the insertable portion P 1 in the insulation 37.
  • the secondary pad 40 has a rectangular shape and is located at the absolute TO. From the viewpoint of improving the fififiability of the soldered portion, it is preferable that these pads 39 and 40 are formed as large as possible. However, the primary pad 39 has its diameter
  • FIG. 5 shows an example of the multi-piece board B 1 used at that time.
  • the child 36 provided with the conductor pattern 38 is used in a state where it is placed between the terminals 3 and 4. At this time, the pattern formation surface of the child # 36 is directed toward the socket # 4. If the pattern formation surface of the child S36 faces the conversion S3 ⁇ 43 side, if there is not enough space, the conductors 38, etc. may come into contact with the lands 5a, 5Aa and short-circuit. is there. The child 36 disposed between the two 3 and 4 is brought into contact with the outer peripheral surface of the IZO pin 24 so that it cannot be displaced in its own plane.
  • the daughter board 36 be in contact with (or be capable of contacting) a plurality of IZO pins 24.
  • the sub-board 36 comes into contact with the five IZO pins 24. More specifically, one of the five I / O pins 24 abuts on the insertion side short side of the child 36. Further, two of the remaining four IZO pins 24 are in contact with one of the long sides of the sub board 36, and the other two are in contact with the other side of: 3 ⁇ 42 . Therefore, this child 36 is positioned from three directions.
  • the primary side pad 39 is located just below the specific I / O pin 24 A, and is provided with the V “hole 5 A” just above the pin.
  • the tip of the I / O pin 24 A is in a state of being 9g on the primary pad 39.
  • the secondary pad 40 is on the conversion ⁇ ⁇ tK3.
  • Input ⁇ Take the position corresponding to the pad 8a, and use the solder S1 to join the tip of the specific I / O pin 24A and the primary pad 39 to form the secondary pad 4a. Transposition pad 8a with 0 is joined.
  • the variation 3 can be obtained by forming a known pattern such as a subtractive method using, as a starting material, a stretched laminate obtained by sticking a copper foil to a surface of a glass epoxy insulated material W, for example. be able to.
  • through-holes 5, 5A, mini-via holes, dipads 7, pads 8, 8a, 8b, etc. are formed on the insulating base material.
  • the socket can be obtained by piercing the pin-through holes 23 in the frame-shaped iifeig 21 and then inserting the socket-shaped I / O pins 24 into them.
  • the child 36 is manufactured by a subtractive method using, for example, a copper-clad laminate obtained by attaching a copper foil to one surface of glass epoxy ⁇ . »In order to divide the pieces, the board for multiple pieces B 1 is divided along the broken lines in FIG.
  • the external connection pin 6 is press-fitted into the opening on the lower surface side of each of the through holes 5 and 5 A on the conversion board 3.
  • a cream solder is printed on the land 5a of the through hole 5 located on the upper surface side of the conversion board 3 by screen printing.
  • each socket-like IZO pin 24 is passed through the opening on the upper surface of the through hole 5 to which the conversion board 3 is attached, and the QFP 9 is placed on the die pad 7. Is fixed.
  • the temperature in the furnace is raised to around fi3 ⁇ 4 where the cream solder melts, and the solder S1 is discharged.
  • the socket-shaped IZO pin 24 is joined to the attached hole 5, and the leads of the QFP 9 are joined to the pads 8, 8a, 8b.
  • the insertable SBfePl of the child S # 36 is inserted between the IZO pins 24.
  • the child 36 can be inserted, for example, through the central hole 22 of the socket 4 (see Hi arrow A2 in FIG. 1).
  • the child 3 ⁇ 4K 36 positioned as indicated by the insertion between the I / O pins 24 is individually soldered using the solder S1.
  • the electronic components 11 and 13 are soldered individually to the corresponding pads 10 and 12 at the same time.
  • the PG # 2 is mounted on the conversion module 1, and the PG # 2 is mounted on the socket 30 of the motherboard MB.
  • the signal conversion is mainly performed by the QFP 9, and the original function of the PGA 2 can be sufficiently exerted.
  • connection pads 8a and the specific I / O pins 24A required for connection are provided via the conductor pattern 38 of the child board 36 disposed between the two boards 3 and 4. Are electrically connected. As a result, a swap connection is made for the specific I / O pin 24A.
  • the specific I / O pin 24 A is not directly conducted to the external conversion pin 6 through the corresponding plated through hole 5 A, but is converted into a signal through the QFP 9 or the like. After that, it is indirectly connected to the external connection pin 6. Since the conductor pattern 38 is formed on the terminal 36 in advance, unlike a case where a lead wire is used, troublesome operations such as cutting to a predetermined length or peeling off the coating are not required.
  • the rigid child 36 is fixed, unlike the lead wire, so that the rigid child 36 abuts on the IZO pin 24 and is kept in position. For this reason, the positioning itself becomes very easy. From the above, this form According to this, replacement can be performed relatively easily, and workability can be improved in the manufacture thereof.
  • the conversion sickle 3 only needs to have a simple structure of a double-sided board, and it is not necessary to rely on a multilayer board or a build-up layer for connection. . Therefore, it is possible to reliably avoid high costs when performing the entry.
  • the child 36 is a single-sided plate having the pattern 38 formed by the subtractive method on one side of the mf 37, it is a decoration and can be relatively easily adjusted. . Therefore, even if this is used, it does not lead to particularly high cost. Furthermore, the sub board 36 used in the present embodiment is much smaller than the conversion board 3 and the socket board 4. Moreover, a large number of powerful children ⁇ 36 can be obtained from a single plate material by a large number of pieces. The above also contributes to prevention of cost increase. It should be noted that child like this ⁇ form
  • the specific I / O pin 24 A which requires connection is formed shorter than other IZO pins 24 which do not require connection. Therefore, when the child board 36 is arranged between the two boards 3 and 4, the tip of the specific I pin 24 is positioned while placed on the primary pad 39 of the conductor pattern 38. . Therefore, both 24 A and 39 can be easily and reliably connected. ,
  • the child is not limited to the child S3 ⁇ 436 having only one ° -turn 38, and may have a plurality of children. Further, the present invention is not limited to the rectangular child S ⁇ b> 36, and may have other shapes.
  • another example of the child 41 shown in FIG. 6 has a substantially U-shape, and two conductor patterns 38 are provided on one side thereof. A primary pad 39 and a secondary pad 40 are formed at both ends of each conductor pattern 38.
  • Child 3 ⁇ 43 ⁇ 4 36 is not limited to rigid ones, but may be thin and flexible. By doing so, the step with the upper surface of the converter # 3 is reduced, so that the solder S1 is surely easily applied and soldering to the secondary pad 40 becomes easier. This leads to a further improvement in reliability.
  • a solder ball or the like may be provided at the lower surface side opening of the through hole 5, 5A on which a solder ball or the like is attached.
  • the I / O terminals of the socket # 4 are not limited to the socket-shaped IZO pins 24, 24 #. Further, the IB I / O terminal is not limited to a pin-shaped terminal, and may be applied to, for example, a bump-like terminal.
  • a semiconductor package conversion module used when upgrading a semiconductor package mounted on a motherboard is relatively simple and involves high cost. It has a structure that allows the connection of the i Zo terminal without the need, and makes it possible to provide a module made of a compound having excellent flexibility.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

A semiconductor socket converter module having a simplified low-cost structure composed of a plurality of circuit boards of high connection reliability and adapted for replacement of I/O terminals, for example, to upgrade a semiconductor package on a motherboard. The module structure comprises a first circuit board provided with replacement connection circuits and having conductor pins for external connections on its lower side, a second circuit board carrying a semiconductor package on its upper side and having I/O terminals projecting downward and corresponding to the conductor pins for external connections, and a daughter board interposed between the first and second circuit boards and having conductor patterns connected with the replacement connection circuit and with particular ones of the I/O pins, the conductor pins for external connections being connected electrically with the particular I/O pins through the replacement connection circuit.

Description

明細書 半導 、。ッケージ変換モジュール 技術分野  Description Package Conversion Module Technical Field
本発明は、 例えばマザ一ボードに搭載された C P U (中央 S¾置) 機能を有する半導体 パッケージをアップグレ一ドするとき等に使用される半導体パッケージ変換モジュールに関 する。  The present invention relates to a semiconductor package conversion module used, for example, when upgrading a semiconductor package having a CPU (central S position) function mounted on a motherboard.
背景技術 Background art
パーソナルコンピュータ內のマザ一ボードには、 C PUとしての機能を有する半導体 ッ ケージがソケットを介して搭載されている。 このような半導^ ッケージとしては、 現在の ところ、 片側面に多数の I /Oピンが立設された P GA (ピングリッドアレイ) タイプが主 流を占めている。  A semiconductor package having a function as a CPU is mounted on a mother board of the personal computer via a socket. As such a semiconductor package, a PGA (pin grid array) type in which a large number of I / O pins are erected on one side is currently in the mainstream.
ところで、 パ一ソナノレコンピュータのユーザ一は、 の高速化を目的としたアップダレ —ドを望む^がある。 この^、 ソケットから既存の半導体パッケージを取り外し、 より 高機能な半導体パッケージを新たに搭載することが必要になる。 その際、 高機能な ^ ッケージを変換モジュールに装着したうえでマザ一ボード上のソケットに間接的に実装する ことがよいと提唱されている。 また、 最近ではより大幅なアップグレードのための変換モジ ユール ¾5tとして、 信号変換素子を し、 同素子により信号変換を行: ¾rるものが提案さ れるに至っている。  By the way, there are some users of personal computers who want to upgrade their computer speed. It is necessary to remove the existing semiconductor package from the socket and mount a more sophisticated semiconductor package. At that time, it is proposed that a high-performance package be mounted on the conversion module and then indirectly mounted on the socket on the motherboard. Recently, as a conversion module # 5t for a larger upgrade, a signal conversion element has been proposed, which performs signal conversion using the element.
従来の変換モジュールとしては、 半導体パッケージが搭載されるソケット S¾と、 I /O ピンの入 ^用回路を有する変換 S«とをその主要な構成要素としたものが提案されてい る。 変 板にはめつきされた複数のスノ ホールが設けられており、 それらの下面側開口 部には外部接続用ピンの 部が挿入されている。 なお、 これらの外部 用ピンはマザ一 ボード上のソケットに対して ¾1¾される。 ソケット¾¾は複数の I ZOピンを備えている。 これらの I /Oピンは、 ソケット¾¾の裏面倒において ήίΠ5めっきされた複数のスルーホ一 ルに対応した箇所に^されている。 各 Ι ΖΟピンは各めつきされたスルーホールに挿入さ れかつ半田付けされ、 これによりソケット 側と変換 側との電気的な導通が図られる。 なお、 これらの I ZOピンは自身の上端面に^ ¾^ ^ッケージの I /Oピンが嵌合される揷 通穴を持つソケット状ピンである。 As a conventional conversion module, a conversion module having a socket S¾ on which a semiconductor package is mounted and a conversion S «having a circuit for inputting I / O pins as main components has been proposed. A plurality of snow holes are provided on the transformer, and external connection pins are inserted into the openings on the lower surface. These external pins are {1} for the socket on the motherboard. Socket II has multiple IZO pins. These I / O pins are provided at locations corresponding to the multiple plated through holes in the back of the socket. Each pin is inserted into each of the plated through holes and soldered, so that electrical conduction between the socket side and the conversion side is achieved. Note that these IZO pins are socket-like pins having through holes on the upper end surface of which the I / O pins of the package are fitted.
そして、 このような構造を採用して特定の I Ζοピンについて入替接続を行うのである。 即ち、 信号変換素子を介して外部接続用ピンに接続すべき特定の Ι ΖΌピンについては、 対 応する箇所にあるス "ホールを介して外部 用ピンに直接導通させずに、
Figure imgf000004_0001
変換素子の入力側に接続してその出力側からの変換信号を上記外部接続用ピンに送るのであ る。
Then, by adopting such a structure, replacement connection is performed for a specific I Iο pin. That is, for the specific Ι す べ き pins to be connected to the external connection pins via the signal conversion element, the specific Ι ΖΌ pins are not directly conducted to the external pins via the corresponding holes,
Figure imgf000004_0001
It is connected to the input side of the conversion element and sends the conversion signal from the output side to the external connection pin.
ところが、 63ϋΙの入 続を!^する一般的な手法である、 リード線を半田付けする手法 では一連の煩雑な作業 ( 被覆されたリード線を所定長さに切断、 半田付け部の 被覆 の剥離、 予備はんだ付け、 位置決め及ぴ半田付け) が要求され、 性に劣るものとなる。 特に、 半導^^ッケ一ジのファイン化'多ピン化が進むと、 位置決め作業自体も困難になる ことが予想され、 さらに接 ^^性の低下にもつながることが予想される。  However, a 63km connection! A common technique for soldering lead wires involves a series of complicated operations (cutting a covered lead wire to a predetermined length, peeling off the coating of the soldered part, pre-soldering, positioning and positioning). Soldering) is required, resulting in poor properties. In particular, as the semiconductor package becomes finer and the number of pins increases, it is expected that the positioning operation itself will become difficult, and that it will also lead to a decrease in connectivity.
この他、 変 自体を多層化するという手^、 変 板にビルドアップ層を形成する という^ ¾によって入 «続を実現しょうとすると、 高コスト化を招くという問題がある。 従って、 低コスト化に対する要求に応じるためには、 両面板のように插カ単純な構造の変換 を TOすべきと考えられている。  In addition, there is a problem that if the connection is realized by means of multiplying the transformation itself or forming a build-up layer on the transformation board, the cost will be increased. Therefore, in order to meet the demand for cost reduction, it is considered that a simple structure such as double-sided board should be converted.
本発明は上記の課題を解決するためなされたものであり、 その目的は、 例えばマザ一ボー ドに搭載された^ ッケージをアップダレ一ドするときに使用される半導体パッケージ 変換モジュールにおいて、 比較的簡単にかつ高コスト化を伴うことなく I /Oピンの入龍 続を行うことができる構造を持ち、 しかも接^ 性に優れた半導^、'ッケージ変換モジュ ールを することにある。  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a relatively simple semiconductor package conversion module used for, for example, upgrading a package mounted on a motherboard. It is an object of the present invention to provide a semiconductor and package conversion module having a structure that allows connection of I / O pins easily and without increasing cost, and that has excellent connectivity.
発明の開示 Disclosure of the invention
第 1の発明は、 入替接続用回路が形成され下面側に外部接続用導体ピンを有する第 1の基 板と、 上面側に半導^ ッケージが搭載され、 前記外部接続用導体ピンに対応した位置で下 面側に矣出する I ZO端子を有する第 2の ¾Kと、 flB第 1の と前記第 2の S¾間に配 置されるとともに、 ΜίΙΒ入 続用回路と前記 I ΖΟ端子の特定の I ΖΟ端子とに接続され る導体パターンを有する子 とからなり、 tirts^部接続用導体ピンと ia特定の I /o端 子とは前記入替接続用回路を介して電気的に接続している半導体パッケージ変換モジュール である。 According to a first aspect of the present invention, the first connection board is formed with a replacement connection circuit and has an external connection conductor pin on the lower surface side, and a semiconductor package is mounted on the upper surface side, and corresponds to the external connection conductor pin. A second ¾K having an I ZO terminal which protrudes downward at the position, and a flB disposed between the first and the second S¾, and a connection circuit and identification of the IΖΟ terminal And a conductor having a conductor pattern connected to the I ΖΟ terminal of the ir, and the conductor pin for connecting the tirts ^ section and the ia specific I / o terminal are electrically connected via the replacement connection circuit. Semiconductor package conversion module It is.
第 2の発明は、 第 1の発明において、 前記第 1の基板はめつきされたスルーホールを有す る両面基板であって、 前記外部接続用導体ピンは前記スルーホールの下面側開口部に位置し、 IB特定の I /O端子は当該スルーホールの上面側開口部に前記子基板の絶縁基材を介して 位置する半導体パッケージ変換モジュールである。  A second invention is the double-sided board according to the first invention, having a through hole fitted with the first board, wherein the external connection conductor pin is located at an opening on the lower surface side of the through hole. The IB-specific I / O terminal is a semiconductor package conversion module located at the opening on the upper surface side of the through hole via the insulating base material of the daughter board.
第 3の発 ^は、 第 1の発明において、 前記第 1の基板上での前記子基板の位置は、 前記特 定の I ZO端子によりその垂直方向で規制され、 当該特定の I ZO端子に比べ突出長の大き な I zo端子の側面によりその水平方向で規制されている半導体パッケージ変換モジュール である。  According to the third aspect, in the first aspect, the position of the daughter board on the first board is regulated in a vertical direction by the specific IZO terminal, and the position of the child substrate is controlled by the specific IZO terminal. This is a semiconductor package conversion module that is restricted in the horizontal direction by the side of the Izo terminal, which has a relatively large protruding length.
第 4の発明は、 第 1の発明において、 前記子 の厚さが 0. 8 mm以下であり、 fffE導 、'ターンが、 l己特定の I に ¾ ^される前記子基板の外形端から Simて形成され た一次側パッドと、 ¾515入 続用回路側となる βίΠΒ子基板の外形端に形成された二次側パ ッドとを有する ^体パッケージ変換モジュールである。  In a fourth aspect based on the first aspect, the thickness of the child board is 0.8 mm or less, and the fffE conduction is turned from the outer edge of the child board to a specific I. This is a ^ package conversion module having a primary side pad formed by Sim and a secondary side pad formed at an outer edge of a β-element board which is a 515 connection circuit side.
麵) 麵)
上記第 1の発明では、 第 1の と第 2の 間に配置された子 の備える導 ^^ター ンを介して、 第 1の基板側の入替接続用回路及び入替接続を要する特定の I ZO¾fr子が電気 的に接続される結果、 特定の I /O端子についての入 続が行われる。 前記子 S¾にはあ らかじめ導 ターンが形成されているため、 例えばリード線を用いた^とは異なり、 所 定長さに切断したり絶縁被覆を剥 BTTる等、 面倒な作業が不要となる。  In the first invention, the first substrate-side replacement connection circuit and the specific IZO¾fr which require the replacement connection are provided via a lead turn provided in a child disposed between the first and second elements. As a result of the electrical connection of the terminals, connection to a specific I / O terminal is performed. Since the child S¾ has pre-formed turns, it does not require any troublesome work such as cutting to a predetermined length or stripping the insulation coating, unlike ^ using lead wires. Becomes
そして、 このような構成であると、 半導体パッケージ側の信号のうちの特定のものが、 前 記特定の I ZO端子を流れるとともに変 ¾¾¾に«された信号変 子等で変換された後、 マザ一ボード側に供給される。  With such a configuration, a specific one of the signals on the semiconductor package side flows through the specific IZO terminal and is converted by a signal modulator or the like that has been changed. Supplied to one board.
第 2の発明では、 第 1の S¾gが両面 ¾¾δのような単純な構造のもので足りることとなり、 高価でカゝっ製造煩雑な多層板やビルドアップ層に頼つて入 続を行う必要がなくなる。 よ つて、 髙コスト化カ s確実に回避される。  In the second invention, it is sufficient for the first S の も の g to have a simple structure such as 両 面 δ on both sides, and it is not necessary to rely on an expensive and cumbersome multilayer board or a build-up layer for connection. . Therefore, 化 cost reduction is surely avoided.
また、 子 はサブトラクティブ法によって形成された導 ίφ^ターンを の片側面 に有する片面 S«とすることもできるため、 であって比較的簡単に製造されることがで き、 これを用いたとしても特に高コスト化にはつながらない。 また、 変換 とソケット基板との間に子 を配置した 、 入 続を要する特定の I ZO端子の先端は、 rfB導 ターンのパッド上に載置された状態で位置決めされること ができる。 従って、 特定の I /O端子とパッドとを簡単にかつ確実に接続することができる。 このとき、 入 続を要しない他の I /O端子については、 対応する個々のめつきされたス ル一ホールの開口部に揷入されかつ同めつきされたスル一ホールとの導通が図られる。 その 反面、 I5特定の I ZOピンについては、 対応するめつきされたスル一ホールの開口部に挿 入されることはなく、 同めつきされたスルーホールから雜間して非導通の状態となる。 In addition, since the element can be a single-sided S «having a φφ turn formed by the subtractive method on one side of the element, it can be relatively easily manufactured. However, this does not lead to higher costs. In addition, the tip of the specific IZO terminal requiring connection, in which a child is arranged between the conversion and the socket board, can be positioned while being placed on the pad of the rfB conductive turn. Therefore, a specific I / O terminal and a pad can be easily and reliably connected. At this time, for the other I / O terminals that do not require connection, conduction is established with the corresponding through hole that is inserted into the corresponding through hole and the same through hole. Can be On the other hand, the I5 specific IZO pin is not inserted into the corresponding through-hole opening, and is in a non-conducting state because it intersects with the through-hole. .
第 3の発明では、 同子基板は I ZO端子により位置ずれ不能に保持されるため、 その位置 決め自体が極めて容易になる。 以上のことから本発明によると、 入 続を比較 単に行 うことができ、 しかも接^ ft頼性に優れたものとなる。  In the third invention, the same substrate is held by the IZO terminal so as not to be displaced, so that the positioning itself becomes extremely easy. From the above, according to the present invention, the connection can be simply performed, and the connection ft reliability is excellent.
し力もこのとき、 揷入可能部位にあるパッドが特定の I /O端子に対して位置決めされる ため、 両者を簡単にかつ確実に接続することができる。  At this time, since the pad at the insertable portion is positioned with respect to the specific I / O terminal at this time, the two can be easily and reliably connected.
第 4の発明では、 一次側パッドが子 ¾Kの外形端から «axた位置に形成されているから、 I ZO端子との■時に溶融半田が流出して第 1 上の導体パターンと短絡する危険が少 ない。 しカも、 子基板の厚さが 0. 8 mm以下であり、 かつ二次側パッドが子基板の外形端 に形成されているから、 第 1の基板上の導^、 'ターンへの電気的接続が容易である。  In the fourth invention, since the primary pad is formed at a position axax from the outer end of the child 子 K, there is a danger that molten solder will flow out at the time of contact with the IZO terminal and short-circuit with the first upper conductor pattern. Less is. Since the thickness of the sub-board is 0.8 mm or less and the secondary pad is formed at the outer edge of the sub-board, the electric conduction to the conductive and Connection is easy.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明を具体化した実施形態の変換モジュールの使用状態を説明するための概! ^Βϋ 面図、 図 2は同 ¾¾¾形態において使用される子 の平面図、 図 3は同実施形態の子 を 配置した状態を示す平面図、 図 4は同実施形態の変換モジュールの部分拡大断面図、 図 5は 同実施形態における分割される前の状態の子基板を示す平面図、 図 6は別例の子基板を BE置 した状態を示す平面図である。  FIG. 1 is a schematic diagram for explaining a use state of a conversion module according to an embodiment of the present invention. FIG. 2 is a plan view of a child used in the same embodiment, FIG. 3 is a plan view showing a state where the child of the same embodiment is arranged, and FIG. 4 is a partially enlarged cross-sectional view of the conversion module of the same embodiment. FIG. 5 and FIG. 5 are plan views showing a sub-substrate before being divided according to the same embodiment, and FIG.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明を具体化した一実施形餾の C P Uとしての機能を有する P G Aタイプの半導 ^ ッケージ変換モジュール 1を図 1〜図 5に基づき詳細に説明する。 Hereinafter will be described the present invention in detail with reference to FIGS. 1 to 5 the semiconductor ^ Kkeji conversion module 1 of the PGA type having a function as embodying CPU of one embodiment form餾.
図 1, 図 4に示されるように、 この実施形態の変換モジュール 1は、 P GA 2を信号変換 を行なったうえでマザ一ボード MBに搭 るための装置である。 変換モジュール 1は複数 の基板、 即ち変換基板 3及びソケット基板 4をその主要な構成要素としている。 As shown in FIGS. 1 and 4, the conversion module 1 of this embodiment converts the PGA 2 into a signal. This is a device for mounting on the motherboard MB after performing the above. The conversion module 1 has a plurality of boards, that is, a conversion board 3 and a socket board 4 as its main components.
第 1の としての変換 S¾ 3は、 矩形状をしたリジッドな両面 S¾である。 同変 m¾¾ 3は、 めっきされた複数のスルーホール 5を略口字状に配置してなるめっきされたスル一ホ —ル群を備えている。 図 3に示されるように、 各めつきされたスルーホール 5は一定のピッ チで千鳥状に配置されている。 図 4に示されるように、 各々のめつきされたスルーホール 5 の下面側開口部には、 外部接続用ピン 6の基端部が挿入されている。 このピン 6ははんだ付 けにより接合されていてもよい。  The first transformation S¾ 3 is a rectangular, rigid, double-sided S 矩形. The variation m¾¾3 includes a plated through hole group in which a plurality of plated through holes 5 are arranged in a substantially square shape. As shown in FIG. 3, each plated through-hole 5 is arranged in a staggered pattern with a fixed pitch. As shown in FIG. 4, the base end of the external connection pin 6 is inserted into the opening on the lower surface side of each of the attached through holes 5. This pin 6 may be joined by soldering.
めっきされたス ホール群によって包囲される略正方形状の領域には、 1つのダイパッ ド 7とそれを取り囲む複数のパッド 8とが形成されている。 ダイパッド 7上には、 信 ¾换 素子としての信号変翻 Q F P (クアツドフラットパッケージ) 9が表面実装されている。  One die pad 7 and a plurality of pads 8 surrounding the die pad 7 are formed in a substantially square region surrounded by the plated holes. A signal conversion QFP (quad flat package) 9 as a signal element is surface-mounted on the die pad 7.
Q F P 9の各リードは、 各パヅド 8に対して導電性材料であるはんだ S 1 を用いて接合され ている。 なお、 歸己パッド 8のうちの 1つは、 入 続用回路としての入替 用パッド 8 aとして割り当てられている。 Each lead of Q FP 9 is joined to each pad 8 using solder S 1 that is a conductive material. One of the return pads 8 is assigned as a replacement pad 8a as a connection circuit.
変 ¾¾¾3の上面側においてスルーホール群により包囲されていなレ、領域には、 電^ P品 接 のパッド 1 0が形成されている。 力かるパッド 1 0には D I P (デュアルインライン パッケージ) 1 1が表面実装されている。 変換 3の下面側にも電子部品 ¾ ^用パッド 1 2が形成されていて、 そこにはチッ: 抗 1 3が表面^されている。 これらの電子部品 1 1, 1 3も、 各パッド 1 0, 1 2に対していずれもはんだ S 1 を用いて接合されている。 ま た、 この変^ «3の上面及び下面には、 図示しない導体パターンが形成されている。 上記 の導体パターンは、 めっきされたスルーホール 5のランド 5 a, 5 b、 Q F P 9及び電子部 品 1 1, 1 3の相互間を電気的に接続している。  In the region not surrounded by the through-hole group on the upper surface side of the transformer 3, a pad 10 for electrical connection is formed in the region. DIP (dual in-line package) 11 is surface-mounted on the powerful pad 10. The electronic component 電子 ^ pad 12 is also formed on the lower surface side of the conversion 3, and the tip 13 is formed on the surface. These electronic components 11 and 13 are also joined to the pads 10 and 12 using solder S 1. In addition, a conductor pattern (not shown) is formed on the upper surface and the lower surface of the modification 3. The conductor pattern described above electrically connects the lands 5 a and 5 b of the plated through hole 5, the Q FP 9, and the electronic components 11 and 13 to each other.
この変換基板 3には図示しないミ二パイァホ一ルが形成されている。 ここでミ二パイァホ ールとは、 ピン掙通及び表裏の導通を目的とした通常のめっきされたスノ^-ホールよりも小 径 (数 Ι Ο μ πι φ ) であって、 表裏の導通のみを目的とするものを指す。 変換基板 3の上下 面を貫通するミ二バイァホールの上端には、 前記パッド 8のうち ffirie変換信号が出力される 側に該当するもの (図 1の 8 b) が電気的に接続されている。  On this conversion substrate 3, a not-shown mini-hole is formed. Here, the minor hole has a smaller diameter (several Ι Ο μπιφ) than a normal plated snow-hole for pin conduction and front-to-back conduction. For the purpose. The pad 8 (8b in FIG. 1) corresponding to the side on which the ffirie conversion signal is output is electrically connected to the upper end of the mini-via hole penetrating the upper and lower surfaces of the conversion board 3.
次に、 ソケット ¾¾4の構成について説明する。 図 1 , 図 4に示されるように、 第 2の基 板としてのソケット2¾4を構成する絶^¾¾"2 1は正方形状かつ枠状をしていて、 その外 形の大きさは»載物である PGA 2の大きさにほぼ等しい。 «¾†2 1〖±ΪΕ方形状の中 央孔 22を備えている。 このような中央孔 22を設けた理由は、 QFP 9の収容スペースを 確保するため、 はんだ付けを容易に行うため、 及び QFP 9の発する熱を効率よく放散する ためである。 従って、 前記中央孔 22は、 QFP9に対応する位置において当該 QFP9よ りも若干大きめに形成されることがよい。 Next, the configuration of the socket # 4 will be described. As shown in FIGS. 1 and 4, the absolute shape of the sockets 2-4 as the second substrate is square and frame-shaped, and the size of the outer shape is not limited to the load. Approximately equal to the size of PGA 2. «¾ † 2 1 〖± A central hole 22 is provided. The reason for providing the central hole 22 is to secure a space for accommodating the QFP 9, facilitate soldering, and efficiently dissipate the heat generated by the QFP 9. Therefore, the central hole 22 is preferably formed slightly larger than the QFP9 at a position corresponding to the QFP9.
中央孔 22の周囲には、 断面円形状であってその中央孔 22よりも遙かに小径のピン揷通 孔 23が多数かつ千鳥状に形成されている。 各ピン挿通孔 23には I/O端子としてのソケ ット状 IZOピン 24がそれぞれ揷通されている。 同 IZOピン 24の下端部は、 絶  Around the central hole 22, a large number of staggered pin through holes 23 having a circular cross section and a diameter much smaller than the central hole 22 are formed. Socket-shaped IZO pins 24 as I / O terminals are passed through the respective pin insertion holes 23. The lower end of the IZO pin 24 is
21の裏面側 (下面側) 力 突出している。 各ソケット状 ΙΖΟピン 24には、 軸線方向に 沿って延びる揷通穴 25が形成されている。 この揷通穴 25には PGA2側の I/Oピン 2 6が挿抜可能である。 即ち、 同ソケット基板 4は PG A 2が着脱可能な構造を表面側 (上面 側) に有している。 21 Back side (lower side) Force Projects. Each socket-like pin 24 has a through hole 25 extending in the axial direction. The I / O pins 26 on the PGA2 side can be inserted into and removed from the through holes 25. That is, the socket board 4 has a structure on the front side (upper side) on which the PGA 2 can be attached and detached.
説明の便宜上、 ソケット状 I/Oピン 24のうち、 入 続を要する特定の IZOピンを 24 Aで表わし、 入替接続を要しないその他の I/Oピン 24と区別する。 また、 特定の I ZOピン 24 Aに対応するめつきされたスルーホールを 5 Aで表わし、 それ以外のめっきさ れたスルーホール 5と区別する。  For convenience of description, of the socket-like I / O pins 24, a specific IZO pin requiring connection is represented by 24 A to distinguish it from other I / O pins 24 that do not require replacement connection. Also, the plated through-holes corresponding to the specific IZO pins 24 A are represented by 5 A to distinguish them from other plated through-holes 5.
めっきされたスノ ホール 5 Aの下面側開口部のランド 5 Abと、 上述のミニバイァホー ルの下端とは、 図示しない導体パターンにより導通されている。 従って、 QFP9の出力側 と ランド 5 A bとは電気的に接続されおり、 その様子は図 1の 矢印 A1 により概略 的に示されている。  The land 5 Ab at the opening on the lower surface side of the plated snow hole 5 A and the lower end of the above-mentioned mini via hole are electrically connected by a conductor pattern (not shown). Therefore, the output side of QFP9 and the land 5 Ab are electrically connected, and this is schematically indicated by the arrow A1 in FIG.
図 4に示されるように、 前記特定の I/Oピン 24 Aの小径部は、 他の1 0ピン24の 小径部に比べていくぶん短く形成されている。 従って、 入 ^を要しない他の I/Oピン 24をめつきされたスルーホール 5の上面側開口部に挿入した場合であっても、 特定の 1ノ Oピン 24 Aについては、 対応するめつきされたスルーホール 5 Aの上面側開口部に挿入さ れることがない。 このとき、 特定の IZOピン 24 Aは、 同めつきされたスノ ホール 5 A の上面側開口部のランド 5 A aから離間した状態となる。 即ち、 変 ¾S板 3と特定の IZO ピン 24 Aとの間には、 後述する子基板 36を挿入しうる隙間ができる。  As shown in FIG. 4, the small-diameter portion of the specific I / O pin 24A is formed to be somewhat shorter than the small-diameter portions of the other 10 pins 24. Therefore, even if another I / O pin 24 that does not need to be inserted is inserted into the opening on the top side of the plated through hole 5, the corresponding one pin It is not inserted into the opening on the upper surface side of the through hole 5A. At this time, the specific IZO pin 24A is separated from the land 5Aa of the upper opening of the snug hole 5A. That is, there is a gap between the modulation S plate 3 and the specific IZO pin 24A, into which a child substrate 36 described later can be inserted.
ήίΠ5特定の I ΖΟピン 24 Αは、 例えば入替接続を要しないその他の I 0ピン 24の小 径部を所定長さだけ切断することで得ることができる。 勿論、 長さの異なる 2種類の IZO ピン 24, 24 Αをあらかじめ作製しておき、 それらを用いても構わない。 I/Oピン 24 の/ h#部を折り曲げて、 己特定の I/Oピン 24 Aとして用いることも可能である。 図 1に示されるように、 マザ一ポ一ド MBにはあらかじめソケット 3 0がはんだ付けによ つて脱着不能に固定されており、 変換モジュール 1はこのソケット 3 0の上面側に搭載され た状態で使用される。 こめとき、 外部接 ピン 6は、 ソケット 3 0の有するソケット状ピ ン 3 1の挿通穴に挿通される。 なお、 部品交換を行う際の便宜を図るため、 当該接続部位に ははんだ付けがなされない。 {5 specific I pin 24} can be obtained, for example, by cutting a small-diameter portion of the other I 0 pin 24 that does not require replacement connection by a predetermined length. Of course, two types of IZO pins 24, 24 mm with different lengths may be prepared in advance and used. It is also possible to bend the / h # part of the I / O pin 24 and use it as a specific I / O pin 24A. As shown in FIG. 1, a socket 30 is fixed to the motherboard MB in advance so that it cannot be removed by soldering, and the conversion module 1 is mounted on the upper surface side of the socket 30. Used in. At this time, the external connection pin 6 is inserted into the insertion hole of the socket-shaped pin 31 of the socket 30. Note that, for the sake of convenience when replacing parts, soldering is not performed on the connection site.
本 形態の変換モジュール 1は、 変換 3及びソケット 4に加えて、 さらに子基 板 3 6をその構成要素としている。 以下、 その子 ¾¾ 3 6の構造について説明する。  The conversion module 1 of the present embodiment includes a sub board 36 in addition to the conversion 3 and the socket 4. Hereinafter, the structure of the child 36 will be described.
図 2等に示されるように、 本実施形態の子基板 3 6は、 絶緣基材 3 7の片側面に導^ タ —ン 3 8を備える。 前記導体パターン 3 8は、 従来公知のサブトラクティブ法によって形成 されたものであることがよい。 ここで使用されている絶^ 3 7は長方形状かつリジッド なものであって、 0 . 8 ranの厚さを有している。 図 3に示されるように、 ί¾ϋ¾ ί 3 7の幅 W1 は、 I /Oピン 2 4のピッチ (例えば 2 . 5 4 mm, 1 . 2 7面) よりも若干小さめに設 定されている。 よって、 ί&^¾¾· 3 7の一部 (即ち挿入可能雜 P 1 ) は、 入 ^を要し な 数の Iノ Oピン 2 4間に無理なく挿入されることができる。  As shown in FIG. 2 and the like, the sub-substrate 36 of the present embodiment is provided with a conductor 38 on one side of an insulating base material 37. The conductor pattern 38 is preferably formed by a conventionally known subtractive method. The absolute 37 used here is rectangular and rigid, and has a thickness of 0.8 ran. As shown in FIG. 3, the width W1 of the pin 37 is set to be slightly smaller than the pitch of the I / O pins 24 (for example, 2.54 mm, 1.27 plane). Therefore, a part of ί & ^ ¾¾ · 37 (that is, the insertable element P 1) can be inserted between the I / O pins 24 of a number that does not require insertion.
導体パターン 3 8は絶^ ¾材 3 7の長手方向に沿って延びるように形成されている。 導体 パター 3 8の一端には一次側パッド 3 9が形成され、 他端には二次側パッド 4 0が形成さ れている。 一次側パッド 3 9は円形状であって、 絶縁 3 7における掙入可能部位 P 1 の 略中央部に位置している。 二次側パッド 4 0は矩形状であって、 絶^ 7の TOに位置 している。 はんだ付け部分の ¾^fi¾性の向上という観点からすると、 これらのパッド 3 9 , 4 0は極力大きく形成されることがよい。 ただし、 一次側パッド 3 9については、 その直径  The conductor pattern 38 is formed so as to extend along the longitudinal direction of the insulating material 37. A primary pad 39 is formed at one end of the conductor pattern 38, and a secondary pad 40 is formed at the other end. The primary side pad 39 has a circular shape and is located substantially at the center of the insertable portion P 1 in the insulation 37. The secondary pad 40 has a rectangular shape and is located at the absolute TO. From the viewpoint of improving the fififiability of the soldered portion, it is preferable that these pads 39 and 40 are formed as large as possible. However, the primary pad 39 has its diameter
7の幅 W1 よりもひとまわり小さく設定されていることがよい。 一次側パッド 3 9と I ZOピン 2 4との当接によるショートを^^に防止するためである。  It is better to be set a little smaller than the width W1 of 7. This is to prevent a short circuit caused by contact between the primary pad 39 and the IZO pin 24.
上記の子 ¾« 3 6は、 1枚の板材から、 いわゆる ^個どりで «されることが好ましい。 図 5には、 その際に用いられる多数個どり用ボード B 1 の一例が示されている。  The above-mentioned children 36 are preferably formed in a so-called “single” manner from one plate material. FIG. 5 shows an example of the multi-piece board B 1 used at that time.
図 3に示されるように、 導体パターン 3 8を備える子 3 6は、 两 £« 3 , 4間に記置 された状態で使用される。 その際、 子 ¾¾ 3 6のパターン形成面はソケット ¾¾ 4側に向け られる。 子 ¾S 3 6のパターン形成面を変換 S¾ 3側に向けた 、 ある程度のスペースを 設けないと、 導 ターン 3 8等がランド 5 a , 5 A aと接触してショートすることがあり うるからである。 両 3 , 4間に配置された子 3 6は、 I ZOピン 2 4の外周面に対 して当接することにより、 自身の面方向^ ί立置ずれ不能な状態に される。 この^、 位 置決めの確割ヒという観点からすると、 子基板 3 6は複数本の I ZOピン 2 4に対して当接 する (または当接可能) であることがよい。 本実施形態では、 図 3に示されるように、 子基 板 3 6が 5本の I ZOピン 2 4に対して当接する構成となっている。 より具体的にいうと、 前記 5本の I /Oピン 2 4のうち 1本が子 3 6の挿入側短辺に当接する。 さらに残りの 4本の I ZOピン 2 4のうちの 2本が子基板 3 6の長辺のうちの一方側に当接し、 別の 2本 が: ¾2のうちの他方側に当接している。 従って、 この子 3 6はいわば 3方向から位^ めされている。 As shown in FIG. 3, the child 36 provided with the conductor pattern 38 is used in a state where it is placed between the terminals 3 and 4. At this time, the pattern formation surface of the child # 36 is directed toward the socket # 4. If the pattern formation surface of the child S36 faces the conversion S¾3 side, if there is not enough space, the conductors 38, etc. may come into contact with the lands 5a, 5Aa and short-circuit. is there. The child 36 disposed between the two 3 and 4 is brought into contact with the outer peripheral surface of the IZO pin 24 so that it cannot be displaced in its own plane. This ^, place From the viewpoint of securing the placement, it is preferable that the daughter board 36 be in contact with (or be capable of contacting) a plurality of IZO pins 24. In the present embodiment, as shown in FIG. 3, the sub-board 36 comes into contact with the five IZO pins 24. More specifically, one of the five I / O pins 24 abuts on the insertion side short side of the child 36. Further, two of the remaining four IZO pins 24 are in contact with one of the long sides of the sub board 36, and the other two are in contact with the other side of: ¾2 . Therefore, this child 36 is positioned from three directions.
このような位置決め状態においては、 図 4に示されるように一次側パッド 3 9は、 ちょう ど 特定の I /Oピン 2 4 Aの真下、 カゝっ前記めつきされたス V "ホール 5 Aの真上の位 置をとる。 このとき、 I /Oピン 2 4 Aの先端は一次側パッド 3 9上に ¾gされた状態とな る。 一方、 二次側パッド 4 0は変換 ¾tK3上の入 ^^パッド 8 aに対応した位置をとる。 そして、 ともにはんだ S 1 を用いて、 特定の I /Oピン 2 4 Aの先端と一次側パッド 3 9 とが接合され、 二次側パッド 4 0との入 翻パッド 8 aとが接合されている。  In such a positioning state, as shown in FIG. 4, the primary side pad 39 is located just below the specific I / O pin 24 A, and is provided with the V “hole 5 A” just above the pin. At this time, the tip of the I / O pin 24 A is in a state of being 9g on the primary pad 39. On the other hand, the secondary pad 40 is on the conversion 変 換 tK3. Input ^^ Take the position corresponding to the pad 8a, and use the solder S1 to join the tip of the specific I / O pin 24A and the primary pad 39 to form the secondary pad 4a. Transposition pad 8a with 0 is joined.
次に、 この変換モジュール 1を製造する方法の一例を紹介する。  Next, an example of a method for manufacturing the conversion module 1 will be introduced.
まず、 変換 ¾¾ 3、 ソケット ¾¾4及び子 ¾Ιδ 3 6をあらかじめmしておく。 変^^ 3は、 例えばガラスエポキシ製絶^ Wの两面に銅箔を貼着してなる銷張積層板を出発材料 とし、 サブトラクティブ法等のような従 知のパターン形成を行うことで得ることができ る。 それにより、 絶縁基材にはめつきされたスルーホール 5, 5 A、 ミニバイァホール、 ダ ィパッド 7、 パッド 8, 8 a , 8 b等が形成される。 ソケット は、 枠状の iifeig¾it2 1にピン揷通孔 2 3を透設した後、 それらに対してソケット状 I /Oピン 2 4を揷入するこ とで得ることができる。 そして、 ソケット状 1ノ0ピン 2 4のうち特定のものの/ J を所 定長さだけ切断し、 特定のソケット状 I ZOピン 2 4 Aとする。 子 ¾¾ 3 6は、 例えばガラ スエポキシ^ ^ ^の片面に銅箔を貼着してなる銅張積層板を出発材料として、 サブトラ クティブ法により作製される。 »個どりの には、 多数個どり用ボード B 1 を図 5の破 線に沿って分割し、 必要な数だけ子 3 6を得ればよい。  First, the conversion ¾¾3, the socket 及 び 4, and the child ¾Ιδ36 are prepared in advance. The variation 3 can be obtained by forming a known pattern such as a subtractive method using, as a starting material, a stretched laminate obtained by sticking a copper foil to a surface of a glass epoxy insulated material W, for example. be able to. As a result, through-holes 5, 5A, mini-via holes, dipads 7, pads 8, 8a, 8b, etc., are formed on the insulating base material. The socket can be obtained by piercing the pin-through holes 23 in the frame-shaped iifeig 21 and then inserting the socket-shaped I / O pins 24 into them. Then, / J of a specific one of the socket-shaped pins 1 and 24 is cut by a predetermined length to obtain a specific socket-shaped IZO pin 24A. The child 36 is manufactured by a subtractive method using, for example, a copper-clad laminate obtained by attaching a copper foil to one surface of glass epoxy ^^^. »In order to divide the pieces, the board for multiple pieces B 1 is divided along the broken lines in FIG.
続く第 1のピン立て工程では、 変換基板 3の各めつきされたスルーホール 5, 5 Aの下面 側開口部に対して、 外部接^ピン 6の 部をプレスで圧入する。  In the subsequent first pin setting step, the external connection pin 6 is press-fitted into the opening on the lower surface side of each of the through holes 5 and 5 A on the conversion board 3.
続ぐはんだ印刷工程では、 スクリーン印刷の手法によって、 変換基板 3の上面側に位置す るめつきされたスル一ホール 5のランド 5 aにクリ一ムはんだを印刷する。  In the subsequent solder printing process, a cream solder is printed on the land 5a of the through hole 5 located on the upper surface side of the conversion board 3 by screen printing.
変 ¾¾¾3の上面側は、 外部赚用ピン 6が突出している下面側とは異なりフラットなため、 印刷に適しているからである。 このとき、 QFP 9を包囲する各パッド 8, 8 a, 8 bにも クリームはんだが印刷される。 Since the top side of the transformer 3 is flat unlike the bottom side where the external input pins 6 protrude, This is because it is suitable for printing. At this time, cream solder is also printed on the pads 8, 8a, 8b surrounding the QFP 9.
続く第 2のピン立て工程では、 変換基板 3のめつきされたスルーホール 5の上面側開口部 に対して各ソケット状 IZOピン 24の先端部を揷通させるとともに、 ダイパッド 7上に Q FP 9を固定する。  In the subsequent second pin setting step, the tip of each socket-like IZO pin 24 is passed through the opening on the upper surface of the through hole 5 to which the conversion board 3 is attached, and the QFP 9 is placed on the die pad 7. Is fixed.
続くリフロー工程では、 ソケット を搭載した変 板 3をリフロー炉内にセットし た後、 クリームはんだが融点する fi¾付近まで炉内の を上昇させ、 はんだ S1 を さ せる。 したはんだ S1が冷えて硬化すると、 ソケット状 IZOピン 24がめつきされた スノ "ホール 5に接合され、 力つ QFP 9の各リードが各パッド 8, 8a, 8 bに接合され る。  In the subsequent reflow process, after setting the transformer 3 equipped with the socket in the reflow furnace, the temperature in the furnace is raised to around fi¾ where the cream solder melts, and the solder S1 is discharged. When the solder S1 has cooled and hardened, the socket-shaped IZO pin 24 is joined to the attached hole 5, and the leads of the QFP 9 are joined to the pads 8, 8a, 8b.
次に、 子 S¾36の挿入可能 SBfePlを IZOピン 24間に挿入する。 子 ¾«36は、 例 えばソケット¾¾ 4の中央孔 22を介して揷入されることができる (図 1の Hi矢印 A2参 照) 。 そして、 I/Oピン 24間への挿入で のごとく位置決めされた子 ¾K 36を、 は んだ S1 を用いて個別にはんだ付けする。 その際、 同時に電子部品 11, 13を対応するそ れぞれのパッド 10, 12に対して個別にはんだ付けする。  Next, the insertable SBfePl of the child S # 36 is inserted between the IZO pins 24. The child 36 can be inserted, for example, through the central hole 22 of the socket 4 (see Hi arrow A2 in FIG. 1). Then, the child ¾K 36 positioned as indicated by the insertion between the I / O pins 24 is individually soldered using the solder S1. At this time, the electronic components 11 and 13 are soldered individually to the corresponding pads 10 and 12 at the same time.
以上のようにして所望の変換モジュール 1を完成させた後、 その変換モジュール 1に P G Α2を搭載し、 さらにそれをマザ一ボード MBのソケット 30に搭軟する。 このようにして ^すると、 主として QFP 9によって信号変換が図られ、 PG A 2本来の機能を充分に発 揮させることができる。  After the desired conversion module 1 is completed as described above, the PG # 2 is mounted on the conversion module 1, and the PG # 2 is mounted on the socket 30 of the motherboard MB. By doing so, the signal conversion is mainly performed by the QFP 9, and the original function of the PGA 2 can be sufficiently exerted.
さて、 以下に本実施形態において特徴的な作用効果を列挙する。  Now, the characteristic effects in the present embodiment will be listed below.
(ィ) この変換モジュール 1では、 両基板 3, 4間に配置された子基板 36の備える導体 パターン 38を介して、 入 続用パッド 8 a及び入 続を要する特定の I /Oピン 24 Aが電気的に接続される。 その結果、 特定の I/Oピン 24 Aについての入替接続が行われ る。 即ち、 当該特定の I/Oピン 24 Aについては、 対応するめつきされたスルーホール 5 Aを介して外部換暁用ピン 6に直接導通されるのではなく、 QFP 9等を経由して信号変換 されたうえで同外部接続用ピン 6に間接的に導通される。 子 36にはあらかじめ導体パ ターン 38が形成されているため、 例えばリード線を用いた とは異なり、 所定長さに切 断したり 被覆を剥離する等、 面倒な が不要となる。 また、 リジッドな子 ¾«36は、 リ一ド線とは異なり定型的であるので、 I ZOピン 24に当接させることで位置ずれ不陡に 保持される。 このため、 位置決め自体が棰めて容易になる。 以上のことから、 本 形態に よると入替^ ^を比較的簡単に行うことができ、 その製造にあたって作業性の向上を図るこ とができる。 (A) In this conversion module 1, the connection pads 8a and the specific I / O pins 24A required for connection are provided via the conductor pattern 38 of the child board 36 disposed between the two boards 3 and 4. Are electrically connected. As a result, a swap connection is made for the specific I / O pin 24A. In other words, the specific I / O pin 24 A is not directly conducted to the external conversion pin 6 through the corresponding plated through hole 5 A, but is converted into a signal through the QFP 9 or the like. After that, it is indirectly connected to the external connection pin 6. Since the conductor pattern 38 is formed on the terminal 36 in advance, unlike a case where a lead wire is used, troublesome operations such as cutting to a predetermined length or peeling off the coating are not required. In addition, the rigid child 36 is fixed, unlike the lead wire, so that the rigid child 36 abuts on the IZO pin 24 and is kept in position. For this reason, the positioning itself becomes very easy. From the above, this form According to this, replacement can be performed relatively easily, and workability can be improved in the manufacture thereof.
(口) さらに、 本実施形態の変換モジュール 1では、 変換鎌 3が両面板という単純な構 造のもので足りることとなり、 多層板やビルドアップ層に頼つて入 ^続を行う必要がなく なる。 よって、 入 ^暁を行うに際しても、 高コスト化を確実に回避することができる。  (Mouth) Furthermore, in the conversion module 1 of the present embodiment, the conversion sickle 3 only needs to have a simple structure of a double-sided board, and it is not necessary to rely on a multilayer board or a build-up layer for connection. . Therefore, it is possible to reliably avoid high costs when performing the entry.
(ハ) また、 子 3 6はサブトラクティブ法によって形成された導 ターン 3 8を絶 mf 3 7の片側面に有する片面板であるため、 飾であって比較的簡単に i¾tされること ができる。 よって、 これを用いたとしても特に高コスト化にはつながらない。 さらに本実施 形態において使用している子基板 3 6は、 変換基板 3やソケット基板 4に比べて面猪が格段 に小さい。 しかも、 力かる子 ¾¾ 3 6は、 多数個どりによって 1枚の板材から多量に得るこ とができる。 以上のことも高コスト化の防止に貢献している。 なお、 本^ ¾形態のように子  (C) In addition, since the child 36 is a single-sided plate having the pattern 38 formed by the subtractive method on one side of the mf 37, it is a decoration and can be relatively easily adjusted. . Therefore, even if this is used, it does not lead to particularly high cost. Furthermore, the sub board 36 used in the present embodiment is much smaller than the conversion board 3 and the socket board 4. Moreover, a large number of powerful children 子 36 can be obtained from a single plate material by a large number of pieces. The above also contributes to prevention of cost increase. It should be noted that child like this ^^ form
6を長方形状にしておけば、 «個どりを^ ¾する際に好都合となる。  If 6 is made to be rectangular, it is convenient for «individually ^^».
(= -) 本実施形態では、 入 続を要する特定の I /Oピン 2 4 A力 入 続を要しな い他の I ZOピン 2 4に比べて短く形成されている。 ゆえに、 両基板 3 , 4間に子基板 3 6 を配置した場合、 特定の I ΖΟピン 2 4 Αの先端は、 導体パターン 3 8の一次側パッド 3 9 上に載置した状態で位置決めされる。 従って、 両者 2 4 A, 3 9を簡単にかつ確実に接続す ることができる。,  (=-) In the present embodiment, the specific I / O pin 24 A which requires connection is formed shorter than other IZO pins 24 which do not require connection. Therefore, when the child board 36 is arranged between the two boards 3 and 4, the tip of the specific I pin 24 is positioned while placed on the primary pad 39 of the conductor pattern 38. . Therefore, both 24 A and 39 can be easily and reliably connected. ,
なお、 本発明は上記 形態に限定されることはなく、 例えば次のような形態に変更する ことが可能である。  Note that the present invention is not limited to the above-described embodiment, and for example, can be changed to the following embodiment.
◎ 導 、°ターン 3 8を 1つのみ備える子 S¾3 6に限定されることはなく、 複数備える ものであってもよい。 また、 長方形状の子 S« 3 6に限定されることはなく、 それ以外の形 状であってもよい。 例えば、 図 6に示される別例の子 4 1は略コ宇状であって、 その片 側面には導体パターン 3 8が 2つ設けられている。 各々の導体パターン 3 8の両端には、 一 次側パッド 3 9及び二次側パッド 4 0が形成されて ゝる。  ◎ Induction, the child is not limited to the child S¾36 having only one ° -turn 38, and may have a plurality of children. Further, the present invention is not limited to the rectangular child S <b> 36, and may have other shapes. For example, another example of the child 41 shown in FIG. 6 has a substantially U-shape, and two conductor patterns 38 are provided on one side thereof. A primary pad 39 and a secondary pad 40 are formed at both ends of each conductor pattern 38.
◎ 子 ¾¾ 3 6はリジッドなものに限定されることはなく、 肉薄かつフレキシブルなもの でもよい。 このようにすると変換 ¾¾3の上面との段差が小さくなるため、 はんだ S 1 が確 実に被りやすくなり、 二次側パッド 4 0に対するはんだ付けが楽になる。 このことは接^? 頼性のさらなる向上につながる。  ◎ Child ¾¾ 36 is not limited to rigid ones, but may be thin and flexible. By doing so, the step with the upper surface of the converter # 3 is reduced, so that the solder S1 is surely easily applied and soldering to the secondary pad 40 becomes easier. This leads to a further improvement in reliability.
◎ 変換基板 3の下面側に立設された外部接続用ビン 6に代えて、 例えばはんだボール等 をめつきされたスルーホール 5, 5 Aの下面側開口部に設けてもよい。 ◎ ソケット ¾¾4の備える I /O端子はソケット状 I ZOピン 2 4, 2 4 Αに限定され ることはなく、 例えばソケット状でないものであってもよい。 また、 IB I /O端子はピン 形状のものに限らず、 例えばバンプのようなものに適用されうる。 ◎ Instead of the external connection bin 6 erected on the lower surface side of the conversion board 3, for example, a solder ball or the like may be provided at the lower surface side opening of the through hole 5, 5A on which a solder ball or the like is attached. ◎ The I / O terminals of the socket # 4 are not limited to the socket-shaped IZO pins 24, 24 #. Further, the IB I / O terminal is not limited to a pin-shaped terminal, and may be applied to, for example, a bump-like terminal.
◎ itrfS実施形態においては、 子基板 3 6や各種電子部品 1 1, 1 3を個別はんだ付けに よって実装する方法を採用していた。 これに代えて、 Q F P 9等をはんだ付けする際に同時 にそれらを一括はんだ付けすることも許容される。  ◎ In the itrfS embodiment, the method of mounting the daughter board 36 and the various electronic components 11 and 13 by individual soldering was adopted. Alternatively, when soldering the QFP9 etc., it is also acceptable to solder them all together.
ここで、 請求の範囲に記載された発明のほかに、 前述した Hffi形態によって される技 術的思、想をその効果とともに以下に列挙する。  Here, in addition to the inventions described in the claims, the technical ideas and ideas achieved by the above-described Hffi form are listed below together with their effects.
( 1 ) 第 1の発明から第 4の発明のいずれかにおいて、 前記子基板は 0 . 8鹏厚以下で ある半導体パッケージ変換モジュール。 この構成であると、 段差が小さくなるため、 はんだ
Figure imgf000013_0001
(1) The semiconductor package conversion module according to any one of the first to fourth inventions, wherein the daughter board has a thickness of 0.8 mm or less. With this configuration, the step is small, so the solder
Figure imgf000013_0001
( 2 ) 第 1の発明から第 4の発明のいずれかにおいて、 前記第 2の基板は前記信号変換素 子に対応する位置に中央孔を有することを特徴とする、 半導体パッケージ変換モジュール。 この構成であると、 子 S¾を所定位置に挿入しやすくなり 性が向上する。  (2) The semiconductor package conversion module according to any one of the first to fourth inventions, wherein the second substrate has a center hole at a position corresponding to the signal conversion element. With this configuration, the child S¾ can be easily inserted into a predetermined position, and the operability is improved.
産業上の利用可能性 Industrial applicability
以上詳述したように、 本発明によれば、 例えばマザ一ボードに搭載された半導体パッケ一 ジをァップグレードするときに使用される半導体パッケージ変換モジュールにおいて、 比較 的簡単にかつ高コスト化を伴うことなく i Zo端子の入 続を行うことができる構造を持 ち、 しカゝも^ 性に優れた複^ ¾からなるモジュールを^することができる。  As described above in detail, according to the present invention, for example, a semiconductor package conversion module used when upgrading a semiconductor package mounted on a motherboard is relatively simple and involves high cost. It has a structure that allows the connection of the i Zo terminal without the need, and makes it possible to provide a module made of a compound having excellent flexibility.

Claims

請求の範囲 The scope of the claims
1 . 入替接続用回路が形成され下面側に外部接続用導体ピンを有する第 1の基板と、 上面 側に半導体パッケージが搭載され、 爾 s^v部接続用導体ピンに対応した位置で下面側に 突出する I ZO端子を有する第 2の ¾ ^と、 IS第 1の と fris第 2の 間に配置 されるとともに、 前記入 ¾ 回路と前記 Iノ O端子の特定の I /o端子とに SS^さ れる導体パターンを有する子 とからなり、 IE^部接^ ffl導体ピンと βίπε特定の I ζο端子とは前記入 続用回路を介して電気的に接続してレヽる半導 、'ッケージ変換 モジユーノレ。 1. A first substrate on which a replacement connection circuit is formed and which has external connection conductor pins on the lower surface, and a semiconductor package mounted on the upper surface, and a lower surface at a position corresponding to the s ^ v connection conductor pin. A second ¾ ^ having an I ZO terminal protruding from the first input terminal and a second I / O terminal between the first input terminal and the fris second terminal; A semiconductor having a conductor pattern that is connected to an electrode, and an IE connection part ffl conductor pin and a βίπε specific Iζο terminal are electrically connected through the connection circuit to form a semiconductor, package. Transformation module.
2. 第 1の発明において、 前記第 1の基板はめつきされたスルーホールを有する両面基板 であって、 前記外部接続用導体ピンは前記スルーホールの下面側開口部に位置し、 前記 特定の I ΖΟ端子は当該スルーホールの上面側開口部に前記子基板の絶 ^¾材を介して 位置する半導体パッケージ変換モジュール。 2. In the first invention, there is provided a double-sided board having a through-hole fitted with the first board, wherein the external connection conductor pin is located at an opening on the lower surface side of the through-hole, The semiconductor package conversion module, wherein the terminal is located at the opening on the upper surface side of the through hole via the insulating material of the child substrate.
3 . 第 1の発明において、 前記第 1の基板上での前記子基板の位置は、 前記特定の I /O 端子によりその垂直方向で規制され、 当該特定の I ΖΟ端子に比べ突出長の大きな I / ο端子の側面によりその水平方向で規制されている半導体パッケージ変換モジュール。  3. In the first invention, the position of the daughter board on the first board is regulated in the vertical direction by the specific I / O terminal, and has a larger protrusion length than the specific I / O terminal. A semiconductor package conversion module that is regulated in the horizontal direction by the side of the I / ο terminal.
4. 第 1の発明において、 前記子基板の厚さが 0 . 8 mm以下であり、 前記導体パターン 力 前記特定の I zo端子に接続される itriE子 の外形端から amて形成された一次 側パッドと、 前記入 回 となる前記子 の外形端に形成された二次側パッ ドとを有する半導体パッケージ変換モジュール。  4. In the first invention, the thickness of the daughter board is 0.8 mm or less, and the conductor pattern is a primary side formed at am from an outer end of the itriE daughter connected to the specific Izo terminal. A semiconductor package conversion module, comprising: a pad; and a secondary pad formed at an outer end of the child serving as the input.
PCT/JP1999/000005 1998-01-06 1999-01-05 Semiconductor package converter module WO1999035689A1 (en)

Priority Applications (1)

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JP105998A JP3404275B2 (en) 1998-01-06 1998-01-06 Module comprising a plurality of substrates and method of manufacturing the same
JP10/1059 1998-01-06

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04144258A (en) * 1990-10-05 1992-05-18 Nec Corp Sub-substrate mounting type lsi socket
JPH08227970A (en) * 1995-02-21 1996-09-03 Nec Kyushu Ltd Semiconductor circuit module
JPH10261758A (en) * 1997-03-21 1998-09-29 Ibiden Co Ltd Conversion module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04144258A (en) * 1990-10-05 1992-05-18 Nec Corp Sub-substrate mounting type lsi socket
JPH08227970A (en) * 1995-02-21 1996-09-03 Nec Kyushu Ltd Semiconductor circuit module
JPH10261758A (en) * 1997-03-21 1998-09-29 Ibiden Co Ltd Conversion module

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JP3404275B2 (en) 2003-05-06
JPH11195748A (en) 1999-07-21

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