WO1999025018A1 - Dispositif de semi-conducteur comportant une region d'isolation amelioree et procede de fabrication de celui-ci - Google Patents

Dispositif de semi-conducteur comportant une region d'isolation amelioree et procede de fabrication de celui-ci Download PDF

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Publication number
WO1999025018A1
WO1999025018A1 PCT/US1998/010178 US9810178W WO9925018A1 WO 1999025018 A1 WO1999025018 A1 WO 1999025018A1 US 9810178 W US9810178 W US 9810178W WO 9925018 A1 WO9925018 A1 WO 9925018A1
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WIPO (PCT)
Prior art keywords
substrate
implanted
species
trench
implant
Prior art date
Application number
PCT/US1998/010178
Other languages
English (en)
Inventor
Charles E. May
Robert Dawson
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1999025018A1 publication Critical patent/WO1999025018A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

  • the present invention is directed generally to semiconductor devices and, more particularly, to a semiconductor device having an improved isolation region and process of fabrication thereof.
  • MOS metal-oxide-semiconductor
  • CMOS complimentary MOS
  • BiCMOS bipolar CMOS
  • Each of these semiconductor devices generally include a semiconductor substrate on whicn a number of active devices are formed.
  • the particular structure of a given active device can vary between device types.
  • an active device generally includes source and drain regions and a gate electrode which modulates current between the source and drain regions.
  • an active device In bipolar transistors, an active device generally includes a base, a collector, and an emitter.
  • Semiconductor devices like the ones mentioned above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral and vertical dimensions of the device structure.
  • isolation regions i.e., regions in the substrate which are used to electrically isolate adjacent active devices.
  • LOCOS for LOCal Oxidation of Silicon
  • Trench isolation techniques and many LOCOS isolation techniques, generally involve the formation of a trench in the substrate. In most cases, an oxide layer is grown in the trench to form at least part of the isolation region. In trench isolation, a second layer of oxide may be deposited over the grown oxide layer to completely fill the trench.
  • FIG. 1 An isolation region formed using conventional trench isolation techniques is shown in Figure 1.
  • One limitation in particular is the high stresses imparted on portions of the substrate 101 which define the trench 103. These stresses are often caused by growth of the thermally-grown oxide layer and are typically greatest at the corner portions 105 of the trench 103. These stresses have a deleterious impact on device performance and reliability.
  • a more detailed discussion of LOCOS and trench isolation techniques as well as the substrate stresses resulting therefrom can be found in S. Wolf, Silicon Processing For The VLSI Era , Vol. 2: Processing Integration, Chap. 2, pp. 28-58, 1990. Summary of the Invention
  • the present invention relates to a semiconductor device having an improved isolation region and a process for fabricating such a semiconductor device.
  • isolation regions can be formed with reduced substrate stresses as compared to conventionally formed isolation regions.
  • a process of forming a semiconductor device consistent with one embodiment of the present invention includes forming at least one isolation trench in a substrate.
  • An implant species is then implanted into portions of the substrate defining an edge portion of the isolation trench, and an oxide is grown in the trench using the implanted substrate portions.
  • the implant species may, for example, be an inert species, such as a nitrogen- or silicon-bearing species, for example.
  • the implant species is implanted such that the grown oxide grows as least as fast in the implanted substrate portions as in other substrate portions which are not implanted with the implant species.
  • a process of forming a semiconductor device in which a mask is formed over a substrate to selectively expose at least one isolation region. A portion of the substrate is then selectively removed in the isolation region to form an isolation trench. An implant species is implanted into edge portions of the isolation trench to damage a layer of the substrate which defines the edge portions. An oxide layer is then grown in the trench using the damaged layer of the substrate. Subsequently, the mask is removed.
  • a dielectric layer may be formed over the grown oxide layer prior to removing the mask.
  • a semiconductor device consistent with the embodiment of the invention includes a substrate defining at least one isolation trench therein.
  • the isolation trench has a rounded upper corner portion defined by portions of the substrate.
  • the substrate portions defining the trench may further have reduced stresses as compared to conventionally-formed isolation trenches .
  • Figure 1 illustrates a conventional isolation region
  • FIGS. 2A-2F illustrate a fabrication process in accordance with one embodiment of the invention.
  • the present invention is believed to be applicable to a number of semiconductor devices (such as MOS, CMOS, and BiCMOS devices, for example) which employ isolation regions to separate active device regions.
  • the present invention is applicable to those devices having isolation regions formed using trenches. While the present invention is not so limited, an appreciation of various aspects of the invention will be gained through a discussion of the fabrication process in connection with the examples provided below.
  • Figures 2A-2F illustrate a process for fabricating an isolation region of a semiconductor substrate by implanting an implant species into portions of an isolation trench.
  • the example embodiment will illustrate use of the invention using a trench isolation technique. The invention however is not so limited.
  • a mask 203 is formed over a substrate 201 and selectively removed to expose regions of the substrate 201.
  • the substrate 201 is typically formed from silicon.
  • the mask 203 may be formed from a variety of different materials, or combination of materials including, for example, a photoresist or a patterned nitride layer.
  • the mask 203 includes a nitride masking layer 205 and a thin pad oxide layer 207 which insulates the nitride masking layer 205 from the surface of the substrate 201. Formation of the pad oxide layer 207 and the nitride masking layer 205 may be done using, for example, well- known techniques. The resultant structure is illustrated in Figure 2A.
  • the areas 204 of the substrate 201 beneath the mask 203 generally define active regions of the substrate, e.g., regions of the substrate on which active devices such as bases, collectors, emitters, source/drain regions or gate electrodes are formed.
  • the exposed regions (only one of which, is shown) adjacent the masks 203 are generally used to form isolation regions which electrically isolate the active regions 204.
  • the thickness of the mask 203 is suitably selected in consideration of this removal process. In particular, the thickness of the mask 203 is selected to adequately protect the underlying substrate portions 204 during the removal process. In addition, portions of the trench will be implanted with an implant species as will be discussed further below. The thickness of the mask 203 is also selected in consideration of this implant. In particular, the mask thickness and implant energies are selected in consideration of the amount of the implant species, if any, which is desired to penetrate into the areas 204 of the substrate 201 beneath the mask 203.
  • thicknesses of the mask 203 ranging from about 450 to 2250 angstroms would be suitable for many applications. This may, for example, include nitride masking layer thicknesses ranging from about 350 to 1800 angstroms and pad oxide layer thicknesses ranging from 100 to 450 angstroms.
  • a portion of the substrate 201 in the exposed region 206 is then removed to form an isolation trench 209 in the substrate 201, as illustrated in Figure 2B.
  • the trench 209 may be formed using, for example, well-known etching techniques.
  • the depth of the trench 209 can vary depending, for example, on the device being formed. Typical trench depths range from about 0.1 to 0.4 microns for many applications.
  • An implant species 211 is implanted into portions of the substrate 201 which define the trench 209, as illustrated in Figure 2C.
  • the implanted species 211 will serve to reduce the stresses on the substrate 201 resulting from a subsequent oxide growth within the trench 209.
  • the implant species 211 is implanted into at least the upper corner portion 215 of the edge portion 213 of the trench 209.
  • the upper corner portion 215 of the trench is typically associated with the highest substrate stresses.
  • up to all of the edge portion 213 of the trench 209 may be implanted with the implant species 211.
  • a part or even all of the bottom 217 of the trench 209 may be implanted with the implant species 211.
  • the implant species 211 is typically implanted at an angle ⁇ with respect to the substrate surface. Angled implants may be performed by rotating the semiconductor substrate or by positioning the substrate at different orientations relative to an implant source.
  • the implant angle ⁇ is suitable selected in consideration of the height of the mask 203 as well as in consideration of the desired amount of the trench 209 to be implanted. For example, in some applications it may be desirable to only implant edge portions of the trench 209 while in other cases, it may be beneficial to implant the bottom 207 of the trench as well.
  • Suitable implant angles ⁇ typically range between 0 and 90°, and more typically between 30 and 45° for many applications. As the implant angle ⁇ increases, more of the trench 209 is implanted with the implant species 211. For example, at low implant angles (such as 5-10°) only an upper corner portion of the trench may be implanted with the implant species 211. At greater angles, more of the edge portions 213 are implanted with the implant species 211 and, as the angle ⁇ increases further, the bottom portion 217 of the trench is implanted with the implant species 211.
  • the implant species 211 is typically implanted at an energy level and dosage sufficient to damage the implanted portion of the substrate 201 without hindering the ability of oxide to grow on the implanted substrate portions.
  • the implanted or damaged substrate portions such as the upper corner portion 215 of the trench 209, allow oxide to grow at least as fast as oxide would grown in the trench prior to the implant of species 211.
  • the growth of oxide is faster in the damaged substrate portions than it would be had there been no species 211 implant.
  • the particular energy level and dosage of the implant species 211 will vary with the type of implant species 211.
  • the type of implant species 211 may be one or more of a number of different materials which can damage the substrate 201 without hindering subsequent oxide growth.
  • Exemplary implant species 211 include, for example, silicon-containing species such as Si and Si 2 , nitrogen-containing species such as N 2 , N i4 and NO, and argon-containing species, such as Ar.
  • Suitable N 2 implant energies and dosages range from about 20-40 KeV and 1E14- 8E14 atoms/cm 2 , respectively, for many applications.
  • Suitable N i4 implant energies and dosages range from about 10-40 KeV and 1E14-1E15 atoms/cm 2 , respectively, for many applications.
  • Suitable Si implant energies and dosages range from about 10-40 KeV and about 1E14-2E15 atoms/cm 2 , respectively, for many applications.
  • Suitable Ar implant energies and dosages range from about 20-100 KeV and about 1E14-1E15 atoms/cm 2 , respectively, for many applications .
  • the implant energy for the implanted species 211 may also be selected in consideration of the desired penetration of the mask 203.
  • the implant species 211 is implanted through the mask 203 and into areas 204 of the substrate 201 beneath the mask 203.
  • the implant energy and mask thickness is selected such that the mask 203 absorbs substantially all of the implant species 211, thereby preventing doping of the substrate areas 204 with the implant species 211.
  • an oxide layer 219 is grown in the trench 209, as illustrated in Figure 2D. This may be done using, for example, well-known thermal oxidation techniques.
  • the oxide layer 219 generally grows by consuming portions of the substrate 201. During this process, some or all of the implanted implant species 211 is also consumed. Suitable thicknesses of the oxide layer 219 range from about 100 to 700 angstroms for many applications .
  • the dielectric layer 221 may be formed in the trench 209 as well as over the mask 203 and subsequently removed from over the mask 203. Formation and removal of portions of the dielectric layer 221 may be done using, for example, well-known deposition and polishing techniques.
  • the resultant structure is illustrated in Figure 2E. While the oxide layer 219 and the dielectric layer 221 are illustrated separately, it should be appreciated that these two layers may blend together if formed of a similar material.
  • a channel stop implant may be performed before or after forming the liner oxide layer 219.
  • the mask 203 is removed using, for example, well- known wet or dry etching techniques.
  • the resultant structure, illustrated in Figure 2F, includes an isolation region 223 formed in an isolation trench 209.
  • the trench 209 includes a rounded upper corner portion 225.
  • the rounded upper corner portion 225 differs from the pointed upper corner portion found in conventionally- formed isolation regions (see e.g., corner portion 105 of Figure 1) and is associated with reduced stress as compared to the substrate surrounding a conventionally- formed isolation region.
  • the isolation region 223 is illustrated as a uniform region, it should be appreciated that the region 223 may be formed with a number of different dielectric materials.
  • regions of the substrate 201 around the isolation region 223 may contain residual amounts of the implant species 211.
  • Fabrication may continue with conventional fabrication processes to complete the device structure. For example, source/drain regions and gate electrodes may be formed in the active regions 204, followed by silicidation, contact formation, and so forth.
  • an implant is used to damage at least part of the edge of an isolation trench.
  • less stress will be placed on the underlying substrate 201. This can, for example, advantageously enhance the performance and improve the reliability of the ultimately-formed device.
  • the present invention is applicable to the fabrication of a number of different devices where an isolation region is formed in a substrate.
  • the invention is also applicable to LOCOS isolation techniques which employ shallow trenches to recess an isolation oxide region.
  • the second oxide layer is typically omitted and the grown oxide layer is generally used by itself to form the isolation region.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)

Abstract

L'invention a trait à un dispositif de semi-conducteur comportant une région d'isolation améliorée, et à un procédé de fabrication de ce dispositif de semi-conducteur. Selon un mode de réalisation de l'invention, au moins une tranchée d'isolation est formée dans un substrat. Une espèce d'implant est ensuite implantée dans des parties du substrat définissant une partie de bord de la tranchée d'isolation, et un oxyde est formé dans la tranchée au moyen des parties de substrat implantées. L'espèce d'implant peut être, par exemple, une espèce inerte telle que des espèces azotées ou contenant du silicium. Selon un aspect de l'invention, l'espèce d'implant est implantée de telle sorte que l'oxyde formé croît au moins aussi rapidement dans les parties de substrat implantées que dans d'autres parties du substrat non implantées par l'espèce d'implant. A l'aide de ce procédé, on peut former des régions d'isolation qui présentent des contraintes de substrat réduites par comparaison avec des régions d'isolation formées par des techniques classiques.
PCT/US1998/010178 1997-11-07 1998-05-12 Dispositif de semi-conducteur comportant une region d'isolation amelioree et procede de fabrication de celui-ci WO1999025018A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US96587097A 1997-11-07 1997-11-07
US08/965,870 1997-11-07

Publications (1)

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WO1999025018A1 true WO1999025018A1 (fr) 1999-05-20

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19939597A1 (de) * 1999-08-20 2001-03-01 Siemens Ag Verfahren zur Herstellung einer mikroelektronischen Struktur
WO2001050501A2 (fr) * 1999-12-30 2001-07-12 Infineon Technologies North America Corp. Arrondissement d'angles de silicium par implantation d'ions pour tranchees peu profondes
WO2001082333A2 (fr) * 2000-04-20 2001-11-01 Infineon Technologies North America Corp. Maitrise de l'epaisseur d'oxyde dans des structures de transistor vertical
WO2004081989A3 (fr) * 2003-03-12 2004-12-23 Micron Technology Inc Implantation inclinee pour caisson d'isolation
CN104425345A (zh) * 2013-09-09 2015-03-18 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process
US5112762A (en) * 1990-12-05 1992-05-12 Anderson Dirk N High angle implant around top of trench to reduce gated diode leakage
JPH0794503A (ja) * 1993-09-24 1995-04-07 Sumitomo Metal Ind Ltd シリコン基板の酸化方法
US5637529A (en) * 1995-08-26 1997-06-10 Hyundai Electronics Industries Co., Ltd. Method for forming element isolation insulating film of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process
US5112762A (en) * 1990-12-05 1992-05-12 Anderson Dirk N High angle implant around top of trench to reduce gated diode leakage
JPH0794503A (ja) * 1993-09-24 1995-04-07 Sumitomo Metal Ind Ltd シリコン基板の酸化方法
US5637529A (en) * 1995-08-26 1997-06-10 Hyundai Electronics Industries Co., Ltd. Method for forming element isolation insulating film of semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 095, no. 007 31 August 1995 (1995-08-31) *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19939597B4 (de) * 1999-08-20 2006-07-20 Infineon Technologies Ag Verfahren zur Herstellung einer mikroelektronischen Struktur mit verbesserter Gatedielektrikahomogenität
US6368940B1 (en) * 1999-08-20 2002-04-09 Infineon Technologies Ag Method for fabricating a microelectronic structure
DE19939597A1 (de) * 1999-08-20 2001-03-01 Siemens Ag Verfahren zur Herstellung einer mikroelektronischen Struktur
WO2001050501A2 (fr) * 1999-12-30 2001-07-12 Infineon Technologies North America Corp. Arrondissement d'angles de silicium par implantation d'ions pour tranchees peu profondes
WO2001050501A3 (fr) * 1999-12-30 2002-03-21 Infineon Technologies Corp Arrondissement d'angles de silicium par implantation d'ions pour tranchees peu profondes
WO2001082333A2 (fr) * 2000-04-20 2001-11-01 Infineon Technologies North America Corp. Maitrise de l'epaisseur d'oxyde dans des structures de transistor vertical
WO2001082333A3 (fr) * 2000-04-20 2002-01-24 Infineon Technologies Corp Maitrise de l'epaisseur d'oxyde dans des structures de transistor vertical
WO2004081989A3 (fr) * 2003-03-12 2004-12-23 Micron Technology Inc Implantation inclinee pour caisson d'isolation
US6949445B2 (en) 2003-03-12 2005-09-27 Micron Technology, Inc. Method of forming angled implant for trench isolation
JP2006521697A (ja) * 2003-03-12 2006-09-21 マイクロン・テクノロジー・インコーポレイテッド トレンチ分離のための傾斜注入
KR100777376B1 (ko) 2003-03-12 2007-11-19 마이크론 테크놀로지, 인크 트렌치 아이솔레이션을 위한 경사 이온주입
US7514715B2 (en) 2003-03-12 2009-04-07 Aptina Imaging Corporation Angled implant for trench isolation
US7919797B2 (en) 2003-03-12 2011-04-05 Aptina Imaging Corporation Angled implant for trench isolation
CN104425345A (zh) * 2013-09-09 2015-03-18 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的形成方法

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