WO1999018607A1

WO1999018607A1 - Methods of making flexible substrates for electronic packaging and flexible substrates formed by the method

Info

Publication number: WO1999018607A1
Application number: PCT/US1998/020669
Authority: WO
Inventors: Timothy G. Lenihan; Ajay P. Malshe; William D. Brown; Leonard W. Schaper
Original assignee: The Board Of Trustees Of The University Of Arkansas
Priority date: 1997-10-03
Filing date: 1998-10-01
Publication date: 1999-04-15
Also published as: AU1064899A

Abstract

An electronic package (100) including a flexible substrate (305), at least one device positioned on a first portion of a flexible substrate (305) wherein the devices are selected from the group consisting of active devices or passive devices and wherein the substrate is configured into a geometric shape such that the first portion and the second portion are oriented in different planes. A method of making the package (100) includes positioning devices on the first and second portions, and then configuring the substrate into the geometric shape.

Description

METHODS OF MAKING FLEXIBLE SUBSTRATES FOR ELECTRONIC PACKAGING AND FLEXIBLE SUBSTRATES FORMED BY THE METHOD

BAC CreOTTNTj OF THE T VFNTTON

1. Field of the Invention

The present invention relates to substrates, to

5 methods of making such substrates, to products made from such substrates, and to methods of making such products.

In another aspect, the present invention relates to substrates for electronics packaging, to methods of making such substrates, to products made from such substrates, and 0 to methods of making such products. In even another aspect, the present invention relates to flexible substrates for electronics packaging, to methods of making such flexible substrates, to products made from such substrates, and to methods of making such products. 5

2. Description of the Related Art

Many advanced defense and civilian applications of high density electronic packaging, such as commercial electronic products and satellites, airborne electronics, Global Positioning System (GPS) guidance packages, distributed simulation workstations, real time satellite data/image editing, ground stationed high traffic mobile telephone stations, note-books, table-top supercomputer workstations, etc., are limited by the 2-D multi-chip module (MCM) concept for a variety of reasons. Most of these and similar applications demand high volume data handling, extremely high reliability, multiple/complex functional requirements, extremely small space, light weight, and fast operating speeds. To achieve these goals, the required features are high electrical interconnect density, high power, and thus, high temperature handling capacity, compact design, light weight, and easy reworkability. All of these must also be achieved at a reasonable cost since cost is a major driving factor in the electronics industry. To realize these requirements, some form of integrated flexible packaging has been proposed as the best solution.

Additionally, rapid changes in the electronics area are driven by the need for, and attractiveness of, faster, smaller, and lighter-weight electronics. Much of the real estate on a typical semiconductor wafer is occupied by interconnecting electrical lines. Today's electronic "chips" are already so small, making it somewhat costly to obtain sufficient reductions in chip size to provide either an appreciable reduction in weight of the electronic package or an improved speed of operation. A reduction in the space taken up by interconnects must be targeted to achieve the goals of faster speed, lighter weight, and smaller size. It is also believed that integrated flexible packaging is the solution to these problems also. Advancements of electronic packaging technologies are evolving in three directions: (1) high packaging density; (2) high performance; and (3) low cost. Advanced defense and civilian applications demand extremely high density electronic packages. Among the various packaging technologies, flexible packaging is considered to be a potential solution for high packaging density and enhanced electrical performance .

Although three dimensional packages are known in the electronics packaging technology art, and have many strengths and possible applications, several common critical concerns, regardless of the stacking method, have kept three dimensional packaging technology from widespread use. The delay in the widespread use of three dimensional packages by the electronics industry has occurred because of concerns about technical aspects such as complicated assembly processes, lower assembly yield, difficulties in mass production, high assembly cost, and inferior heat dissipation capability.

Specifically, the addition of complicated wafer fabrication and chip interconnection processes results in lower assembly yield and high assembly cost since some of the required processes are difficult to automate. Thus, large volume manufacturing of three dimensional packages has been delayed. Thermal management is also an important concern. Heat that is generated from the center chip of a stack cannot be easily dissipated. For flexible packaging to obtain widespread acceptance, these problems of reduced manufacturing cost, ease of fabrication, and efficient thermal management, must be resolved.

Utilization of embedded metal signal and power lines in flexible films, like polyimide, is known in the art.

Generally, these types of structures can be found on traditional electronic packages like multi-chip modules

(MCMs) where the polyimide films and metal films are deposited and then patterned. These types of interconnections for chip signal and power are cost effective because the number of layers in a traditional electronic package, like a ceramic package, is reduced by using thin film layers. Large area, free-standing, flexible films with metal lines can be made in large sheets and then cut into smaller sections, which is cost effective. However, one major drawback of the free-standing type of film is that the metal line widths manufactured today are much larger (~ 4X) than what can be obtained using thin films in electronics packaging technologies, such as silicon. Also, the current traditional three dimensional or dense high performance electronics packaging format using ceramics or silicon imposes a physical size restriction of about 5 inches for the width.

However, in spite of these advancements in the prior art, there is still room for improving upon flexible packaging for electronics, methods of making such packaging, products made from such packaging, and methods of making such products. Thus, these is still a need for flexible packaging for electronics, methods of making such packaging, products from such packaging, and methods of making such products.

There is another need in the art for flexible packaging that will improve the prior art in one or more of the problem areas of complicated assembly processes, low assembly yield, difficulties in mass production, high assembly cost, and inferior heat dissipation capability.

These and other needs in the art will become apparent to those of skill in the art upon review of this specification, including its drawings and claims.

SUMMARY OF THE INVENTION It is an object of the present invention to provide for flexible packaging for electronics, methods of making such packaging, products made from such packaging, and methods of making such products.

It is another object of the present invention to provide for improved flexible packaging for electronics, methods of making such packaging, products from such packaging, and methods of making such products. It is even another object of the present invention to provide for flexible packaging that will improve the prior art in one or more of the problem areas of complicated assembly processes, low assembly yield, difficulties in mass production, high assembly cost, and inferior heat dissipation capability.

These and other objects of the present invention will become apparent to those of skill in the art upon review of this specification, including its drawings and claims.

The present invention provides for the creation of two dimensional and three dimensional electronic packaging with semiconductor chips mounted on a flexible substrate with and without embedded passive or active devices. In accordance with the present invention, the flexible substrate will generally contains all of the interconnection wiring required between the chips for communication and power. In addition, the flexible substrates will generally comprise one or more of embedded passive devices such as filters, resistors, inductors, capacitors, antennas and transformers, or of embedded active devices such as transistors, sensors, thermisters, actuators and optical devices, required for the chips to operate. Multiple chips can be mounted on the flexible substrates which also serves as the carrier for the chips. A key advantage to using flexible substrates is the ability to shape the total package into a small space and unfold it to repair chips if needed. Finally, the cost of making this type of package would be significantly lower than making a traditional electronic package. Because the manufacturer is not constrained to a fixed package size until assembly, large area flexible substrates with or without embedded passive devices can be made and then separated into smaller packaging units. The present invention allows for the use of different types of heat spreaders/sinks such as Cu/diamond.

According to one embodiment of the present invention there is provided a method of forming an electronics package. The method includes the step of forming on a each in N portions of a flexible substrate, at least one device selected from the group consisting of active devices or passive devices. The method then includes configuring the flexible substrate into a geometric shape such that each of the N portions are oriented in different planes.

According to another embodiment of the present invention there is provided an electronics package. The package includes a flexible substrate. The package also includes at least one device positioned on each of N portions of the flexible substrate, wherein for each portion the device is selected from the group consisting of active devices or passive devices. The package is configured into a geometric shape such that the first portion and the second portion are oriented in different planes .

In the above embodiments of the present invention, N is generally greater than 2, preferably greater than 3, and more preferably greater than 4, and the passive devices may comprise at least one selected from the group of filters, resistors, inductors, capacitors, antennas, and the active devices may comprise at least one selected from among transformers, transistors, sensors, thermisters, actuators and optical devices.

BRTEF DESORTPTTON OF THE DRAWINGS FIG. 1 is a schematic illustration of one embodiment of the present invention showing a thermally and electronically integrated flexible package with embedded passives.

FIGs. 2A and 2B are illustrations of individual embedded resistors.

FIGs. 2C and 2D are graphs of resistor values for the individual embedded resistors of FIGs. 2A and 2B, respectively.

FIGs. 3A and 3B are illustrations of individual embedded capacitors.

FIG. 3C is a graph of impedance values for the individual embedded capacitors of FIGs. 3A and 3B.

FIGs. 4A and 4B are schematic representations of flexible packaging of the present invention.

FIGs. 5A and 5B are illustrations of individual embedded inductors .

FIGs . 5C and 5D are graphs of impedance values for the individual embedded inductors of FIGs. 5A and 5B, respectively.

FIG. 6 is a schematic representation of one embodiment of a 2-D layout of the present invention. FIG. 7 is a schematic representation of one embodiment of a manufacturing layout of the present invention.

FIG. 8 is a schematic representation of one embodiment of a 2-D package of the present invention.

FIG. 9 is a schematic representation of one embodiment of a 2-D layout of the present invention.

FIG. 10 is a schematic representation of one embodiment of a 3-D package of the present invention with cooling provided by a gas.

FIG. 11 is a schematic representation of one embodiment of a 3-D package of the present invention with cooling provided by a liquid.

FIG. 12 is a schematic representation of one embodiment of a 3-D package of the present invention with interposers provided.

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1 there is shown a schematic illustration of one embodiment of a 3-D package 100 of the present invention showing a thermally and electronically integrated flexible package with embedded devices .

The package 100 includes a cooling system 120. While in the embodiment shown, cooling system 120 utilizes cooling water, it should be understood that any suitable cooling medium, including any suitable gas or liquid, may be utilized.

Package 100 also includes one or more embedded devices 140 and interconnect devices 150. While in the embodiment shown, embedded devices 140 are electronic chips, it should be understood that any desired passive devices such as filters, resistors, inductors, capacitors, antennas and transformers, or active devices such as transistors, sensors, thermisters, actuators and optical devices, may be utilized.

Heat conductors 130 are provided to pass heat from embedded devices 140 to cooling system 120. Of course, any suitable heat conducting material may be utilized for heat conductor 130, including heat conducting metals, ceramics, polymers, and combinations thereof. Non-limiting examples of suitable heat conducting materials include heat conducting metals, such as aluminum and copper, metal - ceramic composites, carbon-carbon composites, diamond, metal carbide-metal composites.

Package 100 may optionally also include bus connections 170. Typically, one signal layer is made on each layer of thin film with two layers (an X and Y) required to make a - In ¬

complete signal path within the package. Suitable methods of accomplishing this signal path are disclosed in U.S. Patent No. 5,410,107, issued to Schaper, herein incorporated by reference. Referring now to FIG. 4A, interconnector 200 can contain both signal lines 210 and 215, x and y, in one layer. Using a different design approach as shown in FIG. 4B, the interconnector 200 can contain both signal layers 210 and 215, and the power lines 220 required in two thin film layers. Thus, this technology approaches the wiring density that can be obtained in thin film layers in traditional packages.

Concerning dimensions, there is no limitation on how long the flexible layer can be. This is in contrast to the limited length restriction for traditional high performance packaging. Thus, there is not the physical limitation found in a fixed format package.

Another advantage with the present invention is that the layers can be tested individually before assembly which allows the removal of defects early in the fabrication process. In a traditional package, significant processing is required to remove defective layers and replace them. This extra processing is a significant cost component for the traditional packaging process. Another advantage of using the present invention is that passive passive devices such as filters, resistors, inductors, capacitors, antennas and transformers, or active devices such as transistors, sensors, thermisters, actuators and optical devices, can be embedded in the layers, reducing the need to place them on the surface as is typically done in traditional electronic packages. Their reliability would be greater since their connections can be tested before the chips are attached to the film. Internal thin film connections are more reliable than external connections such as soldering or wire bonding. In instances where multiple layers of interconnection films are required, a conductive adhesive could be used to attach the film layers. As a non-limiting example, one layer may contain capacitors and inductors, another layer may contain resistors, and a third or fourth layer could contain signal and power interconnections. The present invention is not to be limited to any number of layers or combination or arrangement of embedded devices.

In the practice of the present invention there will generally be at least 2 layers, preferably at least 3 layers, more preferably at least 4 layers, even more preferably at least 5 layers and still more preferably at least 10 layers, and yet more preferably at least 15 layers .

An advantage of using flexible layers with embedded signal and power lines is that there is no restriction on the number of chips that can be put on each layer.

FIG. 6 is a schematic representation of one embodiment of a 2-D layout 300 of the present invention. This 2-D layout 300 includes flex film 305 supporting any desired number of chips 310 having any desired number of devices 315. This 2-D layout further includes heat spreader 320 and any desired number of heat sinks 330. Complete processor systems, could be put on a strip of flexible film 305 with multiple layers. Flexible substrate 305 may be made of any suitable flexible material that will provide the required support for any devices, and that can be configured into the desired geometric configuration. Preferred materials include polymers such as thermoplastics, thermoplastic elastomers, thermosets and elastomers. Non-limiting examples of suitable polymers include polyolefins, polyimides, polyamides, polyacrylamides, epoxies, copolymers of 2 or more alpha olefins, polystrenes, fiber glass, polyurethane, polyalkylene oxides, polyacrylates, ethylene vinyl acetate copolymers. Referring now to FIG. 7, there is shown the manufacturing layout 301 for the 2-D layout 300 of FIG. 6. Flex film 305 can be made of any suitable length to accommodate any desired number of chips 310 and heat spreaders 320. Since there are no restrictions on how long flex film 300 can be, as opposed to a traditional package, many independent groups of processors could be mounted on one flexible film 300 thereby making a parallel processing computer or supercomputer.

It is envisioned that manufacturing layout 301 can be folded to reduce the size of the system. For example, referring now to FIG. 8, there is shown 2-D package layout 302 for 2-D manufacturing layout 301 of FIG. 7. Further shown in FIG. 8 is cooling jacket 360 and cooling medium 363. While in the embodiment shown, cooling jacket 360 is a water cooling jacket utilizing water as cooling medium 363, it is to be understood that any suitable type of cooling apparatus and cooling medium may be utilized.

Packaging layout 302 may be utilized to provide higher silicon packing density as components normally found on the surface are now embedded inside the package. This is achieved by placing many chips 310 on flexible film 305 and folding it .

With such a folded layout, there may be a trade-off in signal delay if the metal lines extend out into a single flexible layer 305 away from chips 310 as layer 305 becomes wider. At such a point it becomes more efficient to use multiple layers of flexible films with the chips connected in a three dimensional format.

Referring now to FIGs. 9-12, it can be seen that by folding the layers, a very compact 2D package can be made. FIGs. 9-12 show respectively, 3-D layout 400, 3-D Package 401 with chips 310 mounted on both sides of film 305 with cooling water 363, 3-D package 402 with chips 310 mounted on both sides of film 305 with cooling air 363, and 3-D package 403 with chips 310 mounted on both sides of film 305. Even though chips 310 are stacked in three dimensions, flexible film 3-5 still remains a 2D package which is merely folded. To make the package three dimensional, interposers 350 would be used between the layers of films providing a third dimension for signals to travel to the chips on the films. Interposer 350 provides an electrical path between the signal layers.

For high power applications, where current density is a reliability issue, thicker metal lines can be easily imbedded in flexible films 305 (such as Cu metal lines which can be plated onto flexible film 305) . Chip assembly can be made by conductive epoxy, solder joints, or wire bond.

In previously envisioned 3-D diamond multi chip modules ( "MCM" ) as shown in FIG. 2B, the diamond only serves as a means of carrying heat, and does not take an active role in supporting the electrical interconnect network. In the present invention, the use of diamond as a heat spreader, significantly reduces the quantity of diamond required. As there is no need for large area diamond substrates in the present invention for providing structural support, or post substrate synthesis processing, the present invention provides a major cost reduction.

Both the two dimensional and three dimensional flexible packages of the present invention will require sufficient cooling systems because they are so compact when folded resulting in heat generation. This can be solved by inserting a conductive material 320, such as a heat spreader like a Cu sheet or a heat sink, between two levels of chips 310 when the package is folded. This would allow heat to be removed from chips 310 while folded, and will not necessarily require heat conductor 320 to be attached to the chips as in conventional packages. If the heat spreader is not sufficient to remove all of the heat, then heat sinks 330 can be attached to the heat spreader to supplement heat removal capacity and rate. This same scheme could be used for the three dimensional flexible package since the interposer would be mounted away from the heat spreaders/ sinks as shown in FIG. 12. The heat spreader/sink and the chip can be brought in contact mechanically or by using an adhesive. Mechanical contact would require a supporting structure, such as cooling jacket 360 shown in FIG. 10, for aligning the heat sinks, if used. A thermally conductive adhesive could be used to insure contact between the chip and the heat sink.

But if the thermal adhesive is not reworkable, the ability to unfold the film and rework the chips is not possible. Even finned heat sinks could be used. The heat spreader can be air cooled or could be attached to a water cooled jacket . As shown in FIGs. 9-12, incorporating interposers 350 into the flexible substrate package allows a design that provides convenient test points for the two adjacent chips near each interposer. By allocating a unique address line for each chip 310, they can be accessed separately and tested prior to assembly. This allows for repairs to be made prior to final assembly and is more cost effective than a traditional high performance electronic package. The interposer could also be designed to have test points on its edge, accessible after assembly, to find defective parts. Test points could also be made available on the edge of the film for post-assembly testing, or for testing a package after it has been in a system, to find problems. Repair of a flexible film would be possible if the interposer connections to the flexible film were reworkable. Since only the section that needs to be repaired has to be disconnected to be unfolded, only one side of the interposer would have to be disconnected. One approach that could be used is a low temperature connection, like solder, for the interposer connection. It could be locally heated to disconnect without affecting the chips near it. Reattachment could be made using a low temperature attachment, like solder or conductive epoxy. Another approach might be to use a metal interposer which can be heated directly. This would allow for the use of a low temperature solder several times for repair. The cost of this type of interposer would be higher, since electrical isolation of the signal lines would still be needed.

Prior to assembly, the film, chips, thermal conductor, and interposers can be tested individually to remove defects early in the process and, therefore, at a lower cost. The chips can optionally be tested after assembly on the film through the interposer. After assembly, the flexible film can be unfolded by disconnecting the interposer on one side, which would leave two sides of a film exposed for repair, making it easier to isolate sections of the package. A whole section of a layer can be replaced, if needed, by using an interposer on the other side, away from the three dimensional connection interposer. Attachment techniques consistent with normal chip attachment technologies, where the chips use solder or conductive paste, could be used for the interposer as part of the normal processing.

The cost of the interconnection/passive device layers would be fixed since large films can be made and cut into smaller packages later. The thermal conductor cost would also be fixed since the heat spreader/sink could be cut from a large sheet and would be less expensive than for a typical traditional package where the heat spreader/heat sink is customized as part of the electronic package. If there were diamond heat sinks required, they could also be made in large sheets, cut out to chip size, and added to the heat spreader later as needed. With the present invention, if a thermal spreader or heat sink is defective, it may easily be replaced since it is not permanently affixed to the fixed-form package, as in a traditional electronic package. It is only attached to the - In ¬

flexible film. The packaging system could also be designed such that the heat spreader doesn't have to be attached to the flexible film, as in the case of a water cooled jacket which would support the film. The heat spreader could just be placed over the chips during assembly, but some attachment to maintain alignment for heat sinks over the chips would be better. The rest of the cost of the package would be proportional to the number of chips required. Because the heat spreader, heat sink, and interconnection film can be tested before assembly, defects can be removed early in the process, and at significantly lower costs.

Because the film is flexible, it can be made to conform to the shape of the system into which it is going. For example, a flexible film could be used in a satellite by conforming to the shape of the satellite. This presents a major advantage over conventional electronic packaging, particularly, for consumer applications where space and weight may be critical (like portable communication devices, portable PC's, etc.). The fact that the flex substrate will be used as the carrier of electrical power offers several advantages and contributes to the potential success of the program.

Such flexible electronic packages will have an extremely wide market and a potential to enter the market within a short time after development. From the futuristic point of view, the success of the fabrication of thermally and electrically integrated flexible substrates opens up avenues for embedding flexible optical fiber interconnects in similar structures for faster inter-planar communication. EXAMPLES

The following examples are provided merely to illustrate embodiments of the present invention, and are not to limit the scope of the claims.

Example 1. Embedded Resistors.

FIGs. 2A and 2B are illustrations of individual embedded resistors of this example.

Example 2. Embedded Capacitors.

FIGs. 3A and 3B are illustrations of individual embedded capacitors .

Example 3. Embedded Inductors.

FIGs. 5A and 5B are illustrations of individual embedded inductors .

FIGs . 5C and 5D are graphs of impedance and phase values for the individual embedded inductors of FIGs . 5A and 5B.

While the illustrative embodiments of the invention have been described with particularity, it will be understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the examples and descriptions set forth herein but rather that the claims be construed as encompassing all the features of patentable novelty which reside in the present invention, including all features which would be treated as equivalents thereof by those skilled in the art to which this invention pertains.

Claims

WE CLAIM :

1. A method of forming an electronics package, comprising the steps of: (a) forming on each of N portions of a flexible substrate, at least one device selected from the group consisting of active devices or passive devices; (b) configuring the flexible substrate into a geometric shape such that each of the N portions are oriented in different planes.

2. The method of claim 1 further comprising the step of: c) positioning a cooling system between two adjacent N portions.

3. The method of claim 1 wherein the flexible substrate contains at least one interconnecting member for electrically connecting two or more N portions.

4. The method of claim 1 where N is greater than 2.

5. The method of claim 1 where N is greater than 3.

6. The method of claim 1 where N is greater than 4.

7. The method of claim 1 where at least one semiconductor chip is mounted on at least one N portion.

8. The method of claim 1 wherein the passive devices comprise at least one selected from the group of filters, resistors, inductors, capacitors, antennas and transformers, and wherein the active devices comprise at least one selected from the group of transistors, sensors, thermisters, actuators and optical devices, required for the chips to operate.

9. The method of claim 1 further comprising the step of: c) positioning a cooling system between two adjacent N portions; wherein the flexible substrate contains at least one interconnecting member for electrically connecting two or more N portions; and wherein N is greater than 2.

10. An apparatus comprising: (a) a flexible substrate; and, (b) at least one device positioned on N portions of a flexible substrate, wherein the device is selected from the group consisting of active devices or passive devices; wherein the substrate is configured into a geometric shape such that the N portions are oriented in different planes.

11. The apparatus of claim 10 further comprising: c) a cooling system positioned between two adjacent N portions.

12. The apparatus of claim 10 wherein the flexible substrate contains at least one interconnecting member for electrically connecting two or more N portions.

13. The apparatus of claim 10 where N is greater than 2.

14. The apparatus of claim 10 where N is greater than 3.

15. The apparatus of claim 10 where N is greater than 4.

16. The apparatus of claim 10 where at least one semiconductor chip is mounted on at least one N portion.

17. The apparatus of claim 10 wherein the passive devices comprise at least one selected from the group of filters, resistors, inductors, capacitors, antennas and transformers, and wherein the active devices comprise at least one selected from the group of transistors, sensors, thermisters, actuators and optical devices, required for the chips to operate.

18. The apparatus of claim 10 further comprising: c) a cooling system positioned between two adjacent N portions; wherein the flexible substrate contains at least one interconnecting member for electrically connecting two or more N portions; and wherein N is greater than 2.