WO1999017552A1 - Appareil et procede d'extraction de mesures des besoins de traitement d'un courant binaire a des fins de decodage - Google Patents

Appareil et procede d'extraction de mesures des besoins de traitement d'un courant binaire a des fins de decodage Download PDF

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Publication number
WO1999017552A1
WO1999017552A1 PCT/JP1998/004330 JP9804330W WO9917552A1 WO 1999017552 A1 WO1999017552 A1 WO 1999017552A1 JP 9804330 W JP9804330 W JP 9804330W WO 9917552 A1 WO9917552 A1 WO 9917552A1
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WO
WIPO (PCT)
Prior art keywords
bitstream
syntax elements
decoder
decoding
processing
Prior art date
Application number
PCT/JP1998/004330
Other languages
English (en)
Inventor
William Brent Wilson
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to CN98801409A priority Critical patent/CN1241334A/zh
Priority to BR9806269A priority patent/BR9806269A/pt
Priority to EP19980944260 priority patent/EP0956705A1/fr
Publication of WO1999017552A1 publication Critical patent/WO1999017552A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
    • H04N21/633—Control signals issued by server directed to the network components or client
    • H04N21/6332—Control signals issued by server directed to the network components or client directed to client
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/127—Prioritisation of hardware or computational resources
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/65—Transmission of management data between client and server
    • H04N21/654—Transmission by server directed to the client

Definitions

  • This invention relates to appartus and method for extracting measures of a bitstream's processing requirements for decoding, and more particularly, to the field of digital audio and video decoders and the extraction of the processing requirements of a bitstream to be decoded by these decoders.
  • Digital audio and video has become widespread in the field of consumer electronics, due in large part to the emergence of digital video standards such as MPEG1 (see “CD11172 - Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbps” by International Organisation for Standardisation, ISO MPEG Document, ISO-IEC/JTC1/SC2/WG11 , 1994), MPEG2 (see “IS 13818 - Generic coding of Moving Pictures and Associated Audio” by International Organisation for Standardisation, ISO MPEG Document, ISO-
  • MPEG4 which includes further added functionality and quality over MPEG1 and MPEG2.
  • MPEG1 and MPEG2 decoders there are certain expectations regarding the decoder processing power which must be met in order to conform to the respective standard.
  • MP@ML Main Profile and Main Level
  • MPEG4 includes the concept of video objects, which are picture sequences which may be used to describe a separable object in a scene. If a scene contains many objects, it is desirable to know the objects processing requirements for decoding so that decoder resources can be efficiently allocated to objects. If there are multiple decoders in a system which use the same resources, it is desirable to know the decoder's processing requirements so that resources can be efficiently allocated to each decoder.
  • An object of this invention is to extract information from a bitstream which can be used to predict the processing requirements for decoding that bitstream.
  • a resource reallocation can be performed. It is an object of this invention to permit the processing requirements of a bitstream to be measured in order for the efficient allocation of computational and memory resources to a decoder function, which can be used to help maintain decoder performance.
  • a parser parses a bitstream for syntax elements.
  • a processor processes said syntax elements and determines processing indicators.
  • a buffer stores said indicators.
  • a buffer stores said syntax elements and a processor processes said stored syntax elements and determines processing indicators.
  • Said parser's position in the decoder may be before said decoder's input bitstream buffer.
  • Said parser may be combined or be a subset of said decoder's bitstream syntax decoder which parses the bitstream for the purpose of decoding.
  • Said parser and decoder's bitstream syntax decoder may be before or after said decoder's input bitstream buffer.
  • Said processor processing may include analysing occurrences of said syntax elements to obtain some measures of processing requirements for decoding said bitstream.
  • Said decoder may comprise of one or more video decoders, one or more audio decoders, one or more graphics decoders, or a combination of these decoders.
  • the parser extracts syntax elements useful for determining the processing requirements of decoding the bitstream. In some cases it may be possible to combine this function with the decoder's bitstream syntax decoder since it's function is also to extract syntax elements from the bitstream. If the parser and decoder's bitstream syntax decoder are located before the decoder's input bitstream buffer, the input bitstream buffer can store extracted syntax elements for the decoding function to use later.
  • the extracted syntax elements passed to the processor are processed in order to determine some processing indicators, which are measures of the processing requirements for decoding the bitstream. These extracted syntax elements may or may not be buffered before the processor operates on them.
  • the processing indicators made by the processor may or may not be buffered. The buffer is used to permit the measures of processing requirements to be delayed until they are required.
  • Fig. 1 is a block diagram of a first mbodiment of the invention.
  • Fig. 2 is a block diagram of a second embodiment of the invention.
  • Fig. 3 is a block diagram of a third embodiment of the invention.
  • Fig. 4 is a block diagram of a fourth embodiment of the invention.
  • a first embodiment of this invention is shown in Fig. 1.
  • One or more bitstreams are input via the bitstream input 100, 101, 102.
  • the decoder 110 decodes the bitstreams and outputs decoded outputs 103.
  • the parser 120 accepts the bitstreams 102 and outputs syntax elements 121.
  • the processor 122 accepts the syntax elements 121 and outputs indicators 123.
  • the buffer 124 accepts the indicators 123 and outputs measures of the bitstream's processing requirements 125.
  • the parser 120 extracts syntax elements relevant to determining the processing requirements of the bitstreams and passes them to the processor 122.
  • the processor 122 determines from these syntax elements one or more indicators which can be used to measure the bitstreams processing requirements. These indicators are buffered by the buffer 124 until they are required. Second embodiment of this invention is shown in Fig.
  • the buffer 222 accepts the syntax elements 221 and outputs buffered syntax elements 223.
  • the processor 224 accepts the buffered syntax elements 223 and outputs measures of the bitstream's processing requirements 225.
  • the bitstream input 201 is passed to the decoder's input buffer 211, which passes the buffered bitstream 212 to a decoder parser 213.
  • the decoder parser passes decoder syntax elements 214 to the simple decoder 215, which outputs decoded outputs 203.
  • the parser 220 extracts syntax elements relevant to determining the processing requirements of the bitstreams and passes them to the buffer 222 for storage.
  • the processor 224 determines from these stored syntax elements one or more measures of the bitstreams processing requirements 225.
  • the decoder input buffer 211 stores the input bitstream until the appropriate time for decoding.
  • the decoder parser 213 performs some or all of the syntax decoding functions of the decoder 210.
  • the simple decoder 215 performs the remaining functions of the decoder 210.
  • the location of the buffer can be before or after the processor. It is also possible to have buffers both before and after the processor.
  • the actual structure of the decoder 210 shown in Fig. 2 is not a limitation of this invention. This structure is used to illustrate the differences between the embodiment of Fig. 2 and the embodiment of Fig. 3.
  • the parser 320 outputs decoder syntax elements 314 to a simple decoder 315, and outputs processing syntax elements 321 to the buffer 322.
  • the buffer 322 accepts the processing syntax elements 321 and outputs buffered processing syntax elements 323.
  • the processor 324 accepts the buffered processing syntax elements 323 and outputs measures of the bitstream's processing requirements 325.
  • the operation of the third embodiment in Fig. 3 is now described.
  • the parser 320 extracts processing syntax elements 321 relevant to determining the processing requirements of the bitstreams and passes them to the buffer 322 for storage, while also extracting decoder syntax elements 314 and passing them to the simple decoder 315.
  • a simple decoder may be simpler than the full decoder because some of it's syntax decoding functions are performed by the parser 320.
  • parsing and decoder bitstream syntax decoding functions can be performed by the same block, thus reducing cost. Both functions require similar functions which can easily be shared, such as syntax understanding and syntax element extraction.
  • Fig. 4 shows a fourth embodiment in which, the parser 420 outputs decoder syntax elements 412 to a decoder input buffer 411, which outputs buffered decoder syntax elements 414 to the simple decoder 415.
  • the parser also outputs processing syntax elements 421 to the buffer 422.
  • the buffer 422 accepts the processing syntax elements 421 and outputs buffered processing syntax elements 423.
  • the processor 424 accepts the buffered processing syntax elements 423 and outputs measures of the bitstream's processing requirements 425.
  • the parser 420 extracts processing syntax elements 421 relevant to determining the processing requirements of the bitstreams and passes them to the buffer 422 for storage, while also extracting decoder syntax elements 414 and passing them to the decoder input buffer 411.
  • the buffer 124, 222, 322, 422 is used to supply a delay determined by the embodiment's structure and the system's requirements for the measures of bitstream's computational requirements 125, 225, 325, 425.
  • the decoder input buffer 211 may be the video buffer verifier input buffer of an MPEG2 video decoder. This buffer stores incoming bitstreams such that a picture can be instantaneously extracted and decoded, as described in the MPEG2 specification. This buffer can also be used to synchronize decoders by allowing decoding and corresponding outputs to be delayed.
  • the complexity of the picture's coded bitstream can be determined before any of the picture is extracted from the decoder input buffer 211.
  • the system resources required by the decoder 210 can be determined and allocated before the picture decoding begins. Since it may be convenient to assign resources at the start of decoding a new picture, it is convenient to have a picture's measures of bitstream's computational requirements 225 before the picture is decoded.
  • the delay through the buffer 222 is similar to the delay of the decoder input buffer 211 for this example. This is not a limitation of the invention however, because other examples of this invention will require different buffer characteristics. For example, for a video decoder, the delay could vary from no delay to many pictures of delay. As an additional variation, some information occurs in the bitstream with different frequency than others, thereby requiring different buffering.
  • the decoder can be a video decoder, an audio decoder, a graphics decoder, or combinations and hybrids of these.
  • the parser may extract syntax elements from the bitstream which are used directly in the decoding process, or it may extract syntax elements that are placed in the bitstream for the purposes of indicating bitstream decoding computational requirements. This is not a limitation of the invention.
  • the processor processing is not limited by this invention.
  • the extracted data can be simply counted, averaged, filtered, or any number of operations, including none, may be performed.
  • the decoder 210 is an MPEG2 video decoder.
  • the parser 220 extracts the following syntax elements 221 from the bitstream input 202:
  • picture_coding_type (I, P, B,D) These elements can be used to determine some indication of the possible processing requirements of the bitstream. The picture size and rate can be determined from these elements.
  • the macroblock_type can be extracted and processed to determine the number of bi-directionally predicted macroblocks that are coded in a picture. This will help determine the computational requirements of decoding that picture. Bi-directionally predicted macroblocks require about twice the amount of frame memory accessing required by uni-directionally predicted macroblocks.
  • One effect of this invention is that information can be extracted from a bitstream which can be used to predict the processing requirements for decoding that bitstream.
  • the parser extracts syntax elements relevant to determining the processing requirements. Parsing can be performed together with the decoder's existing syntax decoder or separately, and can occur before or after the decoder's input bitstream buffer.
  • the processor processes these syntax elements resulting in measures which indicate the processing requirements of decoding the bitstream.
  • the buffer enables the measures to be available as and when needed.
  • An effect of this invention is that the processing power requirements of a bitstream may be measured in order for the efficient allocation of processing resources to a decoder function, which can be used to help maintain decoder performance. Ultimately this results in better picture and audio quality.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention porte sur un procédé d'extraction d'éléments de syntaxe d'un courant binaire afin de mesurer les besoins de traitement nécessaires au décodage du courant binaire. Cette mesure permet une attribution dynamique des ressources de décodage se basant sur la connaissance des besoins nécessaires au fonctionnement du décodeur. Le procédé recourt à un analyseur grammatical extrayant les d'éléments de syntaxe pertinents, à un processeur élaborant les mesures des besoins du courant binaire, et à une mise en tampon permettant de disposer des desdites mesures quand elles sont requises.
PCT/JP1998/004330 1997-09-30 1998-09-28 Appareil et procede d'extraction de mesures des besoins de traitement d'un courant binaire a des fins de decodage WO1999017552A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN98801409A CN1241334A (zh) 1997-09-30 1998-09-28 在解码中提取比特流处理要求的装置和方法
BR9806269A BR9806269A (pt) 1997-09-30 1998-09-28 Aparelho e método para extrair medidas de requerimentos de processamentos de um fluxo de bits para decodificação
EP19980944260 EP0956705A1 (fr) 1997-09-30 1998-09-28 Appareil et procede d'extraction de mesures des besoins de traitement d'un courant binaire a des fins de decodage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26621697A JPH11112972A (ja) 1997-09-30 1997-09-30 複合化処理量情報の抽出装置および方法
JP9/266216 1997-09-30

Publications (1)

Publication Number Publication Date
WO1999017552A1 true WO1999017552A1 (fr) 1999-04-08

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PCT/JP1998/004330 WO1999017552A1 (fr) 1997-09-30 1998-09-28 Appareil et procede d'extraction de mesures des besoins de traitement d'un courant binaire a des fins de decodage

Country Status (8)

Country Link
EP (1) EP0956705A1 (fr)
JP (1) JPH11112972A (fr)
KR (1) KR100317919B1 (fr)
CN (1) CN1241334A (fr)
BR (1) BR9806269A (fr)
ID (1) ID21549A (fr)
TW (1) TW404116B (fr)
WO (1) WO1999017552A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001069934A1 (fr) * 2000-03-17 2001-09-20 Telecom Italia Lab S.P.A. Procede et systeme de transmission de flux d'information
EP1519588A2 (fr) * 2003-07-30 2005-03-30 Sony Corporation Programme, méthode de traitement de données, et système de traitement de données
WO2006092671A1 (fr) * 2005-03-03 2006-09-08 Koninklijke Philips Electronics N.V. Systeme de secours adaptatif pour decodeurs mpeg
WO2010104432A1 (fr) * 2009-03-13 2010-09-16 Telefonaktiebolaget Lm Ericsson (Publ) Procédés et configurations permettant de traiter un flux binaire codé
CN102665081A (zh) * 2012-05-14 2012-09-12 青岛海信信芯科技有限公司 多格式码流的解析方法、多格式码流的解析装置和显示装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10218812A1 (de) * 2002-04-26 2003-11-20 Siemens Ag Generische Datenstrombeschreibung
KR101232780B1 (ko) * 2006-01-12 2013-09-03 (주)휴맥스 통합 코덱 장치 및 방법
JP4847890B2 (ja) 2007-02-16 2011-12-28 パナソニック株式会社 符号化方式変換装置
KR100943214B1 (ko) * 2007-06-07 2010-02-18 한국전자통신연구원 프로세스 간 통신을 이용한 오디오 복호화 장치 및 그 방법
JP5056600B2 (ja) * 2008-06-10 2012-10-24 富士通株式会社 画像復号装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457499A (en) * 1989-12-29 1995-10-10 Massachusetts Institute Of Technology Source adaptive television system
EP0719050A2 (fr) * 1994-12-23 1996-06-26 SIP SOCIETA ITALIANA PER l'ESERCIZIO DELLE TELECOMUNICAZIONI P.A. Dispositif pour la transmission, la réception et le décodage des flux de données audiovisuelles comprimées
GB2299237A (en) * 1995-03-21 1996-09-25 Samsung Electronics Co Ltd Video decoding apparatus
US5608459A (en) * 1993-08-13 1997-03-04 Texas Instruments Incorporated Video data decoder having motion compensation and image memory circuitry on single substrate
EP0776134A2 (fr) * 1995-11-22 1997-05-28 General Instrument Corporation Of Delaware Redressement d'erreur dans des données audio transportées dans un flux de paquets de données

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457499A (en) * 1989-12-29 1995-10-10 Massachusetts Institute Of Technology Source adaptive television system
US5608459A (en) * 1993-08-13 1997-03-04 Texas Instruments Incorporated Video data decoder having motion compensation and image memory circuitry on single substrate
EP0719050A2 (fr) * 1994-12-23 1996-06-26 SIP SOCIETA ITALIANA PER l'ESERCIZIO DELLE TELECOMUNICAZIONI P.A. Dispositif pour la transmission, la réception et le décodage des flux de données audiovisuelles comprimées
GB2299237A (en) * 1995-03-21 1996-09-25 Samsung Electronics Co Ltd Video decoding apparatus
EP0776134A2 (fr) * 1995-11-22 1997-05-28 General Instrument Corporation Of Delaware Redressement d'erreur dans des données audio transportées dans un flux de paquets de données

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001069934A1 (fr) * 2000-03-17 2001-09-20 Telecom Italia Lab S.P.A. Procede et systeme de transmission de flux d'information
EP1519588A2 (fr) * 2003-07-30 2005-03-30 Sony Corporation Programme, méthode de traitement de données, et système de traitement de données
EP1519588A3 (fr) * 2003-07-30 2007-06-13 Sony Corporation Programme, méthode de traitement de données, et système de traitement de données
US7664373B2 (en) 2003-07-30 2010-02-16 Sony Corporation Program, data processing method, and system of same
WO2006092671A1 (fr) * 2005-03-03 2006-09-08 Koninklijke Philips Electronics N.V. Systeme de secours adaptatif pour decodeurs mpeg
WO2010104432A1 (fr) * 2009-03-13 2010-09-16 Telefonaktiebolaget Lm Ericsson (Publ) Procédés et configurations permettant de traiter un flux binaire codé
US20110299593A1 (en) * 2009-03-13 2011-12-08 Martin Pettersson Methods of and Arrangements for Processing an Encoded Bit Stream
US9462233B2 (en) * 2009-03-13 2016-10-04 Telefonaktiebolaget Lm Ericsson (Publ) Methods of and arrangements for processing an encoded bit stream
CN102665081A (zh) * 2012-05-14 2012-09-12 青岛海信信芯科技有限公司 多格式码流的解析方法、多格式码流的解析装置和显示装置

Also Published As

Publication number Publication date
EP0956705A1 (fr) 1999-11-17
ID21549A (id) 1999-07-24
BR9806269A (pt) 2000-04-04
KR20000069051A (ko) 2000-11-25
KR100317919B1 (ko) 2001-12-24
JPH11112972A (ja) 1999-04-23
TW404116B (en) 2000-09-01
CN1241334A (zh) 2000-01-12

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