WO1999016044A1

WO1999016044A1 - Frame updating in interlaced animation systems

Info

Publication number: WO1999016044A1
Application number: PCT/US1998/020035
Authority: WO
Inventors: Nigel S. Keam
Original assignee: Microsoft Corporation
Priority date: 1997-09-23
Filing date: 1998-09-22
Publication date: 1999-04-01

Abstract

A system that produces animation includes an interlaced display device that alternately displays even and odd display rows during even and odd refresh periods, respectively. The system further includes one or more display frame buffers containing pixel values corresponding to pixels of even display rows and pixel values corresponding to pixels of odd display rows. A graphics rendering component renders graphics to said one or more display frame buffers for display on the interlaced display device. The graphics rendering component updates frame buffer pixel values corresponding to pixels of odd display rows only during even refresh periods, and updates frame buffer pixel values corresponding to pixels of even display rows only during odd refresh periods.

Description

FRAME UPDATING IN INTERLACED ANIMATION SYSTEMS TECHNICAL FIELD

This invention relates to computer-based systems that produce animation in conjunction with interlaced display devices.

BACKGROUND OF THE INVENTION

A development that has possibly contributed most to the field of output technology is that of raster graphics . In raster graphics, display primitives such as lines, characters, and solid areas (typically polygons), are stored in a frame buffer in terms of their component points, called pixels (short for "picture elements"). An image is formed from the raster. The image is a set of horizontal scan rows each made up of individual pixels. The raster is thus simply a matrix of pixel values corresponding to the pixels of an entire screen area. Specifically, the raster image maintained in the frame buffer corresponds to pixels that can be created on a cathode ray tube (CRT) or other line scanning device. In a CRT, pixels are illuminated individually by an electron beam (i.e., the cathode ray) that sequentially scans each row of pixels beginning with the top row and ending with the bottom row. The beam is deflected horizontally and vertically to scan or "refresh" an area of the screen to produce a single display frame. The rate at which the beam performs periodic top-to-bottom scans is referred to as the refresh rate. The electron beam strikes phosphors positioned at the screen of the CRT monitor to cause them to glow. The phosphors are arranged according to a desired pixel pattern, which is customarily a matrix of rows and columns. Conventional color VGA monitors have a resolution of 640 x 480 pixels or higher.

The use of raster graphics is widespread in computers and computer-based devices such a video games. Raster data typically resides in a frame buffer that is implemented within the computer's DRAM (dynamic randomly accessible memory). Typically, each pixel is represented by a multi-bit pixel value that specifies various attributes of the pixel such as color, luminance, etc.

To produce animation, it is necessary to establish the appropriate data in the frame buffer for sequential display frames. A display frame is a single still image rendered by the CRT by scanning all of its available pixels. The display frame rate is the rate at which sequential display frames are displayed. In most computer display devices, display frames are produced at the same rate as the refresh rate (often 60 Hz), by scanning the CRT's electron beam sequentially from top to bottom over all of a CRT's pixel rows. In some systems, however, interlaced CRT's are used. An interlaced CRT does not scan all pixels in a single pass of the electron beam. Rather, only every other row of pixels is scanned during a single top-to-bottom pass of the electron beam over the CRT surface. Even rows are refreshed or displayed during one such pass, and odd rows are refreshed or displayed during intervening passes. When an interlaced display is used, display frames are produced at a rate that is half of the refresh rate. Thus, half of the CRT pixels are refreshed each l/60^th of a second when the refresh rate is 60 Hz. The display frame rate in this example is 30 Hz.

When producing animation, it is important that data in the frame buffer remain static during CRT refreshes. If pixel data is changed during the middle of a display frame, an undesirable anomaly referred to as "tearing" can result (wherein moving objects appear to tear horizontally). Tearing is avoided in many high-performance systems by using two frame buffers, which are displayed alternately. While a previously generated frame is being displayed from one frame buffer, the next image is rendered to the non- displayed buffer (referred to as a "back" or "background" buffer). Once the new image has been completed, rendering ceases until the CRT completes its current display frame. Then, the frame buffers are swapped and rendering of the subsequent image is commenced to the frame buffer that had previously been displayed. The animation rate is the rate at which new images are rendered and actually displayed. It is desirable to achieve the highest possible animation rate. Typically, this is achieved when the animation rate matches the refresh rate — when the frame buffers are updated and alternated at the refresh rate. As discussed above, the display frame rate in most non-interlaced systems is 60 Hz or higher.

The animation rate of high performance rendering systems is typically limited by two basic factors (in addition to the display frame rate): the number of separate commands that the rendering system can process per second; and the number of memory writes (pixels) the system can achieve per second. For 3D display systems, these are referred to as the "polygon rate" and the "fill rate," respectively.

The invention described below is especially beneficial in cases where the animation rate is limited by the fill rate. In these cases, use of the invention can potentially double the maximum animation rate at a given refresh rate. In addition to this advantage, the amount of required frame buffer memory can often be dramatically reduced when using the invention.

SUMMARY OF THE INVENTION

The invention is a system and method for producing animation in systems using interlaced display devices. Effectively, two frame buffers are used for each display frame. Instead of each frame buffer containing the pixel values of an entire display frame, one of the frame buffers contains pixel values corresponding to even pixel rows of the display device, while the other frame buffer contains pixel values corresponding to odd pixel rows. In use, the frame buffer containing even pixels rows is updated while the CRT displays odd pixels rows, and the frame buffer containing odd pixel rows is updated while the CRT displays even pixel rows. In a typical system, this means that a 60 Hz animation rate can be achieved by writing only half of the pixels values that would otherwise be required to generate an entire display frame. Furthermore, if the system can guarantee successful generation of a new frame buffer every l/60^th of a second, there is no need for an independent back buffer. Instead, the system generates the pixel values for even rows while the odd rows are being displayed, then generates the pixel values for odd rows while the even rows are being displayed. The total frame buffer memory requirement is therefore half of what it might otherwise be when using prior art methods.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of a system in accordance with the invention.

Fig. 2 is a block diagram showing one frame buffer implementation in accordance with the invention.

Fig. 3 is a block diagram showing another frame buffer implementation in accordance with the invention.

Fig. 4 is a block diagram showing a previous value buffer in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Fig. 1 shows basic components of a computer system 15 that produces animation in conjunction with an interlaced display device 14 such as a CRT. In one embodiment, the system is a game controller that is used in conjunction with a television to produce interactive animation in response to operator input via buttons, a joystick, and/or other input mechanisms. In other embodiments, the computer system might be a desktop computer or other computer-based device the incorporates or can be connected to an interlaced CRT or other interlaced display device.

Computer system 15 includes a data processor 17 and some type of computer- readable non- volatile storage medium 19 containing instructions or programs that are executable by the computer system to perform desired tasks, including the methodological steps described herein. In the disclosed embodiment of the invention, the non- volatile memory is ROM (read-only memory) or battery-backed RAM (randomly accessible memory). The computer system also includes volatile memory 18 in the form of electronic RAM such as DRAM (dynamic randomly accessible memory).

CRT 14 is preferably a television receiver or a computer monitor. The CRT displays sequential display frames containing graphical images. A "display frame" or "frame" means a single, two-dimensional, screen-size image made up of a matrix of pixels corresponding to the available pixels on the CRT. CRT 14 has a refresh rate of 60 Hz, meaning that its cathode ray scan from top to bottom once every 1/60 or 0.01667 second. Since the CRT is of the interlaced type, however, the CRT alternately displays even and odd rows during consecutive refresh periods. Thus, only half of the CRT pixels are actually refreshed or displayed during each l/60^th second refresh period — the pixels of even rows are updated during every other l/60^th second refresh period, while the pixels of odd rows are updated during the intervening refresh periods. CRTs having higher refresh rates can also be used in conjunction with the invention. Computer system 15 also includes general I/O circuits 20 that interface with operator input devices such a buttons and joysticks.

As in most modern personal computer systems, the displayed matrix of display frame pixels is specified by a corresponding matrix of pixel values stored within memory 18. Specifically, the computer system has one or more frame buffers that are configured within memory 18 so that they contain pixel values corresponding to pixels of both even and odd display rows of CRT 14. A graphics component 24 referred to as a CRT timing and hardware driver reads pixel values from frame buffer 23 during each CRT scan to determine the color and intensity of each display frame pixel.

The computer system includes a graphics rendering component that renders graphics to the display frame buffer(s) for eventual display on interlaced display device 14. In less sophisticated embodiments, data processor 17 might form the graphics rendering component. In more capable systems, however, a dedicated graphics processor, such as graphics controller 21 shown, is used for graphics-intensive operations. The graphics controller executes graphics instructions that are provided by data processor 17, and writes resulting pixel values into frame buffer(s) 23. Such graphics controllers are found on widely available 2D and 3D graphics accelerator cards. A significant feature of the invention is that the graphics rendering component is configured to alternately update pixel values corresponding to even and odd rows, respectively. That is, the graphics rendering component modifies or updates frame buffer pixel values corresponding to pixels of odd display rows only during even refresh periods, and updates frame buffer pixel values corresponding to pixels of even display rows only during odd refresh periods. With a CRT having a 60 Hz refresh rate, a 60 Hz animation rate can be achieved while requiring only half of the available pixel values to be updated during every refresh period. Thus, for a system limited by its fill rate, twice the scene complexity can be animated at a given refresh rate than could have been achieved using prior art methods that used two full-size frame buffers. If the system can guarantee that it will be able to update either the odd or even rows during every refresh period, there is no need for an independent back buffer. Instead, the system generates the pixel values for even rows while odd rows are being displayed, and generates the pixel values for odd rows while even rows are being displayed. The total frame buffer size requirement is only that required to hold a single copy of all the pixel values, rather than twice that size as required in the prior art.

This scheme can be implemented in at least two different ways. As shown in Fig. 2, it can be implemented with only a single frame buffer 50 containing both even and odd rows of pixel values. In this case, application programs executed by data processor 17 act as if there are two independent frame buffers. When the graphics controller is instructed to write to the current "back" buffer, the graphics controller in actuality is configured to write only to the even or odd rows of the single frame buffer 50. One way to accomplish this on an existing graphics controller that is not designed to perform separate odd-line and even-line operations is to set the "stride" register (the stride value is the number of bytes between adjacent lines in a frame buffer) of the graphics controller to twice the normal value. Then, graphics operations on the left half of the display area appear on the even lines while operations on the right half of the display area appear on odd lines. The height of such operations should be halved, and the operations should be clipped to restrict changes to the appropriate half of the visible display lines.

As shown in Fig. 3, the system disclosed herein can also be implemented with two separate display frame buffers 52 that contain pixel values corresponding to even and odd display rows respectively. Assuming that the CRT has a selected vertical resolution such as 480 rows, each frame buffer has a vertical resolution of half that, or 240 rows. Application programs executed by data processor 17 act as if the display resolution is half of the CRT's selected vertical resolution, and that one of the buffers is a back buffer at any given time. The graphics controller is similarly configured to render graphics to the display frame buffers at half the selected vertical resolution of the CRT. Furthermore, the graphics controller is configured to adjust vertical rendering coordinates by half a row height when rendering to the display frame buffer corresponding to even display rows. More specifically, the graphics controller is configured to subtract a value equal to half a row height from y coordinates of every rendering command executed by the graphics controller with respect to the frame buffer that corresponds to even display rows. This compensates for the fact that the even rows are displayed below their counterpart odd rows.

On 3D graphics controllers using fixed or floating-point non-integer numbers, this is particularly easy. The half-line shift can be performed along with general 3D transformations by altering the transformation matrix. As a result, no additional mathematical operations are required once the transformation matrix has been calculated. o

Using either of these two implementations, an application program can execute just as it would under prior art schemes that implement background buffers, with the graphics controller taking care of required conversions and frame buffer manipulations.

As in other display systems, anti-flicker filtering might be desirable. Such well- known filtering techniques require, when updating a particular pixel value, that neighboring pixel values (or at least the luminance components of such values) be available. Filtering like this is typically performed by the CRT timing and hardware driver 24 (Fig. 1). When even rows are being displayed, driver 24 also needs pixel luminance values from neighboring odd rows. Since the odd rows are being rewritten, they are not available for use by the driver. Rather, the luminance values are stored in a previous value buffer for use in filtering the pixel values as they are displayed. Fig. 4 shows a system implemented with such a previous value buffer, designated by reference numeral 60.

Previous value buffer 60 is maintained by the display hardware. As even-line data is read from the frame buffer to be displayed, the odd-line luminance values are read from the previous value buffer to be blended with the even-line data. The odd-line luminance values are then replaced by the luminance values of the even lines. Subsequently, when odd-line data is read from the frame buffer to be displayed, even-line luminance data is available in the previous value buffer. In addition to the operational characteristics and features described above, the invention also includes methodological steps performed by data processor 17 and by graphics controller 21. Such steps comprise, generally, a step of alternately updating pixel values corresponding to even and odd display rows, respectively, in conjunction with an interlaced display device that alternately displays even and odd display rows. More specifically, the invention comprises a step of configuring one or more display frame buffers to have pixel values that correspond to pixels of even display rows and pixel values that correspond to pixels of odd display rows. During even refresh periods, the system performs a step of updating only those frame buffer pixel values corresponding to pixels of odd display rows. During odd refresh periods, the system performs a step of updating only those frame buffer pixel values corresponding to pixels of even display rows. In one embodiment, only a single frame buffer is used. In this embodiment, steps are performed of updating pixel values corresponding to even display rows while the display device displays odd display rows, and updating pixel values corresponding to odd display rows while the display device displays even display rows.

In another embodiment, a step is performed of configuring two separate display frame buffers containing pixel values corresponding to even and odd display rows, respectively. Each display frame buffer has a vertical resolution that is half of the selected vertical resolution of the display device. Further steps in accordance with this embodiment include rendering graphics to the display frame buffers at half the selected vertical resolution of the display device, and adjusting vertical rendering coordinates by half a row height when rendering to the display frame buffer containing even pixel rows. The frame buffer corresponding to even rows is updated during display of the odd rows, and the frame buffer corresponding to odd rows is updated during display of the even rows.

Optional steps include filtering pixel values to reduce flicker, and maintaining a previous value buffer for use in filtering the pixel values as they are updated.

The invention can be implemented with little or no cost, since no additional hardware is required. However, using the invention allows dramatically higher animation rates in systems using interlaced displays, while reducing the amount of required frame buffer memory. Although the invention has been described in language specific to structural features and/or methodological steps, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or steps described. Rather, the specific features and steps are disclosed as preferred forms of implementing the claimed invention.

Claims

1. A method of producing animation on an interlaced display device that alternately displays even and odd display rows; comprising a step of alternately updating pixel values corresponding to even and odd display rows, respectively.

2. A method as recited in claim 1, further comprising a step of configuring two separate display frame buffers to contain pixel values corresponding to even and odd display rows respectively.

3. A method as recited in claim 1, further comprising a step of configuring a single display frame buffer to includes pixel values corresponding to both even and odd display rows.

4. A method as recited in claim 1, the interlaced display device having a selected vertical resolution, the method further comprising the following additional steps: configuring two separate display frame buffers to contain pixel values corresponding to even and odd display rows respectively, each display frame buffer having a vertical resolution that is half of the selected vertical resolution of the display device; rendering graphics to the display frame buffers at said half of the selected vertical resolution of the display device; when rendering to one of the display frame buffers, adjusting vertical rendering coordinates by half a row height.

5. A method as recited in claim 1, the interlaced display device having a selected vertical resolution, the method further comprising the following additional steps: configuring two separate display frame buffers to contain pixel values corresponding to even and odd display rows respectively, each display frame buffer having a vertical resolution that is half of the selected vertical resolution of the display device; rendering graphics to a first of the display frame buffers at said half of the selected vertical resolution while the display device displays odd display rows; rendering graphics to a second of the display frame buffers at said half of the selected vertical resolution while the display device displays even display rows; when rendering to one of the display frame buffers, adjusting vertical rendering coordinates by half a row height.

6. A method as recited in claim 1 , further comprising the following additional steps: configuring a single display frame buffer to include pixel values corresponding to both even and odd display rows; updating pixel values corresponding to even display rows while the display device displays odd display rows; updating pixel values corresponding to odd display rows while the display device displays even display rows.

7. A method as recited in claim 1, further comprising a step of filtering the pixel values to reduce flicker.

8. A method as recited in claim 1, further comprising the following additional steps: filtering the pixel values to reduce flicker; maintaining a previous value buffer for use in filtering the pixel values as they are updated.

9. A method of producing animation on an interlaced display device that alternately displays even and odd display rows during even and odd refresh periods respectively, comprising the following steps: configuring one or more display frame buffers to have pixel values that correspond to pixels of even display rows and pixel values that correspond to pixels of odd display rows; during even refresh periods, updating only those frame buffer pixel values corresponding to pixels of odd display rows; during odd refresh periods, updating only those frame buffer pixel values corresponding to pixels of even display rows.

10. A method as recited in claim 9, wherein the configuring step includes configuring two separate display frame buffers containing pixel values corresponding to even and odd display rows respectively.

11. A method as recited in claim 9, wherein the configuring step includes configuring a single display frame buffer that includes pixel values corresponding to both even and odd display rows.

12. A method as recited in claim 9, the interlaced display device having a selected vertical resolution, wherein the configuring step includes configuring two separate display frame buffers containing pixel values corresponding to even and odd display rows respectively, each display frame buffer having a vertical resolution that is half of the selected vertical resolution of the display device, the method further comprising the following additional steps: rendering graphics to the display frame buffers at said half of the selected vertical resolution of the display device; when rendering to one of the display frame buffers, adjusting vertical rendering coordinates by half a row height.

13. A method as recited in claim 9, further comprising a step of filtering the pixel values to reduce flicker.

14. A method as recited in claim 9, further comprising the following additional steps: filtering the pixel values to reduce flicker; maintaining a previous value buffer for use in filtering the pixel values as they are updated.

15. A method as recited in claim 9, wherein each updating step is performed approximately 30 times per second.

16. A system that produces animation on an interlaced display device that alternately displays even and odd display rows, comprising: one or more display frame buffers containing pixel values that correspond to pixels of even display rows and pixel values that correspond to pixels of odd display rows; a graphics rendering component that alternately updates pixel values corresponding to even and odd display rows, respectively.

17. A system as recited in claim 16, wherein said one or more display frame buffers include two separate display frame buffers that contain pixel values corresponding to even and odd display rows respectively.

18. A system as recited in claim 16, wherein said one or more display frame buffers include only a single display frame buffer that includes pixel values corresponding to both even and odd display rows.

19. A system as recited in claim 16, wherein: the interlaced display device has a selected vertical resolution; said one or more display frame buffers include two separate display frame buffers that contain pixel values corresponding to even and odd display rows respectively, each display frame buffer having a vertical resolution that is half of the selected vertical resolution of the display device; the rendering component renders graphics to the display frame buffers at said half of the selected vertical resolution of the display device and adjusts vertical rendering coordinates by half a row height when rendering to one of the display frame buffers.

20. A system as recited in claim 16, wherein: the interlaced display device has a selected vertical resolution; said one or more display frame buffers include two separate display frame buffers that contain pixel values corresponding to even and odd display rows respectively, each display frame buffer having a vertical resolution that is half of the selected vertical resolution of the display device; the rendering component performs steps comprising: rendering graphics to a first of the display frame buffers at said half of the selected vertical resolution while the display device displays odd display rows; rendering graphics to a second of the display frame buffers at said half of the selected vertical resolution while the display device displays even display rows; when rendering to one of the display frame buffers, adjusting vertical rendering coordinates by half a row height.

21. A system as recited in claim 16, wherein: said one or more display frame buffers include only a single display frame buffer that includes pixel values corresponding to both even and odd display rows; the rendering component updates pixel values corresponding to even display rows while the display device displays odd display rows; the rendering component updates pixel values corresponding to odd display rows while the display device displays even display rows.

22. A system as recited in claim 16, further comprising an anti-flicker filter that filters the pixel values to reduce flicker.

23. A system as recited in claim 16, further comprising: an anti-flicker filter that filters the pixel values to reduce flicker; a previous value buffer for use in filtering the pixel values as they are updated.

24. A system that produces animation, comprising: an interlaced display device that alternately displays even and odd display rows during even and odd refresh periods, respectively; one or more display frame buffers containing pixel values corresponding to pixels of even display rows and pixel values corresponding to pixels of odd display rows; a graphics rendering component that renders graphics to said one or more display frame buffers for display on the interlaced display device; the graphics rendering component updating frame buffer pixel values corresponding to pixels of odd display rows only during even refresh periods; the graphics rendering component updating frame buffer pixel values corresponding to pixels of even display rows only during odd refresh periods.

25. A system as recited in claim 24, wherein said one or more display frame buffers include two separate display frame buffers that contain pixel values corresponding to even and odd display rows respectively.

26. A system as recited in claim 24, wherein said one or more display frame buffers include only a single display frame buffer that includes pixel values corresponding to both even and odd display rows.

27. A system as recited in claim 24, wherein: the interlaced display device has a selected vertical resolution; said one or more display frame buffers include two separate display frame buffers that contain pixel values corresponding to even and odd display rows respectively, each display frame buffer having a vertical resolution that is half of the selected vertical resolution of the display device; the rendering component renders graphics to the display frame buffers at said half of the selected vertical resolution of the display device and adjusts vertical rendering coordinates by half a row height when rendering to one of the display frame buffers.

28. A system as recited in claim 24, further comprising an anti-flicker filter that filters the pixel values to reduce flicker.

29. A system as recited in claim 24, further comprising: an anti-flicker filter that filters the pixel values to reduce flicker; a previous value buffer for use in filtering the pixel values as they are updated.

30. A computer-readable storage medium containing instructions for producing animation on an interlaced display device that alternately displays even and odd display rows during even and odd refresh periods respectively, the instructions being executable by a computer to perform the following steps: configuring one or more display frame buffers to have pixel value that correspond to pixels of even display rows and pixel values that correspond to pixels of odd display rows; configuring a graphics rendering component to update only those frame buffer pixel values corresponding to pixels of odd display rows during even refresh periods; configuring the graphics rendering component to update only those frame buffer pixel values corresponding to pixels of even display rows during odd refresh periods.

31. A computer-readable storage medium as recited in claim 30, wherein the step of configuring one or more display frame buffers includes configuring two separate display frame buffers containing pixel values corresponding to even and odd display rows respectively.

32. A computer-readable storage medium as recited in claim 30, wherein the step of configuring one or more display frame buffers includes configuring a single display frame buffer that includes pixel values corresponding to both even and odd display rows.

33. A computer-readable storage medium as recited in claim 30, the interlaced display device having a selected vertical resolution, wherein the step of configuring one or more display frame buffers includes configuring two separate display frame buffers containing pixel values corresponding to even and odd display rows respectively, each display frame buffer having a vertical resolution that is half of the selected vertical resolution of the display device, the instructions being executable to configure the graphics rendering component to perform the following steps: rendering graphics to the display frame buffers at said half of the selected vertical resolution of the display device; when rendering to one of the display frame buffers, adjusting vertical rendering coordinates by half a row height.