WO1999014800A1 - Procede et dispositif pour la realisation d'interconnexions sur circuit integre haute performance - Google Patents

Procede et dispositif pour la realisation d'interconnexions sur circuit integre haute performance Download PDF

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Publication number
WO1999014800A1
WO1999014800A1 PCT/US1998/019367 US9819367W WO9914800A1 WO 1999014800 A1 WO1999014800 A1 WO 1999014800A1 US 9819367 W US9819367 W US 9819367W WO 9914800 A1 WO9914800 A1 WO 9914800A1
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Prior art keywords
layer
tin
copper
depositing
globally planarized
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PCT/US1998/019367
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English (en)
Inventor
Mehrdad M. Moslehi
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Cvc Products, Inc.
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Application filed by Cvc Products, Inc. filed Critical Cvc Products, Inc.
Priority to EP98947076A priority Critical patent/EP1018149A1/fr
Priority to KR1020007002846A priority patent/KR20010024096A/ko
Priority to JP2000512243A priority patent/JP2001516970A/ja
Publication of WO1999014800A1 publication Critical patent/WO1999014800A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only

Definitions

  • This invention relates in general to the field of semiconductor integrated circuit fabrication, and more particularly to a method and apparatus for multi-level interconnect fabrication for high performance semiconductor chips.
  • Integrated circuits fabricated on semiconductor substrates typically have multiple metal layers, interconnected by contact or via plugs and separated by insulator layers, that provide electrical connections among devices formed on a silicon (or other semiconductor material such as GaAs) substrate. These on-chip interconnects thereby provide signal communication paths among the transistors and/or other active/passive devices fabricated on the monolithic integrated circuit chip.
  • the multilevel on-chip interconnects in state-of-the-art silicon integrated circuits, typically use aluminum (or aluminum alloys such as Al/0.5% Cu) as the electrical conductor and silicon dioxide or an alternative lower permitivity dielectric materials (e.g., an organic low-k material or an inorganic low-k material, such as fluorinated silicon oxide or Si x O y F z ) as the interlevel/inter-metal insulator.
  • aluminum or aluminum alloys such as Al/0.5% Cu
  • an alternative lower permitivity dielectric materials e.g., an organic low-k material or an inorganic low-k material, such as fluorinated silicon oxide or Si x O y F z
  • the process flow for multilevel interconnect fabrication starts after completion of the transistor fabrication process flow (often called Front- End-of-the-Line or FEOL) .
  • ICs State-of-the-art silicon integrated circuits (ICs) often employ either tungsten plugs or aluminum plugs to form the conductive via plugs for making electrical contacts between different levels of metal interconnects in conjunction with aluminum (or an aluminum alloy such as Al/0.5% Cu) metal interconnect lines .
  • an improved method and apparatus for high-performance interconnect fabrication is disclosed that provides advantages over conventional interconnect fabrication process flows.
  • a method for interconnect fabrication on a semiconductor integrate circuit Trenches are formed in an insulator layer for conductive lines, and holes are formed in the insulator layer for plugs to connect to an underlying conductive metallization layer.
  • a first conductive layer is then formed above the insulating layer (or a glue/barrier layer deposited over the insulating layer) and filling the trenches and the vias .
  • a globally planarized layer is formed above the first conductive layer. The globally planarized layer and at least a portion of the first conductive layer are then removed, and the removing is stopped when both layers have been removed except for material from the first conductive layer filling the trenches and the holes.
  • the first conductive layer is a copper layer
  • the globally planarized layer is either a tin layer or an alloy containing tin.
  • the removing process is accomplished by an ion-beam etch process which is stopped based upon a real-time measured reflectance of the surface of the integrated circuit.
  • a method for removing conductive layers from an integrated circuit in order to form either single-damascene or dual-damascene structures. The method includes removing conductive layers from a surface of a wafer being processed and producing a globally planarized surface with embedded patterned interconnect lines and plugs.
  • a reflectance of the surface of the wafer is measured while the globally planarized disposable layer and the conductive layer are being removed.
  • the removal of the disposable and the conductive layers is then stopped when the surface reflectance goes through certain transitions and matches an expected end-point value.
  • the expected end-point value is observed after going through a number of expected transitions between various surface reflectance values.
  • an apparatus for high-performance interconnect fabrication on an integrate circuit.
  • the apparatus includes a cluster tool central wafer handler, a vacuum load lock chamber, and preferably a cleaning process module.
  • the apparatus also includes a second deposition process module for depositing a conductive liner/barrier layer, a third deposition process module for depositing a conductive interconnect metal layer, and a fourth deposition process module for depositing a globally planarized disposable material layer.
  • the apparatus further includes an etch process module for removing the disposable material layer and at least a portion of the conductive interconnect metal layer.
  • the load lock chamber and all of the process modules are mounted on a cluster tool platform.
  • a technical advantage of the present invention is the formation of embedded high-performance interconnects (such as with copper) using a clusterable process flow without a need for metal chemical-mechanical polishing (CMP) .
  • CMP metal chemical-mechanical polishing
  • the methodology and process flow of the present invention results in formation of a globally planarized integrated circuit surface without a need for a relatively expensive CMP process.
  • a globally planarized chip surface is an essential requirement for enhanced manufacturing yield of advanced integrated circuits (particularly due to the relatively stringent depth-of-focus requirements of advanced optical lithography tools) .
  • Another technical advantage of the present invention by not employing wet processing, is the elimination of the significant waste generation and disposal problems associated with the CMP process of conventional copper interconnect fabrication processes. This can result in improved environmental impact and reduced cost of ownership for the metallization process flow.
  • Another technical advantage of the present invention is reduced manufacturing cycle time due to the cluster tool implementation of the interconnect process flow.
  • FIGURE 1 is a flowchart of a conventional prior art process flow for fabrication of multilevel aluminum interconnects using tungsten plugs (current mainstream technology) ;
  • FIGURE 2 is a flowchart of a conventional prior art process flow for a dual-damascene multilevel copper interconnect structure
  • FIGURES 3A, 3B, 3C and 3D are cross sections of a portion of an integrated circuit interconnect structure after steps in the process flow of FIGURE 2;
  • FIGURE 4 is a block diagram of one embodiment of a cluster tool implementation for interconnect fabrication according to the present invention.
  • FIGURES 5A and 5B provide a block diagram of an alternate cluster tool implementation for interconnect fabrication according to the present invention
  • FIGURE 6 is a cross section of a portion of an integrated circuit after the deposition of a globally planarized tin (or an alloy containing tin) layer according to the present invention
  • FIGURE 7 is a diagram of real-time optical reflectance measured during the ion-beam etch processing of the integrated circuit of FIGURE 6 used for the purpose of real-time etch process end-pointing;
  • FIGURE 8 is a flowchart of a process flow for fabrication of a multilevel copper interconnect structure according to the present invention.
  • FIGURE 1 is a flowchart of a conventional prior art process flow for fabrication of multilevel aluminum interconnects using tungsten plugs on silicon integrated circuitry.
  • the transistor (and other device) fabrication process is completed (Front- End-of-the-Line (FEOL)) on the silicon wafer.
  • interlevel dielectric (ILD) material is deposited, usually using a plasma-enhanced chemical-vapor deposition (PECVD) or a thermal chemical-vapor deposition (CVD) process.
  • PECVD plasma-enhanced chemical-vapor deposition
  • CVD thermal chemical-vapor deposition
  • CMP chemical-mechanical polishing
  • the dielectric layer is globally planarized. Additional interlevel dielectric (ILD) is then deposited (by thermal CVD or PECVD) in step 16 to establish the desired thickness.
  • the interconnect contact holes are formed by microlithography patterning and anisotropic etch such as reactive ion etch (RIE) .
  • RIE reactive ion etch
  • a liner/barrier layer is then deposited in step 20 by, for instance, a collimated physical-vapor deposition (PVD) process. This layer may serve both as a diffusion barrier and an adhesion layer.
  • tungsten contact plugs are formed by chemical-vapor deposition (CVD) of tungsten and subsequent chemical-mechanical polishing (CMP) .
  • a first metal layer is then deposited in step 24 by sputter deposition of an aluminum alloy (e.g., Al/0.5% Cu) .
  • the metal interconnect lines are formed in step 26 by microlithography and metal etch such as an RIE process.
  • an interlevel (or intermetal) dielectric (ILD) is deposited by a suitable deposition process such as plasma enhanced CVD (PECVD) or spin-on dielectric formation.
  • PECVD plasma enhanced CVD
  • This dielectric layer is then globally planarized in step 30 using dielectric chemical-mechanical polishing (CMP) followed by post-CMP clean. Subsequently, an additional dielectric layer may be deposited in step 32 to establish the desired ILD thickness .
  • a microlithography patterning step and a reactive-ion etch (RIE) step are performed for formation of via holes (for connections between the first metal layer and a second metal layer) .
  • a liner/barrier layer is deposited by either a collimated PVD process or an MOCVD process, and, in step 38, tungsten plugs for the vias are formed by chemical- vapor deposition (CVD) of tungsten and subsequent metal chemical-mechanical polishing.
  • the second metal layer is then deposited, in step 40, by sputter deposition of an aluminum alloy (e.g., Al/0.5% Cu) .
  • the metal interconnects are formed, in step 42, by microlithography patterning and metal reactive-ion etch (RIE).
  • step 44 if more metal interconnect levels are needed, the process flow is repeated starting at step 28. If not, then the process continues at step 46 with deposition of a passivation overlayer by plasma- enhanced chemical-vapor deposition (PECVD) . Then, in step 48, bonding pad openings are formed by microlithography patterning and dielectric etch. Chip packaging is then accomplished in step 50 to form the final integrated circuit product.
  • PECVD plasma- enhanced chemical-vapor deposition
  • the interconnect process flow of FIGURE 1 employs dielectric chemical-mechanical polishing (CMP) to form a globally planarized interlevel/intermetal dielectric surface prior to formation of the subsequent plugs and interconnect level.
  • CMP dielectric chemical-mechanical polishing
  • a globally planar surface facilitates the microlithography patterning process control and is essentially a requirement for 0.25_m technologies and beyond.
  • a global planarization process typically improves the overall chip manufacturing yield and enables fabrication of multi-level interconnects with increased number of interconnect levels.
  • some semiconductor fabrication technologies employ aluminum (or an alloy of Al such as Al/0.5% Cu) , instead of tungsten, to form the conductive interlevel/intermetal plugs (for contacts and vias) .
  • This approach would employ an aluminum reflow sputtering process or PVD reflow and would result in a less complex interconnect fabrication process flow, improved interconnect reliability, improved interconnect performance (due to lower resistance plugs) , and improved fabrication yield.
  • PVD reflow physical-vapor-deposition reflow or PVD reflow
  • tungsten deposition, CMP of tungsten, post-CMP clean, liner/barrier layer deposition, and aluminum or aluminum alloy metal deposition into a single metal deposition step by PVD reflow, thus, resulting in a significant process simplification.
  • An alternative approach would be to form the Al plug by metal-organic chemical-vapor deposition (MOCVD) of Al followed by PVD and Al/0.5% Cu to form the interconnect lines.
  • MOCVD metal-organic chemical-vapor deposition
  • the combination of copper metallization with low-k interlevel/intermetal dielectrics enables enhanced chip performance, improved interconnect reliability, and reduced chip manufacturing cost (due to the reduced number of metal interconnect levels required with Cu/low-K compared to the Al/Si0 2 interconnect material system) for a given chip performance.
  • CMP copper chemical-mechanical polishing
  • the damascene and dual-damascene techniques are the preferred and proven methods for fabrication of copper interconnects.
  • FIGURE 2 is a flowchart of a conventional process flow for a dual-damascene multilevel copper interconnect structure fabrication.
  • the transistor (and other device) fabrication process is first completed (FEOL) .
  • the interlevel dielectric (ILD) material e.g., silicon dioxide or a suitable low-k material
  • the dielectric is then planarized, in step
  • step 56 by chemical-mechanical polishing (CMP) followed by a post-CMP clean process.
  • step 58 additional interlevel dielectric is deposited by PECVD or CVD to establish the desired thickness.
  • Contact holes are formed, in step 60, by microlithography patterning and reactive ion etch (RIE) .
  • a thin liner/barrier layer is then deposited, in step 62, by collimated physical-vapor deposition (PVD) or metal-organic chemical-vapor deposition (MOCVD) .
  • step 64 a copper layer is deposited using, for example, metal-organic chemical-vapor deposition (MOCVD) , physical-vapor deposition (PVD) or plating (or a combination of these methods) .
  • MOCVD metal-organic chemical-vapor deposition
  • PVD physical-vapor deposition
  • plating or a combination of these methods
  • the copper layer is planarized, in step 66, by metal chemical-mechanical polishing (CMP) followed by a post-CMP clean process.
  • Multilayer interlevel (intermetal) dielectric is then deposited in step 68 (e.g., SiN/Si0 2 /SiN/Si0 2 ) .
  • the SiN layers will be used as etch stop layers during formation of the metal trenches and via holes.
  • step 70 microlithography patterning and an anisotropic dielectric etch are performed to form trenches for embedded metal lines of the first metal layer.
  • step 72 microlithography patterning and another anisotropic dielectric etch are performed to form via holes.
  • a thin liner/barrier layer is deposited using, for example, collimated physical-vapor deposition (PVD) or metal- organic chemical-vapor deposition (MOCVD) .
  • a copper layer is deposited using, for example, metal-organic chemical-vapor deposition (MOCVD) , physical-vapor deposition (PVD) or plating (or a combination of any two methods) .
  • the copper layer is planarized, in step 78, by chemical-mechanical polishing (CMP) followed by post-CMP clean, resulting in embedded patterned copper interconnect lines and plugs.
  • CMP chemical-mechanical polishing
  • step 80 it is determined whether or not more interconnect levels are needed. If not, the process continues at step 82 and a passivation overlayer is deposited by plasma-enhanced chemical-vapor deposition (PECVD). Bonding pad openings are formed, in step 84, by microlithography patterning and dielectric etch, and final chip packaging is accomplished in step 86.
  • PECVD plasma-enhanced chemical-vapor deposition
  • FIGURE 3A is a cross section of a portion of an integrated circuit interconnect structure after this step 68 in the process flow.
  • FIGURE 3A shows a lower level of copper interconnect line 88 in conjunction with a copper via plug 89.
  • a conductive liner/barrier layer 90 separates copper interconnect lines 88 and plugs 89 from adjacent interlevel dielectric layers 92 and 94 (e.g., Si0 2 and SiN, respectively) .
  • the subsequently deposited multilevel dielectric layers 96 e.g., SiN
  • 98 e.g., Si0 2
  • the stacked dielectric structure e.g., SiN/Si0 2 /SiN/Si0 2
  • FIGURE 3B is a cross section of the integrated circuit interconnect structure of FIGURE 3A following the microlithography patterning and dielectric etch process steps of 70 and 72 in FIGURE 2.
  • metal line trenches 99 and via holes 100 have been formed in the dielectric layers 96 and 98 (which are now planarized layers as deposited) .
  • FIGURE 3C shows a cross section of the integrated circuit interconnect structure after deposition of liner/barrier and copper layers (after steps 74 and 76 in FIGURE 2) .
  • a thin conductive liner/barrier layer 102 and a new copper layer 104 have been deposited above the existing interconnect levels.
  • FIGURE 3D is a cross section of the integrated circuit interconnect structure after step 78 in which copper layer 104 was planarized and both copper and liner/barrier layers were removed from the top surface of dielectric layer 98.
  • One significant advantage of a dual-damascene interconnect process is that both the interlevel conductive plugs (contacts/vias) and the metal lines are formed by a single copper deposition process step (or a single multi-step deposition process sequence) .
  • Another advantage of the dual damascene copper interconnect structure and process flow is that, beyond the first interlevel dielectric layer, the subsequent intermetal dielectric layers are deposited on globally planarized surfaces and remain globally planarized in the as- deposited condition.
  • the intermetal dielectric deposition steps do not require any CMP dielectric polishing steps, resulting in process simplification.
  • the conventional damascene or dual- damascene copper interconnect processes described above suffer from problems and relatively high fabrication cost due to the requirement to use chemical-mechanical polishing (CMP) of the copper to form the embedded copper metal interconnect lines and plugs.
  • CMP chemical-mechanical polishing
  • the CMP process is a relatively complex and expensive process which requires a significant amount of consumables such as polishing pads and slurry.
  • the CMP process is a stand-alone wet process and cannot be easily integrated on a cluster tool with the preceding or subsequent process steps.
  • CMP can cause device damage and wafer contamination, and requires effective post-CMP cleaning. Therefore, it would be highly desirable if a process flow could be developed that would enable formation of globally planarized embedded copper interconnects using single or dual damascene approach without a need for copper CMP.
  • a method and apparatus that allow formation of embedded copper interconnects (lines and plugs) using a clusterable process flow without a need for copper CMP.
  • the process flow of the present invention results in formation of a globally planarized surface without a need for CMP.
  • the process flow does not employ wet processing and eliminates the significant waste generation and disposal problems associated with the current CMP processes. For instance, a typical CMP process with a slurry flow rate of 300 cc/min. and a process time of 3 min. /wafer consumes 900 cc/wafer of slurry.
  • FIGURE 4 is a block diagram of one embodiment of a cluster tool implementation of the present invention. It should be apparent that various other implementations are possible within the teachings of the present invention.
  • a cluster tool indicated generally at 110, includes a cluster tool platform or central wafer handler 112.
  • Vacuum load lock modules 114 and 116 provide a means for loading and unloading wafers through wafer cassettes.
  • cluster tool 110 has six process modules connected to the central wafer handler for processing the wafers. These include a soft plasma cleaning module 118 (such as an inductively-coupled plasma or ICP module) , a metal-organic chemical- vapor deposition (MOCVD) module 120 for conformal deposition of a thin liner/barrier layer (such as TiN or TaN) , and another MOCVD module 122 to deposit copper.
  • a soft plasma cleaning module 118 such as an inductively-coupled plasma or ICP module
  • MOCVD metal-organic chemical- vapor deposition
  • a thin liner/barrier layer such as TiN or TaN
  • another MOCVD module 122 to deposit copper.
  • the modules also include a physical-vapor deposition (PVD) module 124 for sputter deposition of a suitable low melting point/high boiling point (or extremely low vapor pressure in the molten state above or near the melting point) elemental or compound material (such as tin, indium, or bismuth, or their alloys) .
  • PVD physical-vapor deposition
  • the modules include two ion- beam etch (IBE) (also called ion milling) modules 126 and 128.
  • IBE ion- beam etch
  • the invention is applicable where the liner/barrier is formed by physical-vapor deposition (PVC) instead of MOCVD, is also applicable where copper is deposited by a PVD and/or plating process or a hybrid MOCVD/plating or PVD/plating process or MOCVD/PVD process, and is further applicable where another interconnect metal material such as gold, aluminum or silver is used instead of copper.
  • PVC physical-vapor deposition
  • this embodiment of the present invention can be implemented on a single vacuum- integrated cluster tool 110 such as the one shown.
  • the wafers can be then loaded into one of the vacuum load lock chambers 114 or 116 (LL 2 or LL 2 ) attached to the vacuum-integrated cluster tool 110.
  • this cluster tool 110 has six single-wafer or mini-batch process modules 118 through 128 ⁇ ⁇ >M 1 through PM 6 ) as described above .
  • FIGURES 5A and 5B provide a block diagram of an alternate cluster tool implementation of the present invention.
  • cluster tool 130 has a platform 134 and two vacuum load lock chambers 136 and 138.
  • Cluster tool 130 includes four process modules: an ICP soft clean module 140, MOCVD liner/barrier layer module 142, and MOCVD copper deposition modules 144 and 146.
  • Cluster tool 132 similarly has a platform 148 and vacuum load lock chambers 150 and 152.
  • the four process modules of cluster tool 132 are: a PVD tin (or a tin alloy) deposition module 154, and three IBE modules 156, 158 and 160.
  • FIGURES 5A and 5B While the dual six-sided cluster tool implementation of FIGURES 5A and 5B is functionally equivalent to the single eight-sided cluster tool implementation of FIGURE 4, the former can provide a higher fabrication throughput due to the use of multiple MOCVD copper deposition modules 144 and 146 and the IBE modules 156, 158 and 160, which perform the slower process steps (copper deposition and ion milling) of the interconnect process flow.
  • the subsequent description and discussion is presented in reference to the eight-sided cluster tool implementation of FIGURE 4, it is applicable to the implementation of FIGURES 5A and 5B as well as alternate implementations within the scope of the present invention.
  • each wafer contains the dual-damascene dielectric trench and contact/via hole structure such as that shown in FIGURE 3B.
  • each wafer is first processed in the ICP soft clean module 118 in order to remove any etch-induced contaminants and any native oxide on any underlying exposed copper surfaces and dielectric trench surfaces.
  • the wafer is then transferred into the MOCVD liner/barrier module 120 in order to deposit a suitable thin liner/barrier layer such as TiN, Ta, or TaN (the layer thickness may be 100 __ to 300 _) .
  • a collimated PVD or directional ionized PVD module may alternatively be used instead of the MOCVD module, although MOCVD provides a superior process conformality and sidewall/bottom coverage compared to PVD.
  • the wafer is then moved into the MOCVD copper process module 122 in order to deposit a blanket layer of copper. This fills up the dielectric trenches formed for embedded copper metal lines as well as the contact or via holes reserved for interlevel or intermetal conductive copper plugs.
  • the copper layer is thick enough so that the lowest point on the final copper layer surface is above the globally planarized dielectric surface by a comfortable margin.
  • a conformal copper deposition process such as with MOCVD, ensures void-free filling of the high-aspect-ratio trenches and holes. While the illustrated embodiment of this invention is shown using an MOCVD process to form the copper interconnect regions, the process flow of this invention is also applicable to interconnect formation using alternative methods of copper deposition, such as a combination of MOCVD copper seed layer or PVD copper seed layer formation followed by plating, or complete formation of copper lines/plugs by a PVD reflow process (or combination of an MOCVD copper seed layer followed by a PVD copper reflow process) .
  • the wafer is then moved into the PVD tin (PVD-Sn) process module 124 in order to deposit a relatively thick layer of tin (or any metallic element or alloy with a low melting point and preferably a relatively high boiling point) and then globally planarize the tin layer in situ.
  • the tin layer thickness can be on the order of 5,000 Angstroms to over 2 _m such that it is made significantly (e.g. several times) larger than the peak-to-peak height variation on the surface of deposited copper layer.
  • Deposition of tin can be performed either at room temperature (or near room temperature) or at a temperature above the melting point of tin (e.g., 232 ' C) .
  • the wafer is then heated (preferably in situ in the PVD-Sn module 124) to a temperature slightly over the melting point of tin (e.g., to 250 * C or as 350 * C) for a short period of time (e.g., for 1 to 60 seconds).
  • a temperature slightly over the melting point of tin e.g., to 250 * C or as 350 * C
  • a short period of time e.g., for 1 to 60 seconds.
  • the liquid tin medium becomes globally planarized immediately upon melting due to its high liquid-state surface tension and very low viscosity, and the tendency of the liquid metal medium to achieve minimum surface energy.
  • the wafer is then cooled (preferably rapidly) back to a temperature below the melting point of tin (e.g., as 150 * C) , for instance by rapid chuck cooling, prior to removal of the wafer from the PVD-Sn module 124.
  • the tin deposition process may also be performed while the wafer temperature is kept at above the melting point of tin which is 232 " C (e.g., at a temperature between 250 ' C and 350° C) .
  • tin module 124 This results in a globally planarized liquid tin layer over the copper surface by the time the deposition process is completed. Again, the wafer is then rapidly cooled down to below the melting point of tin (e.g., to as 150 ' C) to resolidify the globally planarized liquid tin layer before it is removed from the tin module 124.
  • tin melting point
  • Any suitable metal or metallic alloy with a relatively low melting point (preferably below 350° C) and preferably a relatively high boiling point may be used instead of tin. These include indium, bismuth, any binary or tertiary alloys containing tin and/or indium and/or bismuth, and any suitable alloys of tin or indium or bismuth containing lead.
  • the wafer with deposited copper and globally planarized tin layer is then loaded into one of the ion- beam etch (IBE) modules 126 or 128.
  • the cluster tool 110 of FIGURE 4 has two IBE modules 126 and 128 for increased fabrication throughput.
  • Each IBE module 126 and 128 preferably has an optical endpoint detection sensor, such as an optical reflectance sensor, which can recognize the reflectance changes and transitions between the surface of tin and the underlying copper and the surface of the underlying interlevel insulator with embedded copper lines and plugs.
  • the IBE module 126 or 128 performs a blanket physical etch process over the entire wafer surface with a good etch uniformity (e.g., 1& non- uniformity as 3% over 200mm wafer area) .
  • FIGURE 6 is a cross section of a portion of an integrated circuit interconnect structure after the deposition of a globally planarized tin (or a low- melting-point alloy containing tin, indium, and/or bismuth) layer according to the present invention.
  • a lower copper interconnect line 162 and copper plug 163 have adjacent liner/barrier layer 164 (e.g., TiN, Ta, TaN, WN X , or a ternary liner/barrier such as TiN or TaSiN) separated by an interlayer dielectric 166 (e.g, Si0 2 ) .
  • a multilayer dielectric e.g.,
  • SiN/Si0 2 /SiN/Si0 2 is formed by layers 168 and 170, and a subsequent liner/ barrier layer 172 (e.g., TiN, Ta, TaN, WN X , or a ternary liner/barrier such as TiSiN or TaSiN) is formed above the multilayer dielectric layers 168 and 170.
  • a copper layer 174 is subsequently formed above liner/barrier layer 172, and a globally planarized tin (or a low-melting-point alloy containing tin, indium, and/or bismuth) layer 176 is formed above copper layer 174.
  • FIGURE 7 is a diagram of an optical reflectance signal during the ion-beam etch processing of the integrated circuit interconnect structure of FIGURE 6.
  • the laser or optical reflectance sensor of the IBE module 126 or 128 first measures the surface reflectance of blanket metallic tin layer (R x ) . This reflectance remains the same until the ion milling process begins to break through the tin layer 176 at the thinnest regions of tin (corresponding to the peak copper heights) . This transition from tin to copper results in a transition in the optical reflectance measurement (for instance, from an R x value to a higher R 2 value) .
  • the IBE process is then continued until the liner/barrier layer 172 is cleared from the ILD top surface of layer 170. This corresponds to a third transition (transition #3) from a reflectance of R 3 to R 4 . This third transition signals the endpoint of the sensor-based IBE process.
  • the wafer has embedded copper lines and plugs with a globally planarized surface where the patterned interconnect formation and global surface planarization have been accomplished in a vacuum-integrated cluster tool environment without a need for CMP. If desired, the wafers can be directly transferred to another cluster tool for deposition of the subsequent ILD stack.
  • FIGURE 8 is a flowchart of a process flow for fabrication of a multilevel copper interconnect structure according to the present invention.
  • step 170 the transistor (and other front-end device) fabrication process flow has been completed (FEOL) .
  • step 172 interlevel dielectric material (IDL) is deposited, and, in step 174, the dielectric is planarized by physical-vapor deposition (PVD of tin (Sn) and ion-beam etch (IBE) ) . Additional interlayer dielectric (ILD) is deposited in step 176 to establish the desired thickness.
  • step 178 contact holes are formed by microlithography patterning and reactive-ion etch.
  • a liner/barrier layer is deposited, in step 180, by MOCVD or PVD, and a copper layer is deposited, in step 182, by MOCVD, PVD and/or plating.
  • a tin (or a low-melting-point alloy containing tin, indium, and/or bismuth) layer is deposited using physical-vapor deposition (or another deposition method) and is melted and solidified in situ. This step forms a globally planarized tin (or metallic alloy) layer.
  • the tin layer is processed and removed along with removal of a fraction of the copper and liner/barrier layer by an ion-beam etch (IBE) to leave a globally planarized surface and to produce the patterned and embedded copper interconnect lines and plugs.
  • a multilayer intermetal dielectric is deposited in step 188 comprising, for example, alternating SiN and Si0 2 layers.
  • step 190 trenches for embedded metal lines are formed by microlithography patterning and dielectric anisotropic (e.g., RIE) etch, and, in step 192, via holes also are formed by microlithography patterning and dielectric (e.g., RIE) etch.
  • step 194 a liner/barrier layer is deposited by MOCVD or PVD followed by deposition, in step 196, of a copper layer by, for example, MOCVD, PVD and or plating.
  • a tin (or a low-melting-point element or alloy consisting of tin, indium, and/or bismuth) layer is deposited by PVD and melted and solidified in situ to create a globally planarized tin (or another metallic) layer.
  • the tin layer and at least a fraction of copper and liner/barrier layers are removed by ion-beam etch as described above to leave a planarized surface with the embedded and patterned copper lines and via plugs.
  • step 202 it is determined whether more interconnect levels are needed. If so, the process flow returns and continues at step 188. If not, the process flow continues with step 204 and a passivation overlayer is deposited. In step 206, bonding pad openings are formed by microlithography patterning and dielectric etch, and the chip is packaged in step 208. While the description of the above embodiment of the present invention was based on the use of tin as the global planarization layer, other materials can be used, such as indium, bismuth, or any suitable low melting point (e.g., below 350 ' C) alloys of tin, indium, bismuth, lead, or other suitable elements.
  • RIE reactive ion etch

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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

L'invention concerne un procédé et un dispositif permettant de réaliser des interconnexions multiniveau sur circuit intégré. Une couche de garniture/d'arrêt (172) et une couche conductrice (174) sont déposées, de manière à remplir les saignées et les orifices d'une couche isolante. Une couche consommable de structure globalement planar (176) est ensuite formée sur la couche conductrice (174). Après quoi, on ôte les couches selon des taux sensiblement analogues d'extraction de matériau, et le processus d'élimination en question prend fin lorsque les deux couches ont été arrachées, sauf pour la matière de la couche conductrice remplissant les saignées et les orifices. Selon une variante, la couche conductrice (174) est en cuivre, et la couche consommable de structure globalement planar (176) est en étain ou en alliage d'étain, sa formation comprenant les phases de dépôt, de fusion et de resolidification. Par ailleurs, l'élimination des matériaux peut être effectuée sous gravure ionique, opération que l'on interrompt d'après le résultat de mesures de réflectance en temps réel in situ à la surface des plaquettes. Le procédé fait appel à un système d'outil multiposte.
PCT/US1998/019367 1997-09-18 1998-09-17 Procede et dispositif pour la realisation d'interconnexions sur circuit integre haute performance WO1999014800A1 (fr)

Priority Applications (3)

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EP98947076A EP1018149A1 (fr) 1997-09-18 1998-09-17 Procede et dispositif pour la realisation d'interconnexions sur circuit integre haute performance
KR1020007002846A KR20010024096A (ko) 1997-09-18 1998-09-17 고성능 집적 회로 배선 제조 방법 및 장치
JP2000512243A JP2001516970A (ja) 1997-09-18 1998-09-17 高性能集積回路の相互接続製造の方法及び装置

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US93342097A 1997-09-18 1997-09-18
US08/933,420 1997-09-18

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005076348A1 (fr) * 2004-01-30 2005-08-18 Lam Research Corporation Systeme et procede de reduction, passivation, prevention de corrosion et activation de surface en cuivre
EP1611599A2 (fr) * 2003-03-14 2006-01-04 Lam Research Corporation Systeme, procede et appareil de planarisation locale amelioree par dual-damascene (methode de realisation d'interconnexions multi-niveaux avec de fortes densites)
WO2008064491A1 (fr) * 2006-12-01 2008-06-05 D-Wave Systems, Inc. Blindage superconducteur pour circuit intégré utilisé en informatique quantique
DE10064041B4 (de) * 1999-12-22 2009-09-10 Hyundai Electronics Industries Co., Ltd., Ichon Verfahren zur Herstellung einer Kupferverdrahtung in einem Halbleiterbauelement
US10700256B2 (en) 2012-03-08 2020-06-30 D-Wave Systems Inc. Systems and methods for fabrication of superconducting integrated circuits
US11856871B2 (en) 2018-11-13 2023-12-26 D-Wave Systems Inc. Quantum processors
US11957065B2 (en) 2017-02-01 2024-04-09 1372934 B.C. Ltd. Systems and methods for fabrication of superconducting integrated circuits

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6221612B1 (en) 1997-08-01 2001-04-24 Aurora Biosciences Corporation Photon reducing agents for use in fluorescence assays
KR20040007862A (ko) * 2002-07-11 2004-01-28 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성 방법
KR100764054B1 (ko) * 2006-08-22 2007-10-08 삼성전자주식회사 금속배선 및 그 형성 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5284804A (en) * 1991-12-31 1994-02-08 Texas Instruments Incorporated Global planarization process
US5292393A (en) * 1986-12-19 1994-03-08 Applied Materials, Inc. Multichamber integrated process system
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits
US5478780A (en) * 1990-03-30 1995-12-26 Siemens Aktiengesellschaft Method and apparatus for producing conductive layers or structures for VLSI circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292393A (en) * 1986-12-19 1994-03-08 Applied Materials, Inc. Multichamber integrated process system
US5478780A (en) * 1990-03-30 1995-12-26 Siemens Aktiengesellschaft Method and apparatus for producing conductive layers or structures for VLSI circuits
US5284804A (en) * 1991-12-31 1994-02-08 Texas Instruments Incorporated Global planarization process
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10064041B4 (de) * 1999-12-22 2009-09-10 Hyundai Electronics Industries Co., Ltd., Ichon Verfahren zur Herstellung einer Kupferverdrahtung in einem Halbleiterbauelement
EP1611599A2 (fr) * 2003-03-14 2006-01-04 Lam Research Corporation Systeme, procede et appareil de planarisation locale amelioree par dual-damascene (methode de realisation d'interconnexions multi-niveaux avec de fortes densites)
EP1611599A4 (fr) * 2003-03-14 2007-06-13 Lam Res Corp Systeme, procede et appareil de planarisation locale amelioree par dual-damascene (methode de realisation d'interconnexions multi-niveaux avec de fortes densites)
WO2005076348A1 (fr) * 2004-01-30 2005-08-18 Lam Research Corporation Systeme et procede de reduction, passivation, prevention de corrosion et activation de surface en cuivre
WO2008064491A1 (fr) * 2006-12-01 2008-06-05 D-Wave Systems, Inc. Blindage superconducteur pour circuit intégré utilisé en informatique quantique
US7687938B2 (en) 2006-12-01 2010-03-30 D-Wave Systems Inc. Superconducting shielding for use with an integrated circuit for quantum computing
US8247799B2 (en) 2006-12-01 2012-08-21 D-Wave Systems Inc. Superconducting shielding for use with an integrated circuit for quantum computing
US10700256B2 (en) 2012-03-08 2020-06-30 D-Wave Systems Inc. Systems and methods for fabrication of superconducting integrated circuits
US11930721B2 (en) 2012-03-08 2024-03-12 1372934 B.C. Ltd. Systems and methods for fabrication of superconducting integrated circuits
US11957065B2 (en) 2017-02-01 2024-04-09 1372934 B.C. Ltd. Systems and methods for fabrication of superconducting integrated circuits
US11856871B2 (en) 2018-11-13 2023-12-26 D-Wave Systems Inc. Quantum processors

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TW426983B (en) 2001-03-21
EP1018149A1 (fr) 2000-07-12
JP2001516970A (ja) 2001-10-02

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