WO1999012212A3 - Lone-electron circuit arrangement, operating mode, and application for adding binary numbers - Google Patents
Lone-electron circuit arrangement, operating mode, and application for adding binary numbers Download PDFInfo
- Publication number
- WO1999012212A3 WO1999012212A3 PCT/DE1998/002521 DE9802521W WO9912212A3 WO 1999012212 A3 WO1999012212 A3 WO 1999012212A3 DE 9802521 W DE9802521 W DE 9802521W WO 9912212 A3 WO9912212 A3 WO 9912212A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- lone
- circuit arrangement
- binary numbers
- application
- operating mode
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4828—Negative resistance devices, e.g. tunnel diodes, gunn effect devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/84—Manufacture, treatment, or detection of nanostructure
- Y10S977/89—Deposition of materials, e.g. coating, cvd, or ald
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/937—Single electron transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/94—Specified use of nanostructure for electronic or optoelectronic application in a logic circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98952513A EP1010205B1 (en) | 1997-09-01 | 1998-08-26 | Lone-electron circuit arrangement, operating mode, and application for adding binary numbers |
KR1020007002150A KR20010023504A (en) | 1997-09-01 | 1998-08-26 | Lone--electron circuit arrangement, operating mode, and application for adding binary numbers |
DE59813900T DE59813900D1 (en) | 1997-09-01 | 1998-08-26 | CIRCUIT ARRANGEMENT WITH SINGLE ELECTRON COMPONENTS, METHOD FOR THE OPERATION AND USE OF THE METHOD FOR ADDING BINARY NUMBERS |
JP2000509120A JP2001515289A (en) | 1997-09-01 | 1998-08-26 | Circuit device having an isolated electronic component, method of driving the circuit device, and method of using a method of adding a binary number |
US09/516,658 US6307422B1 (en) | 1997-09-01 | 2000-03-01 | Circuit configuration having single-electron components, a method for its operation and use of the method for addition of binary numbers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19738115A DE19738115C1 (en) | 1997-09-01 | 1997-09-01 | Circuit arrangement with single-electron components, method for their operation and application of the method for adding binary numbers |
DE19738115.4 | 1997-09-01 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/516,658 Continuation US6307422B1 (en) | 1997-09-01 | 2000-03-01 | Circuit configuration having single-electron components, a method for its operation and use of the method for addition of binary numbers |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1999012212A2 WO1999012212A2 (en) | 1999-03-11 |
WO1999012212A3 true WO1999012212A3 (en) | 1999-06-03 |
Family
ID=7840827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1998/002521 WO1999012212A2 (en) | 1997-09-01 | 1998-08-26 | Lone-electron circuit arrangement, operating mode, and application for adding binary numbers |
Country Status (6)
Country | Link |
---|---|
US (1) | US6307422B1 (en) |
EP (1) | EP1010205B1 (en) |
JP (1) | JP2001515289A (en) |
KR (1) | KR20010023504A (en) |
DE (2) | DE19738115C1 (en) |
WO (1) | WO1999012212A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6724512B2 (en) | 1999-11-03 | 2004-04-20 | Optodot Corporation | Optical switch device |
US6583916B2 (en) | 1999-11-03 | 2003-06-24 | Optodot Corporation | Optical shutter assembly |
JP4049988B2 (en) * | 2000-11-24 | 2008-02-20 | 株式会社東芝 | Logic circuit |
KR100605696B1 (en) * | 2001-04-30 | 2006-08-01 | 주식회사 포스코 | A Submerged Nozzle For Continuous Casting |
US6777911B2 (en) * | 2002-03-07 | 2004-08-17 | The Regents Of The University Of Michigan | Charge transformer and method of implementation |
US7288970B2 (en) * | 2004-06-18 | 2007-10-30 | Nantero, Inc. | Integrated nanotube and field effect switching device |
KR20160137148A (en) * | 2015-05-22 | 2016-11-30 | 에스케이하이닉스 주식회사 | Electronic device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9206812D0 (en) * | 1992-03-25 | 1992-05-13 | Hitachi Europ Ltd | Logic device |
US5677637A (en) * | 1992-03-25 | 1997-10-14 | Hitachi, Ltd. | Logic device using single electron coulomb blockade techniques |
DE4212220C3 (en) * | 1992-04-09 | 2000-05-04 | Guenter Schmid | Use of an arrangement of cluster molecules as a microelectronic component |
US5646559A (en) * | 1994-03-15 | 1997-07-08 | Kabushiki Kaisha Toshiba | Single-electron tunnelling logic device |
US5838021A (en) * | 1995-12-26 | 1998-11-17 | Ancona; Mario G. | Single electron digital circuits |
DE69629275T2 (en) * | 1996-04-16 | 2004-06-03 | Hitachi Europe Ltd., Maidenhead | Logical device according to a binary decision diagram |
-
1997
- 1997-09-01 DE DE19738115A patent/DE19738115C1/en not_active Expired - Fee Related
-
1998
- 1998-08-26 DE DE59813900T patent/DE59813900D1/en not_active Expired - Fee Related
- 1998-08-26 JP JP2000509120A patent/JP2001515289A/en active Pending
- 1998-08-26 WO PCT/DE1998/002521 patent/WO1999012212A2/en active IP Right Grant
- 1998-08-26 EP EP98952513A patent/EP1010205B1/en not_active Expired - Lifetime
- 1998-08-26 KR KR1020007002150A patent/KR20010023504A/en active IP Right Grant
-
2000
- 2000-03-01 US US09/516,658 patent/US6307422B1/en not_active Expired - Fee Related
Non-Patent Citations (4)
Title |
---|
BENJAMIN S C ET AL: "A possible nanometer-scale computing device based on an adding cellular automaton", APPLIED PHYSICS LETTERS, 28 APRIL 1997, AIP, USA, vol. 70, no. 17, ISSN 0003-6951, pages 2321 - 2323, XP002098350 * |
IWAMURA H ET AL: "SINGLE-ELECTRON MAJORITY LOGIC CIRCUITS", IEICE TRANSACTIONS ON ELECTRONICS, vol. E81-C, no. 1, January 1998 (1998-01-01), pages 42 - 48, XP000767487 * |
NOMOTO T ET AL: "Single electron-photon logic device using coupled quantum dots: computation with the Fock ground state", JOURNAL OF APPLIED PHYSICS, 1 JAN. 1996, AIP, USA, vol. 79, no. 1, ISSN 0021-8979, pages 291 - 300, XP002098352 * |
T. MOK ET AL.: "A CHARGE-TRANSFER-DEVICE LOGIC CELL", SOLID STATE ELECTRONICS., vol. 17, no. 11, November 1974 (1974-11-01), OXFORD GB, pages 1147 - 1154, XP002098351 * |
Also Published As
Publication number | Publication date |
---|---|
KR20010023504A (en) | 2001-03-26 |
DE59813900D1 (en) | 2007-03-22 |
JP2001515289A (en) | 2001-09-18 |
EP1010205B1 (en) | 2007-02-07 |
US6307422B1 (en) | 2001-10-23 |
DE19738115C1 (en) | 1999-03-18 |
WO1999012212A2 (en) | 1999-03-11 |
EP1010205A2 (en) | 2000-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960008848A (en) | Semiconductor Memory and High Voltage Switching Circuit | |
DE69525517T2 (en) | Output control circuit with selectable, limited high voltage output | |
DE69819278D1 (en) | Integrated semiconductor circuit with logic gate with three operating states | |
ATE349731T1 (en) | DIFFERENTIAL CURRENT SOURCE WITH ACTIVE COMMON REDUCTION | |
TW331041B (en) | Semiconductor memory device | |
WO1999012212A3 (en) | Lone-electron circuit arrangement, operating mode, and application for adding binary numbers | |
TW359887B (en) | IC interline protective circuit | |
DK0753239T3 (en) | Impedance Buffer MOS Circuit with Dynamically Reduced Threshold Voltage, as Used in an Output Buffer for a Hearing | |
KR960038997A (en) | Current Sense Amplifier Circuit of Semiconductor Memory Device | |
KR910007277A (en) | Level conversion circuit | |
JPH0346268A (en) | Cmos type input buffer circuit of semiconductor device | |
KR890013769A (en) | Medium Potential Generation Circuit | |
TW326598B (en) | Output circuit | |
KR960015586A (en) | Memory Cell Circuits Independently Controlled in Write and Read | |
KR910014942A (en) | Output circuit | |
WO2003075611A3 (en) | A circuit, apparatus and method having a cross-coupled load with current mirrors | |
KR910016008A (en) | Low Power Redundancy Circuit for Memory Devices | |
KR970076821A (en) | Latch circuit | |
KR890013655A (en) | Integrated memory circuit | |
KR100268948B1 (en) | Transmission gate circuit | |
WO1997009785A3 (en) | Logic circuits | |
WO2001089089A3 (en) | Bi-directional current source | |
TW377444B (en) | Control gate driver circuit for a non-volatile memory and memory using same | |
JPH01154620A (en) | Semiconductor integrated circuit | |
TW348310B (en) | Semiconductor integrated circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1998952513 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020007002150 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 09516658 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 1998952513 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1020007002150 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1020007002150 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1998952513 Country of ref document: EP |