WO1999004496A1 - Convertisseur analogique/numerique a approximations successives ameliore - Google Patents

Convertisseur analogique/numerique a approximations successives ameliore Download PDF

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Publication number
WO1999004496A1
WO1999004496A1 PCT/US1998/014635 US9814635W WO9904496A1 WO 1999004496 A1 WO1999004496 A1 WO 1999004496A1 US 9814635 W US9814635 W US 9814635W WO 9904496 A1 WO9904496 A1 WO 9904496A1
Authority
WO
WIPO (PCT)
Prior art keywords
value
analog input
digital
input signal
time interval
Prior art date
Application number
PCT/US1998/014635
Other languages
English (en)
Inventor
Russell E. Cooper
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Priority to EP98935670A priority Critical patent/EP0932936A1/fr
Publication of WO1999004496A1 publication Critical patent/WO1999004496A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Definitions

  • the present invention relates generally to analog-to-digital (A/D)
  • A/D conversion constitutes any of many available methods
  • representations of the quantities of interest may be processed by a computer, or
  • the A/D converter 10 consists of three basic components, namely,
  • DAC digital-to-analog converter
  • SAR successive approximation register
  • the comparator 16 compares the output of the DAC 12, which is
  • comparator 16 operate in a closed loop system to determine the digital (binary)
  • an analog voltage of +7.2 volts lies within a range of interest between 0
  • the SAR system divides the valid range (0 to 16 volts) in half, and
  • the comparator output indicates to the SAR that the current binary value
  • analog input voltage can be found is between 4 volts and 8 volts.
  • That digital value is provided as the output of the successive approximation A/D
  • V ⁇ N is wavering because of system noise, jitter, or the like.
  • the comparator may fluctuate between a high and a low output, which is
  • a more specific objective of the invention is to provide an improved
  • the analog input voltage is
  • the SAR is implemented with additional latches and shift register stages to accommodate the
  • the majority detect approach can be limited to only those
  • V m at just slightly more than one-half of V DD (e.g., 2
  • range is selected with an upper limit to encompass the digital value of the analog input
  • the upper limit of the reference range is compared to the magnitude of the
  • the reference range is successively
  • analog input signal over the selected time interval is acquired by rapidly sampling the
  • analog input signal an odd number of times over the predetermined time interval
  • the odd number is at least three.
  • A/D conversion of a variable analog input signal includes
  • n+1 is the number of significant bits in the conversion
  • the comparator to provide the odd number of binary values as the respective values of
  • the SAR includes
  • the successive approximation A/D converter of the invention may also be used as a first and second input signal.
  • the SAR being adapted to adjust the reference range based on a succession of the binary inputs to more closely encompass the
  • the samples are supplied to provide an odd number of binary inputs of at least
  • Logic means coupled to the SAR detects or determines the majority binary
  • the SAR has an effective
  • Another aim of the invention is to improve the repeatability
  • FIG. 1 is a block diagram of a prior art successive approximation A/D
  • FIG. 2 is a signal diagram of analog input signals to a comparator of the
  • FIG. 3 is a sampling and A/D conversion diagram illustrating the
  • FIG. 4 is a block diagram of a preferred embodiment of the SAR portion
  • analog input signal V ]N of FIG. 2 is sampled at a high rate
  • FIG. 3 they produce outputs of 1, 0, 1, 1, and 0, respectively. The majority of these
  • plurality of individual register stages includes individual latches and shift register to
  • the high sampling rate takes into account changes in a rapidly varying analog input
  • sampling may be performed in advance of application to
  • FIG. 4 three bits constituting the result of compared values of three samples that
  • logic circuit 27 which determines binary value of the majority, or a consensus value
  • the contents of the first three stages of SAR 25 are detected by logic 27 as a majority binary value of 1, which
  • the SAR had been taken as the DAC bit value, as in a conventional arrangement, it
  • Each bit determined in that manner may be captured in a latch (not shown).
  • multiple stage shift register and majority detect logic may be and preferably is used by
  • the present invention is a 12-bit system with very high resolution, 10 volts by 4096
  • a battery charge level monitor oftentimes
  • fuel gauge referred to as a "fuel gauge,” must be sufficiently accurate at these levels to assure that

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un dispositif et un procédé pour la conversion analogique-numérique par approximations successives, qui permet de convertir sous forme numérique une tension analogique d'entrée variable par échantillonnage périodique. On utilise à cet effet un comparateur pour comparer les valeurs relatives de l'amplitude de tension analogique d'entrée variable dans un intervalle de temps prédéterminé et la limite supérieure d'une gamme de tensions de référence ajustée successivement jusqu'à s'approcher étroitement de la valeur numérique de la tension analogique d'entrée échantillonnée durant l'intervalle de temps considéré. L'ajustement successif est effectué via un registre par approximations successives ayant un nombre impair d'étages multiples (au moins trois) pour chaque bit numérique significatif représentant la limite supérieure de la gamme de tensions de référence à utiliser dans la comparaison. On affine la précision et la fiabilité de cette limite supérieure en prenant comme valeur pour chaque bit significatif la valeur de majorité correspondante dans les étages multiples. Après un certain nombre de comparaisons visant à fixer la valeur de majorité de chaque bit significatif, on obtient une succession de bits significatifs qui devient la conversion numérique de la tension analogique d'entrée dans l'intervalle de temps considéré.
PCT/US1998/014635 1997-07-18 1998-07-16 Convertisseur analogique/numerique a approximations successives ameliore WO1999004496A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98935670A EP0932936A1 (fr) 1997-07-18 1998-07-16 Convertisseur analogique/numerique a approximations successives ameliore

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US89646097A 1997-07-18 1997-07-18
US08/896,460 1997-07-18

Publications (1)

Publication Number Publication Date
WO1999004496A1 true WO1999004496A1 (fr) 1999-01-28

Family

ID=25406250

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/014635 WO1999004496A1 (fr) 1997-07-18 1998-07-16 Convertisseur analogique/numerique a approximations successives ameliore

Country Status (3)

Country Link
EP (1) EP0932936A1 (fr)
TW (1) TW425772B (fr)
WO (1) WO1999004496A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008032694A1 (fr) * 2006-09-13 2008-03-20 Advantest Corporation Convertisseur analogique-numérique et procédé de conversion analogique-numérique
WO2008149259A3 (fr) * 2007-06-06 2009-01-29 Nxp Bv Circuit convertisseur analogique-numérique par approximations successives
US7605738B2 (en) 2006-09-13 2009-10-20 Advantest Corporation A-D converter and A-D convert method
US8896476B2 (en) 2013-01-25 2014-11-25 Technische Universiteit Eindhoven Data-driven noise reduction technique for analog to digital converters

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0406973A1 (fr) * 1989-07-07 1991-01-09 Koninklijke Philips Electronics N.V. Convertisseur analogique-numérique
JPH0786946A (ja) * 1993-09-13 1995-03-31 Nec Corp 逐次比較型ａ／ｄ変換器
JPH08107354A (ja) * 1994-10-04 1996-04-23 Kawasaki Steel Corp パイプライン式逐次比較型ａ／ｄ変換器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0406973A1 (fr) * 1989-07-07 1991-01-09 Koninklijke Philips Electronics N.V. Convertisseur analogique-numérique
JPH0786946A (ja) * 1993-09-13 1995-03-31 Nec Corp 逐次比較型ａ／ｄ変換器
JPH08107354A (ja) * 1994-10-04 1996-04-23 Kawasaki Steel Corp パイプライン式逐次比較型ａ／ｄ変換器

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DATABASE WPI Section EI Week 9522, Derwent World Patents Index; Class U21, AN 95-165727, XP002082495 *
PATENT ABSTRACTS OF JAPAN vol. 095, no. 006 31 July 1995 (1995-07-31) *
PATENT ABSTRACTS OF JAPAN vol. 096, no. 008 30 August 1996 (1996-08-30) *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008032694A1 (fr) * 2006-09-13 2008-03-20 Advantest Corporation Convertisseur analogique-numérique et procédé de conversion analogique-numérique
US7477177B2 (en) 2006-09-13 2009-01-13 Advantest Corporation A-D converter, A-D convert method, and A-D convert program
US7479914B2 (en) 2006-09-13 2009-01-20 Advantest Corporation A-D converter and A-D convert method
US7605738B2 (en) 2006-09-13 2009-10-20 Advantest Corporation A-D converter and A-D convert method
WO2008149259A3 (fr) * 2007-06-06 2009-01-29 Nxp Bv Circuit convertisseur analogique-numérique par approximations successives
US7973693B2 (en) 2007-06-06 2011-07-05 Nxp B.V. Circuit with a successive approximation analog to digital converter
US8896476B2 (en) 2013-01-25 2014-11-25 Technische Universiteit Eindhoven Data-driven noise reduction technique for analog to digital converters

Also Published As

Publication number Publication date
EP0932936A1 (fr) 1999-08-04
TW425772B (en) 2001-03-11

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