WO1998054632A2 - Dispositif et procede pour le traitement de plaquette a semiconducteur avec elimination des defauts - Google Patents

Dispositif et procede pour le traitement de plaquette a semiconducteur avec elimination des defauts Download PDF

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Publication number
WO1998054632A2
WO1998054632A2 PCT/US1998/010658 US9810658W WO9854632A2 WO 1998054632 A2 WO1998054632 A2 WO 1998054632A2 US 9810658 W US9810658 W US 9810658W WO 9854632 A2 WO9854632 A2 WO 9854632A2
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defects
wafer
wafers
station
stubborn
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PCT/US1998/010658
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WO1998054632A3 (fr
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Paul P. Castrucci
Kenneth Baldwin
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Castrucci Paul P
Kenneth Baldwin
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Priority to AU75977/98A priority Critical patent/AU7597798A/en
Publication of WO1998054632A2 publication Critical patent/WO1998054632A2/fr
Publication of WO1998054632A3 publication Critical patent/WO1998054632A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices

Definitions

  • This invention relates to manufacturing methods and apparatus. More particularly, the invention relates to manufacturing methods and apparatus for defect eradication on semiconductor wafers and the like.
  • Surface contaminant defects include discrete pieces of matter that range in size from submicron dimension to granules visible to observation with the eye. Such contaminants may be fine dust, dirt particles, or unwanted molecules comprised of elements such as carbon, hydrogen, and/or oxygen. Particulate contaminants
  • Particulates frequently adhere to a surface by weak covalent bonds, electrostatic forces, van der Waals forces, hydrogen bonding, coulombic forces, or dipole-dipole interactions, making removal of the particulates difficult.
  • Particulates frequently encountered in practice include polysilicon slivers, photoresist particles, metal oxide particles, metal particles, and slurry residue. It is known that not all particulates are equally undesirable. For example, particulates that adhere at some non-sensitive portions of the IC circuitry may have no effect on operation or performance, and need not necessarily be removed (“don't cares"). On the other hand, particulates that adhere at critical locations (“killer defects”) can cause failure of the IC circuitry and must be removed for proper operation.
  • the presence of surface contaminants renders the contaminated substrate less efficient or inoperable for the substrate's designated purpose.
  • surface defects due to minor molecular contaminants often render semiconductor masks or chips worthless.
  • Tables 1 and 2 above reducing the number of molecular surface defects on a semiconductor wafer by even a small amount can radically improve semiconductor chip test yields.
  • removing molecular surface contaminants, such as carbon or oxygen, from the surface of silicon wafer circuit layers as deposited on the wafer or between deposition of layers significantly improves the quality of the IC chip produced.
  • Annealing treatment methods suffer similar drawbacks.
  • the treatment surface of the substrate being cleaned is heated to a temperature that is generally below the melting point of the material being treated but high enough to enable rearrangement of the material's crystal structure.
  • the surface being treated is held at this elevated temperature for an extended period during which time the surface molecular structure is rearranged and contaminants are removed by ultra high vacuum.
  • Annealing cleaning methods cannot be used where it is desired to preserve the integrity of the existing structure being cleaned.
  • ablation Another currently utilized cleaning method, known as ablation, suffers from its own particular drawbacks.
  • ablation a surface or contaminants on a surface are heated to the point of vaporization.
  • the material may melt before being vaporized, or the material may sublimate directly on heating.
  • ablation cleaning techniques if damage to the treatment surface is to be prevented, the ablation energy must be exactly aimed toward contaminants rather than toward the surface on which the contaminants lie, a difficult task when the contaminants are extremely small or randomly spaced. Even where the ablation energy can be successfully directed at a contaminant, it is difficult to vaporize the contaminant without also damaging the underlying treatment surface.
  • Surface cleaning by melting, annealing, and thermal ablation can be conducted with a laser energy source.
  • the laser annealing method disclosed requires both vacuum conditions and energy levels sufficient to cause rearrangement and melting of the treatment surface.
  • Other known laser surface cleaning methods involving melting or annealing require similar high energy lasing and or vacuum conditions, as disclosed in U.S. Pat. Nos. 4,181,538 and 4,680,616. The method of U.S.
  • Pat. No. 3,464,534 suffers the same drawbacks as other high energy laser thermal ablation methods.
  • the method of U.S. Pat. No. 4,980,536 to Asch et al. uses a high power density excimer laser pulse directed to both front and back sides of a mask to remove small particles.
  • the method of U.S. Pat. No. 4,987,286 to Allen uses an energy transfer medium interposed between each particle to be removed and the surface to which the particles are adhered.
  • the method of U.S. Pat. Nos. 5,283,417 and 5,393,957 to Misawa et al. uses two lasers, a pulsed laser and a trapping laser, to perform modification and processing of particles and microcapsules.
  • a first major object or purpose of the invention is a system for enhancing test yield in semiconductor manufacturing.
  • a second object is a set of methods that enables enhanced test yield in semiconductor manufacturing.
  • a related object is a system that integrates particularly effective cleaning methods into manufacturing tooling for achieving extremely low defect densities, especially for very small particulate defects that affect test yield of semiconductor products characterized by extremely fine minimum dimensions.
  • a further related object is a system that is capable of locating, identifying, and removing individual defects of various sizes, shapes, and compositions from wafer surfaces at various stages in the wafers' fabrication.
  • a still further related object is a system that is capable of individually locating, identifying, and removing those particular individual defects that are "killer" defects, i.e.
  • a more practical object is a system that incorporates cleaning apparatus and methods capable of area cleaning of wafers and also capable of local removal of individual particulates from wafers.
  • a more detailed object is a system including means for transferring semiconductor wafers among a number of processing stations under program control and for creating and maintaining a data record for each wafer indicating processing results at each processing station, also including means for performing a wafer surface cleaning of defects using a photon flux process followed by vapor cleansing, and also including means for transferring cleaned wafers to an output station.
  • Another detailed object is a method for processing wafers including the steps of transferring each wafer to a number of processing stations in a predetermined sequence starting at an input station and ending at an output station, creating and maintaining a data record at each of the stations, mapping and recording the locations of defects on each wafer, cleaning defects from each wafer using a photon flux process followed by vapor cleansing, and transfering the wafers to an output station.
  • An improved semiconductor wafer processing apparatus includes a series of processing stations, in one form, coupled together by computer-controlled cluster tooling which is programmed to achieve a selected wafer throughput for the apparatus at a selected defect level in the range of at least 0.01 defects/cm 2 .
  • Wafers are supplied in a pod to an input station which initiates a data record for recording wafer processing results at each processing station and transfers individual wafers to a precleaning station under control of the wafer handling equipment.
  • the pre-cleaning station performs a self-directed vacuum bake for each wafer after which the pod is transferred to a self-directed defect mapping station where wafer surface defects are identified and located in their x-y coordinates.
  • the defect-mapped wafers are transferred to a self-directed (i.e., computer-controlled) laser area cleaning station which lifts the defects and sweeps the wafer surface clean, except for stubborn defects. Clean wafers are transferred to a final mapping station where the wafer record is updated, followed by transfer of the wafers to an output station.
  • Wafers including stubborn defects are transferred to a second wafer defect mapping station where the stubborn defects are located in x-y coordinates, after which those wafers are transferred to a self-directed (i.e., computer-controlled) Defect Review Tool incorporating a Scanning Electron Microscope (SEM-DRT).
  • SEM-DRT Scanning Electron Microscope
  • An ultra high power wafer surface SEM image review of stubborn defects is performed including a chemical analysis (by energy-dispersive spectroscopy) of the stubborn defects, after which the wafers are routed to a self-directed (i.e., computer-controlled) laser point cleaning station which addresses each stubborn defect identified by x-y coordinates denoted in the data record accompanying the wafer.
  • the laser point cleaning station performs a defect removal operation by lifting and sweeping each stubborn defect from the wafer surface followed by transferring the cleaned wafers to a third wafer defect mapping station where any stubborn defects remaining are mapped in x-y coordinates and recorded in the accompanying data record, after which these wafers are transferred to a second laser area cleaning station.
  • a final cleaning is performed at the second laser cleaning station followed by transfer of the wafers to a final mapping station for location in x-y coordinates of any remaining stubborn defects.
  • the accompanying data records for the wafers are updated. Finally, the wafers are transferred to the output station.
  • Figure 1 is a plan view of manufacturing apparatus incorporating the principles of the present invention of defect eradication on semiconductor wafers.
  • Figure 2 is a flow chart illustrating the steps of a manufacturing method performed in accordance with the invention.
  • Figure 3 is a plan view of a simplified manufacturing apparatus incorporating the principles of the present invention.
  • Figure 4 is a plan view of another simplified manufacturing apparatus incorporating the principles of the present invention.
  • Figure 5 is a graph illustrating a conventional S-shaped yield learning curve commonly occurring in semiconductor fabrication.
  • the invention employs a process (hereafter "Radiance Process”), described in U.S. Pat. No. 5,024,968 to Engelsberg et al., which is based upon the principles of quantum physics rather than chemistry for wafer cleaning purposes. Related methods are described in U.S. Pat. Nos. 5,099,557, 5,531,857, and 5,643,472 to Engelsberg et al. The entire disclosures of U.S. Pat. Nos. 5,024,968, 5,099,557, 5,531,857, and 5,643,472 are incorporated herein by reference. As used in the present invention, the Radiance Process comprises of two components:
  • a photon flux is applied to the surface to be cleaned. This is usually from a deep ultraviolet excimer laser, but Nd:YAG or CO 2 lasers are sometimes suitable.
  • the light source and energy and power fluxes are determined by the combination of surface and contaminant.
  • the photon flux provides sufficient energy to break the bonds holding contaminants to a surface.
  • the contaminants must be removed from the work area. This is accomplished by the use of a flowing gas, usually in a laminar regime to provide a stable boimdary layer.
  • the gas usually nitrogen or argon, must be chosen so as to obviate reactions between it and the surface, noting the photocatalytic effect of some forms of photon flux.
  • the gas may have a role in the process of ejecting the contaminants once they are free of the surface.
  • the process may be applied to a variety of surface configurations ranging from flat surfaces to irregular broken crystals.
  • Processing speed is largely determined by the choice of a particular light source.
  • Process optimization involves tradeoffs of speed, cost, tool size, tool components and operator involvement. There appears to be a range of processing parameters which can produce the desired cleaning for most applications.
  • test yields at which a transition is made between the three indicated regimes are somewhat arbitrary and may vary with the particular semiconductor product and/or fabrication process.
  • the dividing line between regimes I and II may vary from about 5% test yield to about 30% test yield, for example, with similar variations for the transition from regime II to regime III.
  • Figure 1 shows a generic defect eradicator system 10, nicknamed MIDAS or YES (Yield Enhancement System), that utilizes laser cleaning technology and wafer defect mapping technology/tooling/SEM defect revenue tooling and a cluster tooling main frame architecture.
  • the system elements include the following: area laser cleaner station 11, 12 and laser point cleaner station 13, which may be apparatus manufactured by Radiance Services Company, Bethesda, Maryland; wafer mappers 18 - 22, which may be apparatus manufactured by KLA, 160 San Roblas, San Jose, California; Scanning Electron
  • Microscope - Defect Review Tool (SEM-DRT) 24, which may be apparatus manufactured by Amray, 160 Middlesex Turnpike, Bedford, Massachusetts; and computer-controlled cluster tooling 26 for wafer handling purposes including input and output ports 28, 30 respectively, which may be apparatus manufactured by Applied Materials, 350 Bowers Avenue, Santa Clara, California.
  • the cluster tooling may include a wafer pre-clean station 34.
  • Laser cleaner stations utilize the Radiance Processes described in the U.S. Pat. Nos. 5,024,968, 5,099,557, 5,531,857, and 5,643,472. Curved arrows in FIGS 1, 3, and 4 show schematically the movement of wafers from station to station.
  • the wafer yield enhancement/improvement system described in the following description will eradicate in-line IC defects and thereby increase IC yields and dramatically increase the individual wafer revenue potential by using the following process in the overall apparatus 10.
  • Most of the stations of FIGS. 1, 3, and 4 operate with gas atmospheres such as clean air.
  • some of the stations e.g., wafer pre-clean station 34 and SEM-DRT 24
  • the overall process comprises the steps shown schematically in FIG. 2. Specific steps are denoted by reference numerals SI ... SI 2. Wafers coming to the system in a pod of wafers (not shown) are processed in the following manner: (1) Wafer pod loaded (SI) at input station 28. (2) Optionally, wafers are processed (S2) one by one at a pre-clean station 34 (vacuum bake station).
  • SI Wafer pod loaded
  • pre-clean station 34 vacuum bake station
  • Wafers are moved to a wafer mapper station 14. Wafers are mapped (S3) for defects and their x-y positions (positional coordinates).
  • Wafers are illuminated one-by-one by an excimer laser and are swept clean (S4) with nitrogen gas in a laser area cleaning station 11.
  • Wavers now are subject to optionally being directed to
  • the wafers are then routed to the Laser-Point Clean station 13. Individual defect locations are addressed and the laser is directed to each x/y location to point clean each individual defect (S8).
  • the wafers are then mapped (Sll) at station 20 and outputted (S12) at output station 30, where the wafers are extremely clean compared with incoming wafers (pre-Midas) and will exhibit dramatically increased wafer yields.
  • the wafer cleaning apparatus of area laser cleaner station 11, 12 and laser point cleaner station 13, and the cleaning methods employed may be similar to those described in U.S. Pat. Nos. 5,024,968, 5,099,557, 5,531,857, and 5,643,472 (each incorporated by reference).
  • the specific apparatus details are shown in the descriptions and drawings of those patents and are not repeated in FIGS. 1 - 5 of the present application. Similar methods are also described in the articles by A. Engelsberg, "Particle Removal from Semiconductor Surfaces Using a Photon-Assisted, Gas-Phase Cleaning Process," Materials Research Society Symposium Proceedings, vol. 315, pp. 255-260, (1993) and "Laser-Assisted Cleaning Proves Promising" Precision Cleaning, May 1995.
  • An assembly holds a substrate (e.g., semiconductor wafer) from which surface particulate defects are to be removed.
  • a gas from a gas source is constantly flowed over the wafer.
  • the gas is inert to the wafer and is flowed across the wafer so as to bathe the wafer in a non-reactive gas environment.
  • the gas is a chemically inert gas such as helium, nitrogen or argon.
  • An enclosure for holding the wafer communicates with a gas source through a series of tubes, valves, and a gas flow meter.
  • the enclosure preferably comprises a stainless steel reaction cell fitted with opposing gas inlet and outlet ports.
  • the enclosure is fitted with a sealed optical grade quartz window or light guide (e.g., a suitable fiber-optic light guide) through which the radiation can pass, or the laser could be placed within the enclosure.
  • the inlet and outlet ports may comprise, for example, stainless steel tubing fitted with valves.
  • valves are preferably metering valves, regulating valves, or bellows valves suitable for high temperature and pressure applications and for use with toxic, hazardous, corrosive or expensive gases or liquids, as for example Swagelok SS-4H sup TM series valves by Swagelok Co. of Solon, Oh.
  • Each wafer is irradiated with high-energy irradiation characterized by an energy density and duration between that required to release surface contaminants from the substrate treatment surface and that required to alter the crystal structure of the substrate treatment surface.
  • a laser generates laser irradiation which is directed against the wafer surface.
  • the energy flux and the wavelength of the high-energy irradiation is preferably selected to be dependent upon the surface defects being removed.
  • a gas analyzer may be connected to area laser cleaner station 11, 12 and laser point cleaner station 13. The gas analyzer analyzes the contents of exhaust gas from the enclosure to facilitate selective energy and wavelength adjustment of the laser.
  • the gas analyzer may be a mass spectrometer as, for example, a quadrapole mass spectrometer manufactured by Bruker Instruments, Inc. of Billerica, Mass. or by Perkin Elmer of Eden Prairie, Minn. Selection of the high-energy irradiation source for use in the invention depends upon the desired irradiation energy and wavelength.
  • the electron volt/photon (eV/photon) of the irradiation is preferably at least twice the energy necessary to break the bonds adhering the particulate contaminants to the surface being cleaned.
  • the bond energies between common contaminants such as particulates composed of compounds of carbon, hydrogen and oxygen, and common substrate materials such as silicon, titanium, germanium, iron, platinum and aluminum range between 2 and 7 eV/bond as disclosed in Handbook of Chemistry and Physics, 68th ed., pp. F-169 to F-177 (CRC Press 1987) which is hereby incorporated by reference. Accordingly, lasers emitting photons with energies in the range of 4 to 14 eV/photons are desirable.
  • the wavelength should be below the wavelength that would compromise the integrity of the substrate surface by the photoelectric effect, as described in G. W. Castellan, Physical Chemistry, 2nd ed., 458-459 (Academic Press, 1975) which is hereby incorporated by reference.
  • the preferred wavelength depends on the molecular species being removed and the resonance states of such species.
  • the wavelengths and photon energies of a number of lasers operable in the invention are listed in Table 1 of U.S. Pat. Nos. 5,024,968 and 5,531,857, and Table lc of U.S. Pat. No. 5,643,472. A number of those lasers are described in greater detail in the following references which are hereby incorporated by reference: M. J. Webber, ed., CRC Handbook of Laser Science, Vols. 1-5 (1982-1987); Mitsuo Maeda, Laser Dyes, (Academic Press 1984); and laser product literature from Lambda Physik at 289 Great Road, Acton, Mass. Coherent, Inc.
  • irradiation energy density and duration of irradiation used is such that the heat of formation is not approached on the wafer surface. Finding the maximum energy usable on a given wafer material will require some experimentation in light of the material's known heat of formation. Thus, annealing, thermal ablation, and melting are prevented from occurring.
  • a suitable trapping system may be connected to apparatus 10 (preferably at laser area clean stations 11 and 12 and laser pin-point clean station 13) for trapping and neutralizing removed contaminant species.
  • the wafers being treated may be selectively exposed to the laser irradiation by a variety of methods.
  • the wafer may be fixed on an X-Y table which is selectively moved with respect to a fixed beam of laser pulses that are directed through a beam splitter and a focusing lens before contacting selected portions of the surface of the wafer over which inert gas flows.
  • laser pulses may be split by beam splitters into two sets of pulses which are selectively moved by adjusting mirrors over the surface of the wafer on a fixed table.
  • a laser power meter allows for close monitoring of the laser power being applied to the wafers.
  • the photons are preferably directed perpendicular to the plane of the portion of the wafer being treated, to maximize the power and energy fluxes at the surface for a given output from the source of photons.
  • the photons may be directed at an angle to the wafer as convenient or necessary for implementation of the process. In some situations, it may be preferable to direct the radiation at an oblique angle to the wafer.
  • the energy and power fluxes at the surface will vary with the angle of incidence of the photons with respect to the plane of the surface, and this variation must be taken into account in selecting the output of the photon source.
  • Figure 1 shows an integrated system that incorporates all four tool elements. However, the four system elements may also be separated into individual "tools.” Wafers would then be transported between the individual Midas Tool elements by using a mini- environment pod.
  • Simplified configuration versions of the integrated system are shown in Figures 3 and 4.
  • Figure 3 is a plan view of a simplified "mid-range” manufacturing apparatus for use in the intermediate (rapid yield-improvement) stage of a typical semiconductor manufacturing process yield-improvement curve.
  • Figure 4 is a plan view of a further simplified "low-end” manufacturing apparatus for use in the latest (high yield) stage of a typical semiconductor manufacturing process yield-improvement curve.
  • one important aspect of the invention is an improved semiconductor wafer processing apparatus that includes a series of processing stations, in one form, coupled together by computer-controlled cluster tooling which is programmed to achieve a selected wafer throughput for the apparatus at a selected defect level in the range of at least 0.01 defects/cm .
  • Wafers are supplied in a pod to an input station which initiates a data record for recording wafer processing results at each processing station.
  • the individual wafers are transferred to a self-directed defect mapping station where wafer surface defects are identified and located in their x-y coordinates.
  • the defect mapped wafers are transferred to a self-directed laser area cleaning station which lifts the defects and sweeps the wafer surface clean, except for stubborn defects.
  • Clean wafers are transferred to a final mapping station where the wafer record is updated, followed by transfer of the wafers to an output station. Wafers including stubborn defects are transferred to a second wafer defect mapping station where the stubborn defects are located in x-y coordinates, after which the wafers are transferred to a self-directed Defect
  • SEM-DRT Scanning Electron Microscope
  • the laser point cleaning station performs a defect removal operation by lifting and sweeping each stubborn defect from the wafer surface followed by transferring the cleaned wafers to a third wafer defect mapping station where any stubborn defects remaining are mapped in x-y coordinates and recorded in the accompanying data record, after which the wafers are transferred to a second laser area cleaning station wafer.
  • a final cleaning is performed at the second laser area cleaning station followed by transfer of the wafers to a final mapping station for location in x-y coordinates of any remaining stubborn defects.
  • the accompanying data records for the wafers are updated followed by transfer of the wafers to the output station. As mentioned above, it is known that not all particulates are equally undesirable.
  • particulates that adhere at some non-sensitive portions of the IC circuitry may have no effect on operation or performance, and need not necessarily be removed- ("don't cares" or "cosmetic" defects).
  • defects having innocuous physical and/or chemical characteristics may be cosmetic defects.
  • particulates that adhere at locations where they would be critical to device operation (“killer defects”) can cause test failure of the IC circuitry and must be removed for proper operation.
  • Each mapped defect may optionally be further characterized by automatic defect classification, as its physical and chemical characteristics may be pertinent to whether the defect is a killer defect.
  • the present invention is adaptable for selective removal of only killer defects. The positional coordinates of mapped defects are compared (by computer software) with device design data for identifying the killer defects critical to device operation, and the photon flux is then selectively applied only at the positional coordinates of the killer defects while ignoring other defects.
  • the following example illustrates the potential dramatic wafer revenue increase for a system on a chip (SOC) IC product with an average sale price (ASP) of $1,000.
  • SOC system on a chip
  • ASP average sale price
  • the SOC product is assumed to have 0.18 micron minimum feature size and 30 mask levels, 22 of them non-critical with 0.25 micrometer minimum feature size, and 8 of them critical with 0.18 micrometer minimum feature size.
  • the total number of 800 mm SOC chips per wafer is 70.
  • the apparatus and methods of the present invention reducing the defect level to 0.008 defects/cm 2 and thus improving the test yield by 3% from 70% to 73%, the added revenue is estimated at $2,000 per wafer. For 25,000 wafer starts per month per fabrication facility, the total added revenue produced by one fabrication facility would be $600 million per year.
  • a manufacturing apparatus made in accordance with the invention is applicable to manufacturing processes that require extremely low defect densities, especially semiconductor wafer and photomask fabrication processes.
  • the methods of the invention can be used to reduce defect densities of semiconductor wafers, thus increasing the yields and lowering the costs of the semiconductor products on the wafers.
  • Similar apparatus suitably arranged can be used in the manufacture of masks, such as glass or quartz photolithography masks or membrane masks used for photolithography, X-ray lithography, electron projection lithography, or ion-projection lithography.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

L'invention concerne un dispositif amélioré pour le traitement de plaquette à semiconducteur (10), comprenant une série de postes de traitement combinés sous forme unique et reliés par un système informatisé d'outillage multipostes qui permet d'atteindre un niveau de défaut déterminé de l'ordre de 0,01 défaut/cm2 ou moins. Les plaquettes sont fournies dans une structure boîtier à un poste d'entrée (28) qui établit un fichier de données pour l'enregistrement des résultats du traitement au niveau de chaque poste. Les plaquettes individuelles sont transférées vers un poste informatisé de relevé de défaut (14) pour l'identification des défauts et l'enregistrement des coordonnées de position de ces défauts. Les plaquettes sur lesquelles on relève des défauts sont transférées vers un poste informatisé de nettoyage de zone au laser (11) qui extrait les défauts et nettoie la surface de plaquette, en laissant les défauts difficiles à éliminer. Les plaquettes nettoyées sont transférées vers un poste de relevé final (20 ou 22), puis vers un poste de sortie (30). Les plaquettes sur lesquelles subsistent des défauts difficiles à éliminer sont transférées vers un second poste de relevé de défaut (16) pour le relevé des coordonnées de ces défauts, puis à un poste d'examen de défaut comprenant un microscope électronique à balayage (SEM-DRT) (24). L'examen par image de type SEM appliqué aux défauts difficiles à éliminer inclut l'analyse chimique de ces défauts. Un poste de nettoyage ponctuel au laser (13) extrait et élimine individuellement de la surface de la plaquette chaque défaut difficile à éliminer. Les plaquettes nettoyées sont transférées vers un troisième poste de relevé de défaut (18) pour l'enregistrement de tout défaut difficile à éliminer qui subsiste, puis vers un second poste de nettoyage de zone au laser (12) pour un nettoyage final, et les plaquettes sont ensuite transférées vers un poste de relevé final (20 ou 22) pour le relevé de tout défaut difficile à éliminer qui subsiste. Les fichiers de données associés sont actualisés, puis les plaquettes son transférées à un poste de sortie (30).
PCT/US1998/010658 1997-05-29 1998-05-26 Dispositif et procede pour le traitement de plaquette a semiconducteur avec elimination des defauts WO1998054632A2 (fr)

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AU75977/98A AU7597798A (en) 1997-05-29 1998-05-26 Semiconductor wafer processing apparatus and method with defect eradication

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US4790797P 1997-05-29 1997-05-29
US60/047,907 1997-05-29

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EP1061358A2 (fr) * 1999-06-15 2000-12-20 Applied Materials, Inc. Appareil et procédé de réexamen des défauts sur un object
GB2351160A (en) * 1999-05-20 2000-12-20 Nec Corp Lot supply system for a production line
WO2001080289A1 (fr) * 2000-04-13 2001-10-25 Nanophotonics Ag Systeme de mesure de substrat modulaire
EP1152906A1 (fr) * 1998-12-24 2001-11-14 Oramir Semiconductor Equipment Ltd. Enlevement vectoriel local de particules
US6418355B1 (en) 1999-05-20 2002-07-09 Nec Corporation Lot supply system and lot supply method
WO2003063233A2 (fr) * 2002-01-16 2003-07-31 Kla-Tencor Technologies Corp. Systemes et procedes destines a une reduction de defauts en boucle fermee
US6614050B1 (en) 1999-10-26 2003-09-02 Fab Solutions, Inc. Semiconductor manufacturing apparatus
US6842659B2 (en) 2001-08-24 2005-01-11 Applied Materials Inc. Method and apparatus for providing intra-tool monitoring and control
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EP2365512A3 (fr) * 2000-06-27 2012-01-04 Ebara Corporation Appareil d'inspection par faisceau de particules chargées
CN103962347A (zh) * 2013-01-24 2014-08-06 北京京东方光电科技有限公司 一种清洁系统和方法

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1152906A1 (fr) * 1998-12-24 2001-11-14 Oramir Semiconductor Equipment Ltd. Enlevement vectoriel local de particules
EP1152906A4 (fr) * 1998-12-24 2007-10-17 Oramir Semiconductor Ltd Enlevement vectoriel local de particules
US6418355B1 (en) 1999-05-20 2002-07-09 Nec Corporation Lot supply system and lot supply method
GB2351160A (en) * 1999-05-20 2000-12-20 Nec Corp Lot supply system for a production line
EP1061358A2 (fr) * 1999-06-15 2000-12-20 Applied Materials, Inc. Appareil et procédé de réexamen des défauts sur un object
US6614050B1 (en) 1999-10-26 2003-09-02 Fab Solutions, Inc. Semiconductor manufacturing apparatus
WO2001080289A1 (fr) * 2000-04-13 2001-10-25 Nanophotonics Ag Systeme de mesure de substrat modulaire
US7030401B2 (en) 2000-04-13 2006-04-18 Nanophotonics Ag Modular substrate measurement system
EP2365512A3 (fr) * 2000-06-27 2012-01-04 Ebara Corporation Appareil d'inspection par faisceau de particules chargées
US8368031B2 (en) 2000-06-27 2013-02-05 Ebara Corporation Inspection system by charged particle beam and method of manufacturing devices using the system
US9368314B2 (en) 2000-06-27 2016-06-14 Ebara Corporation Inspection system by charged particle beam and method of manufacturing devices using the system
US6842659B2 (en) 2001-08-24 2005-01-11 Applied Materials Inc. Method and apparatus for providing intra-tool monitoring and control
US7074626B2 (en) 2001-08-24 2006-07-11 Applied Materials, Inc. Method and apparatus for providing intra-tool monitoring and control
WO2003063233A3 (fr) * 2002-01-16 2004-03-25 Kla Tencor Tech Corp Systemes et procedes destines a une reduction de defauts en boucle fermee
US7236847B2 (en) 2002-01-16 2007-06-26 Kla-Tencor Technologies Corp. Systems and methods for closed loop defect reduction
WO2003063233A2 (fr) * 2002-01-16 2003-07-31 Kla-Tencor Technologies Corp. Systemes et procedes destines a une reduction de defauts en boucle fermee
CN103962347A (zh) * 2013-01-24 2014-08-06 北京京东方光电科技有限公司 一种清洁系统和方法

Also Published As

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AU7597798A (en) 1998-12-30
WO1998054632A3 (fr) 1999-03-11

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