WO1998051071A2 - Procede de generation de source de courant et de tension de seuil et appareil pour circuit video de type hhk - Google Patents

Procede de generation de source de courant et de tension de seuil et appareil pour circuit video de type hhk Download PDF

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Publication number
WO1998051071A2
WO1998051071A2 PCT/US1998/008869 US9808869W WO9851071A2 WO 1998051071 A2 WO1998051071 A2 WO 1998051071A2 US 9808869 W US9808869 W US 9808869W WO 9851071 A2 WO9851071 A2 WO 9851071A2
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WO
WIPO (PCT)
Prior art keywords
current
output
signal
level
threshold voltage
Prior art date
Application number
PCT/US1998/008869
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English (en)
Other versions
WO1998051071A3 (fr
Inventor
Mehrdad Nayebi
Duc Ngo
Original Assignee
Sony Electronics Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/848,387 external-priority patent/US6018370A/en
Priority claimed from US08/853,046 external-priority patent/US6028640A/en
Application filed by Sony Electronics Inc. filed Critical Sony Electronics Inc.
Priority to AU72762/98A priority Critical patent/AU7276298A/en
Publication of WO1998051071A2 publication Critical patent/WO1998051071A2/fr
Publication of WO1998051071A3 publication Critical patent/WO1998051071A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • the present invention relates to the field of separating synchronization pulses from a composite video signal. More particularly, the present invention relates to the field of generating a timing current and threshold voltage for an equalization pulse removal circuit.
  • a composite video signal contains information which is used by a video system to generate a video picture on a display, monitor or television.
  • Each period, within the horizontal portion of a composite video signal contains information representing one horizontal output line which is to be output on the video display, monitor or television.
  • Each horizontal period includes a horizontal synchronization pulse, a burst signal and a video information signal.
  • color or chrominance information is represented by a particular phase of the chrominance subcarrier signal that is amplitude modulated with color information.
  • the horizontal synchronization pulse is used by a phase locked loop to synchronize the system for displaying the next horizontal line of video information.
  • the burst signal is used to synchronize the phase of the sampling pulses with the phase of the color subcarrier signal.
  • the burst signal consists of a sinusoid with a frequency equal to 3.58 MHz, which is the frequency of the chrominance subcarrier f sc .
  • the video information signal then comprises the chrominance subcarrier having different phases amplitude-modulated with chrominance information.
  • the composite color video signal includes both luminance and chrominance information.
  • a video picture or frame is made up of a number of horizontal lines included within the video display.
  • the video system begins at the top of the screen and displays the information within the composite video signal one horizontal line at a time.
  • the information for each horizontal line is contained within a horizontal period of the composite video signal.
  • the video system moves to the next line and displays the information within the next horizontal period of the composite video system. This process continues until the video system reaches the bottom line on the video display.
  • a conventional video system After displaying the video information on the bottom line of the video display, a conventional video system resets itself to the top of the display in order to begin displaying the next frame.
  • a vertical blanking period is included within the composite video signal after the video information for each frame. This vertical blanking period allows the video system sufficient time to reset to the top of the video display and begin displaying the information for the horizontal lines of the next frame. Therefore, a number of horizontal periods, enough to comprise a frame or screen, are strung together, within the composite video signal.
  • the composite video signal includes a vertical blanking period between each frame which allows the video system to perform a vertical reset and prepare to display the next frame by moving back up to the top of the video display.
  • the composite video signal includes a first period of equalizing pulses, a period of serration pulses and a second period of equalizing pulses.
  • the video system resets itself to the top of the video display so that it is ready to begin displaying the information for the next frame.
  • the video system must be notified of or be able to detect the vertical blanking period so that it can reset itself to the top of the video display.
  • the serration pulses carry synchronization information used by the local vertical oscillator, within the video system, during a vertical reset.
  • the horizontal synchronizing pulses and the vertical synchronizing pulses are combined together into a composite synchronizing signal CSYNC.
  • a device receiving this composite synchronizing signal then extracts the horizontal synchronizing pulses and the vertical synchronizing pulses from the composite signal.
  • the equalizing and serration pulses are all generated during the vertical blanking period at a frequency equal to twice the frequency of the horizontal synchronizing pulses.
  • a sync separator circuit 10 is used to separate all of the synchronization pulses from the composite video signal including the horizontal, equalizing and serration pulses.
  • the sync separator circuit separates the synchronization pulses by comparing their amplitude with respect to the blank level of the signal and therefore has no way of differentiating between horizontal synchronization pulses, equalizing pulses and serration pulses.
  • the output of the sync separator circuit is used by a horizontal phase-locked loop to lock the video system in phase with the composite video signal during the horizontal period of each frame.
  • the sync separator circuit is configured to output the equalizing and serration pulses which are generated at twice the frequency of the horizontal synchronization pulses.
  • twice as many synchronization pulses are generated during the vertical blanking period as during the horizontal period.
  • the horizontal phase-locked loop will therefore be unable to remain locked during this period unless something is done to alter the frequency of synchronization pulses during the vertical blanking period.
  • HHK circuits use precision timing signals from voltage ramps to provide a mask for the equalizing pulses.
  • Such circuits are typically referred to as Half H Killer (HHK) circuits because the extra pulses which are removed are included halfway between adjacent horizontal synchronization pulses.
  • the voltage ramp signals used by HHK circuits are generated by storing charge on a capacitor. Typically, the period of these ramps is relatively long, up to 64 microseconds. Accordingly, either an extremely small current or a very large capacitor are required to efficiently support a period of that length. When an extremely small current is used, small base current variations in the transistors cause large percentage differences in the small reference current, affecting the precise timing nature of the ramp circuit.
  • External components are conventionally used to generate the necessary current and threshold voltage signals because they may be selected for high absolute accuracy.
  • a current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal.
  • the current is generated through a current generation circuit, using a ratio of matched devices.
  • the matched devices are transistors.
  • the current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal.
  • the current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device.
  • the charge storage device is a capacitor and the timing circuit is an HHK video circuit.
  • the preferred embodiment of the current source and threshold voltage generation circuit is implemented within an integrated circuit and does not require any external components.
  • Figure 1 illustrates a block diagram of a sync separator circuit for separating synchronization pulses from the composite video signal.
  • Figure 2 illustrates a block diagram schematic of a circuit to remove every other equalizing pulse during the vertical blanking period.
  • Figure 3a illustrates a timing diagram of a composite video signal.
  • Figure 3b illustrates a timing diagram of an output of the sync separator circuit illustrated in Figure 1.
  • Figure 3 c illustrates a timing diagram of a voltage signal V c which represents a voltage level stored across a capacitor Cl.
  • Figure 3d illustrates a timing diagram of an output V Comp of a comparator 20.
  • Figure 3e illustrates a timing diagram of a signal B which represents an output Q of an
  • Figure 3f illustrates a timing diagram of an output signal C of the circuit of the present invention.
  • Figure 4 illustrates a schematic diagram of a current source and threshold voltage generation circuit according to the present invention.
  • Figure 5 illustrates a detailed schematic diagram of the current source and threshold voltage generation circuit according to the present invention.
  • FIG. 2 A block diagram schematic of one example of a circuit for removing every other equalizing pulse during the vertical blanking period is illustrated in Figure 2. This circuit is described in detail in co-pending U.S Patent Application Serial Number 08/583,972. entitled “Method of and Apparatus For Removing Equalizing Pulses Without Using External Pins.” which is hereby incorporated by reference. This circuit generates an output signal C representing every horizontal synchronization pulse and every other vertical synchronization pulse within the composite video signal.
  • the output signal C is provided as a feedback control and coupled to the first terminal of a resistor Rl within the circuit of Figure 2.
  • the second terminal of the resistor Rl is coupled to the base of an npn transistor Ql .
  • the emitter of the transistor Ql is coupled to ground.
  • the collector of the transistor Ql is coupled to the first terminal of a capacitor Cl, to the first terminal of a current source I 0 and to the positive input of a comparator 20, thereby forming a voltage node V Cap representative of the voltage level stored across the capacitor Cl .
  • the second terminal of the capacitor Cl is coupled to ground.
  • the second terminal of the current source I 0 is coupled to a supply voltage VCC.
  • the negative input of the comparator 20 is coupled to a threshold voltage signal V ⁇ .
  • An output signal V Comp of the comparator 20 is coupled as the set input S of an RS latch 24 and as the input to a logical NOR gate 22.
  • the output signal A from a sync separator circuit such as the sync separator circuit 10 illustrated in Figure 1 , is coupled as an input to a logical NOR gate 26.
  • the inverse signal A which is the inverse of the output signal A from the sync separator circuit 10 is coupled as an input to the logical NOR gate 22.
  • the output of the logical NOR gate 22 is coupled as the input R of the RS latch 24.
  • the output Q of the RS latch 24 provides a signal B.
  • the inverse output Q of the RS latch 24 is coupled as an input to the logical NOR gate 26.
  • the output of the logical NOR gate 26 provides the output signal C which is the output of the circuit to remove equalizing pulses during a vertical blanking period.
  • Timing diagrams of relevant signals within the circuits illustrated in Figures 1 and 2 are illustrated in Figure 3.
  • the composite video signal which is input to the sync separator circuit 10 is illustrated in Figure 3 a.
  • the signal A which is output from the sync separator in response to the composite video signal is illustrated in Figure 3b.
  • the voltage signal V Cap which represents the voltage level stored across the capacitor Cl is illustrated in Figure 3c.
  • the output signal V Comp of the comparator 20 is illustrated in Figure 3d.
  • the signal B which represents the output Q of the RS latch 24 is illustrated in Figure 3e.
  • the output signal C which represents the output of the circuit from which every other equalizing pulse is removed during the vertical blanking period is illustrated in Figure 3f.
  • the timing diagrams illustrated in Figure 3 are shown to correspond in time to each other.
  • the composite video signal illustrated in Figure 3 a includes two horizontal periods followed by five equalization pulses during a vertical blanking period at the end of a frame.
  • the output signal A from the sync separator circuit illustrated in Figure 3 b represents only the synchronization pulses from the composite video signal.
  • the output signal A and the inverse signal A are then input to the circuit to remove equalizing pulses during a vertical blanking period, illustrated in Figure 2.
  • the outputs of the logical NOR gates 22 and 26 are at a logical low voltage level when either of their inputs are at a logical high voltage level.
  • the outputs of the logical NOR gates 22 and 26 are at a logical high voltage level only when both of their inputs are at a logical low voltage level.
  • the output signal A On the rising edge of the output signal A, when the output signal A transitions from a logical low voltage level to a logical high voltage level, the output signal C will fall to a logical low voltage level, turning off the transistor Ql.
  • the transistor Ql is turned off the capacitor Cl is charged by the current source I 0 .
  • the output signal V Comp of the comparator 20 When the voltage level V Cap stored across the capacitor Cl is greater than the level of the threshold voltage V ⁇ , the output signal V Comp of the comparator 20 will rise to a logical high voltage level.
  • the RS latch 24 When the output signal V Comp of the comparator 20 rises to a logical high voltage level, the RS latch 24 is set, causing the output Q to rise to a logical high voltage level and the inverse output Q to fall to a logical low voltage level. Because the inverse output Q is at a logical low voltage level, at the next falling edge of the output signal A from the sync separator 10, where the output signal A transitions from a logical high voltage level to a logical low voltage level, the output signal C will rise to a logical high voltage level.
  • the transistor Ql When the output signal C rises to a logical high voltage level, the transistor Ql is turned on and provides a discharge path for the capacitor Cl. Because the voltage level V c . , stored across the capacitor Cl, is discharged below a level equal to the level of the threshold voltage V ⁇ , the output signal V Comp of the comparator 20 transitions from a logical high voltage level to a logical low voltage level. Because the inverse output signal A is at a logical high voltage level the output of the logical NOR gate 22 remains at a logical low voltage level and the output Q of the RS latch 24 will remain at a logical high voltage level.
  • the inverse output Q of the RS latch 24 will correspondingly remain at a logical low voltage level, causing the output signal C to remain at a logical high voltage level until the output signal A from the sync separator circuit 10 rises to a logical high voltage level.
  • the output signal C transitions from a logical high voltage level to a logical low voltage level. Because the RS latch 24 was previously set and has not yet been reset, the output signal C will transition when the output signal A from the sync separator circuit 10 transitions. Thus, the width of the pulses of the output signal C is equal to the width of the synchronization pulses from the output signal A.
  • the transistor Ql When the output signal C falls to a logical low voltage level, the transistor Ql is turned off and causes the voltage level V Cnp stored across the capacitor Cl to begin charging up again.
  • the output V Comp of the comparator 20 When the voltage level V Cap stored across the capacitor Cl rises above the level of the threshold voltage V ⁇ , the output V Comp of the comparator 20 will rise to a logical high voltage level, again setting the RS latch 24. The output signal C will then rise to a logical high voltage level at the beginning of the next synchronization pulse from the output signal A and will fall to a logical low voltage level at the end of the next synchronization pulse.
  • the values of the capacitor Cl and the current source I 0 have been chosen such that during the horizontal period, the voltage level V Cap stored across the capacitor Cl will reach the level of the threshold voltage V ⁇ before every horizontal synchronization pulse and set the RS latch so that the output signal C will transition at the beginning of the next pulse.
  • the RS latch 24 will not be set and the output signal C will not transition during that next pulse.
  • the voltage level V Cap stored across the capacitor Cl will reach the level of the threshold voltage V ⁇ before the subsequent pulse, setting the RS latch 24 and allowing the output signal C to transition with the edges of that pulse.
  • the timing of the setting of the RS latch 24 is illustrated in Figure 3.
  • the time between two equalization pulses during a vertical blanking period is illustrated as the time period t2.
  • the values of the capacitor Cl and the current source I 0 have been chosen so that the time period tl is greater than the time period t2, but less than the time between two horizontal synchronization pulses. Therefore, as described above, during the vertical blanking period every other pulse is ignored by the circuit of Figure 2.
  • a current source and threshold voltage generation circuit is illustrated in Figure 4.
  • the current source and threshold voltage generation circuit generates a small current, using a ratio of devices, and a threshold voltage signal, which are utilized by an HHK circuit, as illustrated in Figure 2.
  • the small current is generated through a current generation circuit, using a ratio of matched devices. That current is then utilized by the HHK circuit, as the current provided from the current source I 0 , to charge the capacitor Cl, as described above.
  • the current is also mirrored and used to generate the threshold voltage which is compared to the voltage across the capacitor Cl .
  • any errors in the current are reflected in the threshold voltage and therefore cancel out and do not change the length of the time period for blocking equalization pulses. If an error causes less current to be supplied to the capacitor Cl, then the threshold voltage level is reduced by an appropriate amount. Correspondingly, if an error causes more current to be supplied to the capacitor Cl, then the threshold voltage level is increased by an appropriate amount.
  • a 1.2 V bandgap reference voltage signal is coupled to a positive input of an amplifier 40.
  • An output of the amplifier 40 is coupled to a base of an npn transistor 42 and to a base of an npn transistor 44.
  • a collector of the transistor 42 is coupled to the supply voltage VCC.
  • An emitter of the transistor 42 is coupled to a first terminal of a resistor 50.
  • An emitter of the transistor 44 is coupled to a first terminal of a resistor 52.
  • a second terminal of the resistor 52 is coupled to a first terminal of a resistor 54, to a second terminal of the resistor 50 and to a negative input of the amplifier 40.
  • a second terminal of the resistor 54 is coupled to ground.
  • a collector of the transistor 44 is coupled to a collector and base of a pnp transistor 46 and to a base of a pnp transistor 48.
  • An emitter of the transistor 46 is coupled to a first terminal of a resistor 56.
  • a second terminal of the resistor 56 is coupled to the supply voltage VCC.
  • An emitter of the transistor 48 is coupled to a first terminal of a resistor 58.
  • a second terminal of the resistor 58 is coupled to the supply voltage VCC.
  • a collector of the transistor 48 is coupled to a first terminal of a resistor 60.
  • a second terminal of the resistor 60 is coupled to a first terminal of a resistor 62, thereby forming an output node from which the threshold voltage signal is provided.
  • a second terminal of the resistor 62 is coupled to ground.
  • the amplifier 40 mirrors the 1.2 V bandgap reference level at the negative input and therefore at the first terminal of the resistor 54. Therefore, there is a 1.2 V voltage drop across the resistor 54.
  • the resistor In the preferred embodiment of the present invention, the resistor
  • the resistor 54 has a value equal to 52 K ohms. Preferably, a current equal to 23 microamps is generated through the resistor 54. This current is supplied through the split pair of transistors 42 and 44. Preferably, the transistor 44 has an emitter which is nine times bigger than the emitter of the transistor 42.
  • the emitter resistors 50 and 52 have also been chosen to approximate the ratios of the emitters of the transistors 42 and 44 based on the total value of the resistor 54.
  • the resistor 52 is not exactly one-tenth (1/10) and the resistor 50 is not exactly nine-tenths (9/10) of the value of the resistor 52, in order to compensate for base current losses within the system. Accordingly, one-tenth (1/10) of the current flowing through the resistor 54 is supplied through the transistor 42 and flows through the resistor 50. In the preferred embodiment of the present invention this current supplied through the transistor 42 is equal to 2.3 microamps. This current is then mirrored and used as the reference current supplied from the current source I 0 to charge the capacitor Cl within the timing ramp generation circuit, as described above.
  • the current supplied through the corresponding transistor 44 is used to generate the threshold voltage signal used by the timing ramp circuit and compared against the voltage stored on the capacitor Cl to trigger transitions of the output signal V c from the comparator 20. Accordingly, any errors in the current through the transistor 42 are reflected in the threshold voltage, thereby eliminating the potential for errors in the timing ramp signal generated by the circuit to remove equalizing pulses during a vertical blanking period. If the level of the current is reduced or increased by errors within the circuit, the threshold voltage level is correspondingly reduced or increased by an appropriate amount to compensate for those errors and maintain the correct timing period when the voltage across the capacitor Cl rises above the threshold voltage level.
  • the current flowing through the transistor 44 which represents a current which is nine times greater than the current supplied to the capacitor Cl, flows through the transistor 46 and is mirrored through the transistor 48. Because the size of the transistor 48 is three times greater than the size of the transistor 46, the current flowing through the transistor 48 is three times greater than the current flowing through the transistor 46.
  • the current flowing through the transistor 48 is then provided to a resistor ladder including the resistors 60 and 62.
  • the threshold voltage signal V ⁇ is provided from the output node between the resistors 60 and 62 and accordingly represents the voltage drop across the resistor 62.
  • the current which flows through the resistor 62 and which is used to generate the threshold voltage signal V ⁇ corresponds to the current supplied from the current source I 0 , which mirrors the current flowing through the transistor 42. Accordingly, any errors in the level of the current flowing through the transistor 42 are reflected in the current flowing through the transistor 48 and the resistor 62 and ultimately in the level of the threshold voltage signal V-, . Therefore, as the level of the current supplied from the current supply I 0 varies, the level of the threshold voltage signal V ⁇ will correspondingly vary by a proportionate amount, ensuring that the timing ramp generated by the voltage stored across the capacitor Cl will cross the threshold voltage level at the appropriate time interval, regardless of any errors within the current supplied from the current source I 0 .
  • the current and threshold voltage circuit of Figure 4 is preferably implemented within an integrated circuit and therefore does not require the use of any external precision components, thereby conserving space within the system.
  • a detailed circuit schematic of the preferred embodiment of the current source and threshold voltage circuit of the present invention is illustrated in Figure 5.
  • the preferred embodiment of the present invention is implemented within an analog video encoder circuit, Part No. CXA2015Q, which will be available from Sony Corporation of America, 3300 Zanker Road, San Jose, California 95134. While the preferred embodiment of the present invention has been illustrated and described as an integrated circuit using bipolar transistors, it will be apparent to a person of ordinary skill in the art that the circuit of the present invention may be implemented using another device technology, including but not limited to CMOS, MOS, discrete components and ECL. It will also be apparent to those skilled in the art that different logic circuit configurations could be substituted for the logic circuit described above to perform the functions of the preferred embodiment.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Manipulation Of Pulses (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

Selon cette invention, un circuit de génération de source de courant et de tension de seuil génère un courant, en passant par un rapport de dispositifs, ainsi qu'un signal correspondant de tension de seuil, destinés à être utilisés par un circuit de temporisation pour générer une rampe de temporisation et déterminer le moment auquel la rampe de temporisation croise le signal de tension de seuil. Le courant est généré au moyen d'un circuit de génération de courant, à l'aide d'un rapport de dispositifs appariés qui sont, de préférence, des transistors. Un circuit de temporisation utilise ensuite ledit courant pour charger un dispositif de stockage de charge à un niveau supérieur à celui du signal de tension de seuil. On procède également au miroitage du courant, qui est augmenté de manière appropriée et utilisé pour générer le signal de tension de seuil, comparé à la charge stockée dans le dispositif de stockage de charge. De ce fait, toute erreur de génération de courant est également réfléchie par le niveau du signal de tension de seuil, ce qui élimine le potentiel d'erreurs dans le signal de rampe de temporisation, généré par le circuit de temporisation. De préférence, le dispositif de stockage de charge (C1) est un condensateur, et le circuit de temporisation est un circuit vidéo de type HHK. Dans le mode de réalisation préféré, le circuit de génération de source de courant et de tension de seuil est réalisé à l'intérieur d'un circuit intégré et ne demande aucun composant extérieur.
PCT/US1998/008869 1997-05-08 1998-05-01 Procede de generation de source de courant et de tension de seuil et appareil pour circuit video de type hhk WO1998051071A2 (fr)

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Application Number Priority Date Filing Date Title
AU72762/98A AU7276298A (en) 1997-05-08 1998-05-01 Current source and threshold voltage generation method and apparatus for hhk video circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/848,387 US6018370A (en) 1997-05-08 1997-05-08 Current source and threshold voltage generation method and apparatus for HHK video circuit
US08/848,387 1997-05-08
US08/853,046 1997-05-08
US08/853,046 US6028640A (en) 1997-05-08 1997-05-08 Current source and threshold voltage generation method and apparatus for HHK video circuit

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WO1998051071A2 true WO1998051071A2 (fr) 1998-11-12
WO1998051071A3 WO1998051071A3 (fr) 1999-02-04

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AU7276298A (en) 1998-11-27
TW385611B (en) 2000-03-21
WO1998051071A3 (fr) 1999-02-04

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