TW385611B - Current source and threshold voltage generation method and apparatus for HHK video circuit - Google Patents

Abstract

A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is them utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit. Preferably, the charge storage device (C1) is a capacitor and the timing circuit is an HHK video circuit. The preferred embodiment of the current source and threshold voltage generation circuit is implemented within an integrated circuit and does not require any external components.

Description

A7 ________ B7 V. Description of the Invention (ii) M Field The present invention relates to the separation of synchronized pulses from a composite video signal. More specifically, the invention relates to the field of generating sequential currents and threshold voltages for an equalized pulse wave removal circuit. BACKGROUND OF THE INVENTION Composite video signals contain material used by video systems to produce video pictures on a display, monitor, or television screen. In the data contained in each cycle of the composite video signal, the horizontal portion represents a horizontal output line output to a video display, monitor, or television screen. Each horizontal period includes a horizontal sync pulse, a burst signal, and a video data signal. In many video transmission systems, color or chroma data is represented by a specific phase of the chroma subcarrier signal, which is tuned to the amplitude of the color data. The phase-locked loop uses horizontal synchronization pulses to synchronize with the system for displaying the next horizontal line of video data. The burst signal is used to synchronize the phase of the sampling pulse with the color subcarrier signal. A separator circuit separates the horizontal sync signal and the burst signal from the incoming video signal. The burst signal is composed of a sine wave with a frequency of 3.58 MHz, which is the frequency of the chrominance subcarrier f s c. Therefore, the video data signal includes a chrominance subcarrier, which has amplitude modulation with a phase different from that of the chrominance data. The composite color video signal includes luminance and chrominance data. A video image or picture is made up of many horizontal lines in a video display. To display a picture or image, the video system displays the data in the composite video signal from the top of the screen, one horizontal line at a time. Each -4- (please read the note f on the back before filling this page) This paper scale is applicable to China National Standard (CNS) A4 specification (2 丨 0 > < 297 mm) A7 ______________B7__ 5. Description of the invention &) (Please read the note f on the back before filling this page) The information of the horizontal lines is included in the horizontal period of the composite video signal. At the end of each horizontal period, the video system moves to the next line and displays the data in the next horizontal period of the composite video signal. This process continues until the video system reaches the bottom line of the video display. After displaying the video material of the bottom line of the video display, the traditional video system resets itself to the top of the display so that the next picture can be displayed. To allow the system to reset itself to the top of the video display, a vertical blank period needs to be included after the video data of each picture in the video signal is combined. This vertical blank period allows the video system sufficient time to reset to the top of the video display and start displaying horizontal line data for the next frame. Therefore, the number of horizontal periods sufficient to form a picture or screen is concatenated in the composite video signal. The composite video signal includes a vertical blank period between each frame. It allows the video system to perform a vertical reset and thereby shift Back to the top of the video display, ready to display the next picture. During the vertical blank period, the composite video signal includes an equalized pulse wave of the first period, a sawtooth pulse wave period, and an equalized pulse wave of the second period. During the vertical blanking period, the video system resets it to the top of the video display, so it is ready to start displaying data for the next frame. However, the video system must be informed or able to detect the period of vertical blanking in order to reset itself to the top of the video display. The sawtooth pulses carry synchronization data for use by the local vertical oscillator in the video system during vertical reset. The horizontal synchronization pulse and the vertical synchronization pulse are combined into a composite synchronization signal C S YN C. A device receives the composite synchronization signal and then applies the Chinese national standard (CNS > A4 specification (2 丨 0 · 〆297) 嫠) from the composite letter paper size. -5- A7 _B7___ V. Description of the invention (3) (Please Read the notes on the back first and then fill out this page) to extract the horizontal and vertical sync pulses. During the vertical blank period, all the equalized and sawtooth pulses are generated, with a frequency equal to twice the frequency of the horizontal sync pulses. The sync separation circuit 10 (shown in Figure 1) separates all sync pulses in the composite video signal, including horizontal, equalized, and sawtooth pulses. However, the practice of the sync separation circuit is to separate their amplitude from the signal blank level For comparison, it is impossible to distinguish the difference between the horizontal synchronous pulse, the equalized pulse, and the sawtooth pulse. During the horizontal period of each picture, the horizontal phase-locked loop uses the output of the synchronous separation circuit to lock the phase of the video system and the composite video signal. During the vertical blanking period, the synchronous separation circuit is framed to form an output equalization and sawtooth pulse, which has twice the frequency of the horizontal synchronous pulse. Therefore, in Synchronous pulses required during a straight blank period are twice that of a horizontal period. Therefore, during this period, the horizontal phase-locked loop cannot remain locked unless a synchronous pulse of a different frequency is generated during the vertical blank period in some way Traditional circuits use precise timing signals in voltage ramps to provide equalized pulse-shadowing. This type of circuit is typically called a Half H Killer (ΗΗΚ) circuit because it removes excess pulses In addition, the extra pulses in the vicinity of the horizontal synchronization pulse are included. The voltage ramp signal used by the ΗΗK circuit is generated by the charge stored in the capacitor. Typically, the period of these ramps is very long, usually as long as 64 milliseconds. Therefore, very small currents and very large capacitors are needed to effectively support such a long period. When very small currents are used, the small change in the base current in the transistor will result in a small reference current A large percentage difference, which affects the characteristics of the precise timing of the ramp circuit. "Traditionally, the external paper size is suitable for Λ1. National standard rate (CNS) Α4 Specification (210Χ297 mm) ~~ A7 _B7__ V. invention described Q) components to produce a desired threshold voltage and current signals, because they can be highly accurate absolute pick assembly. However, this type of external component is not what we want, because it will increase the cost of the system, occupy additional space on the motherboard on the system, and require additional dedicated pins on the integrated circuit to couple these external components. What meets my needs is a circuit that can generate an internal current source and a threshold voltage. Without external components, it has the ability to generate a small accurate current and a corresponding threshold voltage signal. The invention describes a current source and a threshold voltage generating circuit. A proportional device generates a current and a corresponding threshold voltage signal for a timing circuit to generate a timing ramp, and determines when the timing ramp crosses the threshold voltage signal. This current is generated by a current generating circuit using a ratio matching device, and the matching device is preferably an electric crystal type. This current is then used by the sequential circuit to charge the charge storage device to a level above the threshold voltage signal level. This current is also mirrored, moderately increased and used to generate a threshold voltage signal, and compared with the charge stored in the charge storage device. Therefore, any error caused by the current will be reflected in the threshold voltage signal level, thereby eliminating possible errors in the timing ramp signal generated by the sequential circuit. The charge storage device is preferably a capacitor, and the sequential circuit is preferably an HHK video circuit. The preferred embodiment of the current source and threshold voltage generating circuit is implemented in an integrated circuit and does not require any external components. Schematic description --------- Q ------- 1T ------ qi. R --f?:% (Please read the precautions on the back before filling this page) This & Zhang scale is applicable to the Chinese family standard ([chan) 6 4 specifications (2 丨 0 father 297 mm) ~ A7 B7 V. Description of the invention (5) Figure 1 illustrates the separation of the synchronous pulse wave from the composite video signal Block diagram of a synchronous separation circuit. Figure 2 illustrates a block diagram of a circuit design that removes every other equalizing pulse during a vertical blanking period. Fig. 3a illustrates a timing diagram of a composite video signal. Figure 3b illustrates the output timing diagram of the synchronous separation circuit in Figure 1. Figure 3c illustrates the timing diagram of the voltage signal ▽ (; 31), which represents the voltage level stored in the capacitor C1. "Figure 3d illustrates the timing diagram of the output of the comparator 20. * ·. Fig. 3e illustrates a timing diagram of the signal B representing the output Q- of the RS latch 24. Figure 3f illustrates a timing diagram of the output signal c of the circuit of the present invention. Fig. 4 illustrates a design diagram of a current source and a threshold voltage generating circuit according to the present invention. Figs. 5A and 5B illustrate a detailed design diagram of a current source and a threshold voltage generating circuit according to the present invention. (Please read the note § item on the back before filling this page) -Γ 装 • II 1 · ---- Order ---------. Jing Qi Department 眢 慧 材 4¾member 1.¾ tivn 咋It control components comparison table 10 Synchronous separation circuit 20 Comparator 24 RS latch 26 Logic NOR gate 22 Logic NOR gate 40 Amplifier 42 npn transistor 44 npn transistor This paper is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) _ 8-A7 B7 V. Description of the invention (6) 50 resistor 52 resistor 54 resistor 46 ρηρ transistor 48 ρηρ transistor 56 resistor 58 resistor 60 resistor 62 resistor (铕 先 闻Read the note f on the back and fill in this page again) The detailed description of the preferred embodiment: Figure 2 illustrates a block diagram of a circuit that removes every other equalizing pulse during the vertical blank period. This circuit is described in detail in commonly pending US Patent Application No. 08 / 583,972, entitled "Method of and Apparatus For Removing Equalizing Pulses Without Using External Pins", which is incorporated herein by reference. This circuit generates an output signal C, which represents each horizontal sync pulse and every other vertical sync pulse in the composite video signal. The output signal C provides feedback control and is coupled to a first terminal of a resistor R 1 in the circuit of FIG. 2. The second terminal of the resistor R 1 is coupled to the base of the η ρ η transistor Q 1. The emitter of transistor Q 1 is coupled to ground. The collector of transistor Q 1 is coupled to capacitor C 1 and current source I. And the positive input of comparator 20 to form a voltage node VCap, which represents the voltage level stored on capacitor C1. The first paper size of capacitor C1 applies the Chinese standard (CNS) ) A4 size (210X297 mm)

, 1T The central part of the potash department is printed by Ae Zuosha, only -9-A7 ___ _B7 _ 5. Description of the invention (7) The two terminals are coupled to the ground. Current source I. The second terminal is coupled to the supply voltage V C C. The negative input of the comparator 20 is coupled to a threshold voltage signal Vt. The output signal V < ^ mP of the comparator 20 is input to the S input terminal of the RS latch 24 and the input terminal of the NO'R logic gate 26. The output signal A from the synchronous separation circuit 10 is coupled to the input of the NOR logic gate 26. The reverse signal I is the reverse signal of the output signal A of the synchronous separation circuit 10 and is coupled to the input of the NOR logic gate 22. The output of the NOR logic gate 2 2 is coupled to the input R of the RS latch 24 = the output Q of the RS latch 24 provides a signal B. The inverted output 1 of the RS latch 24 is coupled to the input of the NOR logic gate 26. The output of the NOR logic gate 26 provides an output signal C, which is the output of a circuit that removes the equalizing pulses during the vertical blank period. The related signal timing diagrams of the circuits of FIG. 1 and FIG. 2 are illustrated in FIG. 3. The input composite video signal is shown in Figure 3a. The output of the composite video signal A from the synchronous separation circuit 10 is shown in Figure 3b. The voltage level Vcap stored on the representative capacitor C1 is shown in Fig. 3c. The output signal VhPm of the comparator 20 is shown in Figure 3d. The signal B representing the output Q of the RS latch 24 is shown at point 3e. Figure 3f represents the output signal C of the circuit that removes every other equalized pulse during the vertical blanking period. The timing chart illustrated in FIG. 3 corresponds to time. The composite video signal shown in Figure 3a consists of two horizontal periods, followed by five equalizing pulses during the vertical blank period at the end of the picture. The signal A (as shown in Figure 3b) output from the synchronous separation circuit represents only the synchronous pulse wave in the composite video signal. Next, the output signal A and the reverse signal T " are input to this paper. The size of the paper applies to the Chinese Standard for Standards (CNS) A4 (210 × 297 mm) --------- Γ: clothing ------ 1T- ----- es (Please read the notes on the back before filling in this page) -10- Decision in the Department of Economics and Technology ^ Icon and Consumer Cooperation ^ 卬 ^ A7 B7 V. Invention Description (8) Move to the circuit to move Except for the equalizing pulse wave during the vertical blank period, as shown in FIG. 0, when the inputs of the NOR logic gates 26 and 22 are at a high voltage logic level, their outputs are at a low voltage logic level. When the inputs of NOR logic gates 2 6 and 2 2 are at a low voltage logic level, their outputs are at a high voltage logic level. On the rising edge of the output signal A, when the output signal A is switched from a low voltage logic level to a high voltage logic level, the output signal C will fall to a low voltage logic level, and the transistor Q 1 is turned off. When closed, capacitor C 1 is powered by current source I. Charging. When the voltage level Vcap stored in the capacitor C1 is higher than the threshold voltage Vt, the output signal Vc0mP of the comparator 20 will rise to a high voltage logic level. When the output signal of the comparator 20 rises to the high-voltage logic level, the RS latch 24 is set so that the output Q rises to the high-voltage logic level and at the same time the inverting output i drops to the low-voltage logic level. Since the inverted output is at the low voltage logic level, at the next falling edge of the output signal of the synchronous separation circuit 10, its output signal A is switched from the high voltage logic level to the low voltage logic level. Signal C will rise to the logic high voltage level. When the output signal C rises to a high voltage logic level, the transistor Q 1 is turned on and provides a discharge path for the capacitor C 1. Since the voltage level VCap stored in the capacitor c 1 is discharged to a level lower than the threshold voltage VT, the output signal of the comparator 20 is switched from a high voltage logic level to a low voltage logic level. Since the inverted input signal X is at a high voltage logic level, the NOR logic gate 22 remains at a low voltage logic level, and the output Q of the RS latch 24 remains at a high voltage logic level. R S latch This paper is suitable for the standard of Chinese Standard (CNS) Α4 Washing (210 × 297 mm): 丨 ~: 1ο-I (Please read the precautions on the back before filling this page)

* 1T -11-Good central ministry " _ and κ-τ consumer cooperation women and children ^ A7 __ B7 V. Description of the invention (9)

The inverting output of 2 4 is still at the low voltage logic level, so that the output signal C remains at the high voltage logic level until the signal A output from the synchronous separation circuit 10 rises to the high voltage logic level. The signal A output from the synchronous separation circuit 10 rises to a high voltage logic level, and the output signal C switches from a high voltage logic level to a low voltage logic level. Since the RS latch 24 is set in advance and 尙 is not reset, when the signal A output from the synchronous separation circuit 10 is switched, the output signal C is also switched. Therefore, the width of the output signal C is equal to the width of the synchronous pulse wave of the output signal A. When the output signal C falls to a low voltage logic level, the transistor Q 1 is turned off, and the voltage level stored in the capacitor C 1 is recharged. When the voltage level V c a P stored in the capacitor C 1 rises above the level of the threshold voltage VT, the output signal Vc of the comparator 20. Pm will rise to the high voltage logic level, and the RS latch 2 4 will be set again. Then +, the output signal C will rise to the high-voltage logic level at the beginning of the next synchronization pulse of the output signal A, and will drop to the low-voltage logic level at the end of the next synchronization pulse. The capacitor C 1 and the current source I 0 are selected so that during the horizontal period, the voltage level Vcap stored in the capacitor C 1 will reach the threshold voltage Vt level before each horizontal synchronization pulse and set RS The latch is such that the output signal C switches at the beginning of the next pulse. However, 'During the vertical blank period, when the frequency of the sync pulse is twice that of the horizontal sync pulse, when capacitor C 1 starts to charge at the end of the pulse', the voltage level Vcap stored in capacitor C 1 is before the next pulse It will not reach the threshold. The paper size is applicable to the Central Countries Standards (CNS) Α4 grid (210 × 297 mm) --------- Q ------ 1T ------ 嫂, (Please read the precautions on the back before filling in this page) -12- Zhong Rong 浐 ^^ Cooperative shirt printed on the second consumer ^ A7 B7 — --———— --— 11 — " V. Invention Explain (10) the level of the voltage ντ. Therefore, the RS latch 24 will not be set, and the output signal C will not be switched during the next pulse period. However, the voltage level VcaP stored in the capacitor C1 will reach the threshold voltage Vt level before the subsequent pulse, set the RS latch 24 and allow the output signal C to switch with the edge of the pulse. Figure 3 illustrates the timing of the RS latch 24 setting. The time required for the voltage level stored in the capacitor C 1 to reach the threshold voltage VT from the fully discharged level is the time period t 1. The time between two equalizing pulses during the vertical blank period is time period t2. Capacitor C 1 and current source I.値 is selected so that time period t 1 is greater than time period t 2, but less than the time between two horizontal synchronization pulses. Therefore, as mentioned before, during the vertical blanking period, the circuit of FIG. 2 ignores every other pulse. The current source and threshold voltage generating circuit according to the present invention are shown in FIG. 4. The current source and threshold voltage generating circuit uses a proportional device to generate a small current and threshold voltage signal for HHK circuit use, as shown in Figure 2. The small current is generated by a current generating circuit using a ratio matching element. Current source I. The current provided is used by the HHK circuit to charge the capacitor C 1 as described previously. This current is also mapped and used to generate a threshold voltage, which is compared to the voltage on capacitor C1. Therefore, any errors in the current will be reflected in the threshold voltage and therefore cancel each other out without changing the length of the time period to block the equalizing pulse. If the error causes less current to be supplied to capacitor C1, the threshold voltage level will be reduced by an appropriate amount. Correspondingly, if the current supplied to capacitor C 1 is caused by mistake, the paper size is applicable to China National Standard (CNS) Α4 specification (210X297 mm): iQ—I (Please read the precautions on the back before filling in this purchase)

, 1T • 13- A7 —-_________ 5. The description of the invention (n) is too much, then the threshold voltage level will rise by an appropriate amount. In the generating circuit of Figure 4, the 1.2 volt band gap reference voltage signal is pro- Close to the positive input of amplifier 40. The output of amplifier 40 is coupled to the base of η ρ η transistor 42 and the base of η ρ transistor 4 4. The collector of transistor 42 is coupled to the supply voltage V C C. The emitter of the transistor 42 is coupled to the first end of the resistor 52. The emitter of transistor 4 4 is coupled to the first end of resistor 54, the second end of resistor 5 2, the first end of resistor 5 4, the second end of resistor 50, and the negative of amplifier 40. Input coupling. The second end of the resistor 54 is coupled to ground. Printed in the Ministry of Economic Affairs " '4, · ΛΡ-Τ · Private cooperation printing (please read the precautions on the back before filling this page) Transistor 4 The collector of 4 is coupled to ρ η ρ transistor 4 6 base and collector, and ρ η ρ transistor 4 8 base. The emitter of transistor 46 is coupled to the first end of resistor 56. The second terminal of the resistor 56 is coupled to the power supply voltage V C C. The emitter of the transistor 48 is coupled to the first end of the resistor 58. The second terminal of the resistor 58 is coupled to the power supply voltage V C C. The collector of transistor 48 is coupled to the first terminal of resistor 60. The second terminal of the resistor 60 is coupled to the first terminal of the resistor 62 to form an output node from which a threshold voltage signal is output. When the second end of resistor 62 is coupled to ground, the amplifier 40 maps the 1.2 volt band gap reference level to the negative input and the first end of resistor 54. Therefore, there is a voltage drop of 1.2 volts on the resistor 54. In the preferred embodiment of the present invention, 値 of the resistor 54 is equal to 5 2 K ohms. The current flowing through the resistor 54 is preferably equal to 23 microamperes. This current is supplied to the shunt transistor pairs 4 2 and 4 4. The emitter of transistor 44 is preferably 9 times larger than the emitter of transistor 42. The size of the paper is suitable for Chinese national standard (CNS) Α4 size (210X297mm) -14- Economic " .Ministry folder ^^-and only private consumption and cooperation cooperation private printing ^ A7 — _._ B7 _ Five 'invention Note (12) The pole resistors 50 and 52 are also selected, and according to the total resistance 値 of the resistor 54, it is close to the ratio of the emitters of the transistors 42 and 44. However, in the preferred embodiment of the present invention, In order to compensate for the base current loss in the system, the resistor 5 2 is not exactly 1/1 0, and the resistor 50 is not exactly 9/1 0 of the resistor 5 2 値. Therefore, the resistor flows through the resistor A current of 1 4/10 of 5 4 is supplied to the transistor 4 2 and flows through the resistor 50. In a preferred embodiment of the present invention, the current supplied to the transistor 4 2 is equal to 2.3 microamperes. Then this current is mapped And as the reference current supplied from the current source I, to charge the capacitor C 1 in the timing ramp generating circuit, as described above. To compensate for the low beta transistor in the amplifier 40 and the use of such a small current Any mismatch, the current supplied by the corresponding transistor 4 4 is used to generate a threshold voltage signal for the timing ramp And compare it with the voltage stored in capacitor C 1 to trigger the conversion of the output signal of comparator 20. Therefore, any error in the current flowing through transistor 42 will be reflected in the threshold voltage To eliminate potential errors in the timing ramp signal generated by the circuit in order to remove the equalizing pulse during the vertical blanking period. If the current level is lowered or increased due to errors in the circuit, the threshold voltage level is also relatively To reduce or raise an appropriate amount to compensate for these errors and maintain the correct timing cycle when the voltage across capacitor C 1 rises above the threshold voltage level. The current flowing through transistor 44 is supplied to the capacitor The current of c 1 is 9 times larger and flows through transistor 4 6 and is mapped through transistor 4 8. Since the volume of transistor 4 8 is 3 times that of transistor 4 6, it flows through the transistor (please read the back first) (Please fill in this page for the precautions) .C 裒 ·

、 1T This paper size applies to Chinese national standards (CNS > Α4 size (210X297mm) -15- Goods in the middle folder " • ^ • 而 工 消 Φ 合作 Cooperation deduction 卬 ^ A7 B7 V. Description of the invention (13 ) The current of 48 is three times that of the current flowing through the transistor 46. The current flowing through the transistor 4 8 is then provided to a resistor ladder including the resistors 60 and 62. The threshold voltage signal VT is transmitted from the resistor 60 and The node output between 6 and 2 therefore represents the voltage drop across resistor 62. The current flowing through resistor 62 is used to generate a threshold voltage signal Vt corresponding to the current source I, which maps The current flowing through transistor 42. Therefore, any error in the level of current flowing through transistor 42 will be reflected in the current flowing through transistor 48 and resistor 62, and finally reflected in the threshold voltage signal The level of Vt. Therefore, when the level of the current supplied by the current source I changes, the level of the threshold voltage signal 乂 1 is correspondingly changed by a proportional amount to ensure that the voltage The timing ramp can cross the threshold voltage level in the appropriate time interval, regardless of the electrical Source I. Are there any errors in the current supplied. The current and threshold voltage circuit of Figure 4 is better implemented in an integrated circuit, so there is no need to use any external precision components to save system space. This A detailed circuit design diagram of a preferred embodiment of the current source and threshold voltage circuit of the invention is shown in Figure 5. The preferred embodiment of the invention is implemented in an analog video decoder circuit, Part No. CXA2015Q, available from the United States Acquired by Sony Corporation, 3300 Zanker Road, San Jose, California 95134. Although the preferred embodiment of the present invention described above is an integrated circuit using a bipolar transistor, those skilled in the art will appreciate that the present invention also It can be implemented using its device technology, including but not limited to CMOS, MOS, separate components and ECL. It should also be understood that this paper size can be used in accordance with China National Standard (CNS) Α4 specification (210X297 mm) (please first (Read the notes on the back and fill out this page) Q.

1T -16- A7 B7 V. Description of the Invention (14) Other different logic circuit architectures replace the aforementioned logic circuits that perform the functions of the preferred embodiment. The present invention has been described in detail using specific embodiments in order to easily understand the operation and structural principles of the present invention. The specific embodiments and details referred to herein are not intended to limit the scope of the patents attached below. Obviously, the techniques selected in the embodiments can be modified without departing from the spirit and scope of the present invention. In particular, although the current source and voltage generating circuit of the preferred embodiment is included in the HHK circuit, this circuit can be used in any timing circuit. It should also be understood that the components of the components used in the preferred embodiments of the present invention may be changed or changed without departing from the spirit and scope of the present invention. (Please read the notes on the back before filling this page)

* 1T

A 浐 部 部 屮 irSKTM-T Elimination cooperation ii Printing and printing This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -17-

Claims (1)

Attachment No. 87 1 069 No. 14 Chinese Patent Application Amendment Chinese Republic Amendment September 1988 Amendment 1 · A current source that supplies output current, including: a) Current generation circuit for generating a first current: and b) The first current supply flows through many components, each of which has a corresponding size, wherein the proportion of the size of the components determines the electric-current flow through each component, and the output current generated therein corresponds to the current flowing through a given component Electric Γ current. 2. The current source according to item 1 of the scope of patent application, wherein the current generating circuit comprises a first resistor (54) and an amplifier (40) coupled to receive the first predetermined voltage signal, and the first resistor (54) Provides a voltage drop across. 3. The current source according to item 2 of the patent application scope, wherein the voltage across the first resistor (54) is 1% to the first predetermined voltage signal. 4 · The current source according to item 1 of the scope of patent application, many of which include a first current supply circuit that supplies a first predetermined portion of a first current, and a second current supply that supplies a second predetermined portion of a first current A circuit, wherein the ratio of the first current supply circuit to the second current supply circuit determines the first and second predetermined portions of the first current. 5. A current source according to item 4 of the patent application, wherein the output current generated corresponds to a first predetermined portion of the first current. This paper size is applicable to the national standard (CNSM4 specification (210 X 297 mm) (please read the note on the back before filling in this page)-ην Pack! — Order ·!-Employees' cooperation in the intellectual property bureau of the Ministry of Economic Affairs Du printed Attachment No. 87 1 069 No. 14 Chinese Patent Application Amendment Chinese Republic Amendment September 1988 Amendment 1 · A current source that supplies output current, including: a) Current generation circuit for generating a first current: and b) The first current supply flows through many components, each of which has a corresponding size, wherein the proportion of the size of the components determines the electric-current flow through each component, and the output current generated therein corresponds to the current flowing through a given component Electric Γ current. 2. The current source according to item 1 of the scope of patent application, wherein the current generating circuit comprises a first resistor (54) and an amplifier (40) coupled to receive the first predetermined voltage signal, and the first resistor (54) Provides a voltage drop across. 3. The current source according to item 2 of the patent application scope, wherein the voltage across the first resistor (54) is 1% to the first predetermined voltage signal. 4 · The current source according to item 1 of the scope of patent application, many of which include a first current supply circuit that supplies a first predetermined portion of a first current, and a second current supply that supplies a second predetermined portion of a first current A circuit, wherein the ratio of the first current supply circuit to the second current supply circuit determines the first and second predetermined portions of the first current. 5. A current source according to item 4 of the patent application, wherein the output current generated corresponds to a first predetermined portion of the first current. This paper size is applicable to the national standard (CNSM4 specification (210 X 297 mm) (please read the note on the back before filling in this page)-ην Pack! — Order ·!-Employees' cooperation in the intellectual property bureau of the Ministry of Economic Affairs Du printed 6. Scope of patent application (please read the notes on the back before filling out this page) 6. According to the current source of the scope of patent application, the first current supply circuit includes the first transistor (4 2) And the second current supply circuit includes a second transistor (4 4), and the relative size of the first transistor (4 2) and the second transistor (4 4) provides a ratio, and the first The first and second predetermined parts of a current. 7. The current source according to item 5 of the scope of patent application, wherein the current source is implemented in a integrated circuit without using any external components to provide output current. 8 kinds A method for generating an output signal representing each horizontal synchronous pulse wave in a composite video signal, including each vertical synchronous pulse wave, including the steps of: 'a) receiving a signal representing all synchronous pulses > waves in a composite video signal, Including horizontal and vertical synchronous pulses; b) generating an output signal representative of the synchronous pulses in the signal, the output signal having a first voltage logic level and a second voltage logic level; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs c) When the output signal is at the first voltage logic level, a current source is used to provide an output current by generating a first current flowing through the first element to raise the charge level stored in the storage unit, wherein the first current flows through the second The ratio of the element to the third element, the second to the third element determines the current 値 through the second and third elements, and the output current therein corresponds to the current through the second element; and d) f. The output signal rises to At the second voltage logic level, the charge stored in the storage unit is released to a single level. Only when the level of the charge exceeds a predetermined threshold level, a -2- is produced. 210 X 297 mm) A8 B8 C8 6. Scope of patent application The steps printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs have only begun, and the level of the charge has risen above a predetermined threshold level to initiate the steps including the representative level of each output signal Sync pulse and every other vertical straight pulse. 9. The method according to item 8 of the patent application, wherein the first current is generated by a predetermined voltage drop generated on the first element. 10. The method according to item 9 of the scope of patent application, wherein the first element is a * resistor. 1 1. The method according to item 10 of the scope of patent application, wherein the horizontal synchronization pulse wave has a first frequency, and the vertical synchronization pulse has a second frequency 〇2. The method according to item 11 of the patent application scope, wherein The second element includes a second transistor and the third element includes a third transistor. The relative size of the second transistor and the third transistor provides a ratio that determines the current flowing through the second and third elements. . 13.—A device for generating an output signal representing each horizontal synchronization f 'pulse wave and each \ Nth vertical synchronization pulse wave in a composite video signal, wherein the first time period exists between the horizontal synchronization pulse waves, and the second The time period exists between N vertical synchronization pulses. The device includes: a) a storage unit (C1) level for storing charge; b) a charge supply circuit coupled to the storage unit (C1) level for raising charge The charge supply circuit includes a current source (I.), which provides an output current by generating a first current flowing through the first element, wherein the supplied first current flows through the second and third elements, and the second and third elements. The ratio determines the current 値 flowing through the second and third components, and the output current corresponds to the ------------ 0¾ -------- order ----- ---- ^ (1 (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -3- A8B8C8D8 The current of the two components; (Please read the precautions on the back before filling this page) C) Monitoring circuit (2 0) To the storage unit (C 1) to determine when the level of charge exceeds a predetermined threshold level, wherein the charge supply circuit will raise the charge level to exceed the predetermined threshold level in a third time period: and d) the output generation circuit Coupling to a monitoring circuit to generate an output pulse wave signal representative of horizontal and vertical synchronous pulse waves, wherein the output pulse wave signal is generated only when the level of the charge exceeds a predetermined threshold level. 14. The device according to item 13 of the scope of patent application, whose f third time period is less than the first time period but greater than the second time period, so that the level of the charge rises above a predetermined threshold level to generate a value corresponding to The output pulse wave and signal of each horizontal sync pulse and every Nth vertical sync pulse in the composite video signal. J 1 5. The device according to item 14 of the scope of the patent application, wherein the first voltage is generated by a predetermined voltage drop generated on the first element. 16. The device according to item 15 of the scope of patent application, wherein the y »one element 瘥 resistor (54). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 17 · The device according to item 16 of the scope of patent application, in which the second element includes a second transistor (42), and the third element includes a third transistor (44), The relative size of the second transistor, the body (42) and the third transistor (44) provides a ratio, and thereby provides a current 値 through the second and third elements. 1 8. The device according to item 17 of the scope of patent application, wherein the first r current is generated by a current generating circuit, which includes the first element 'applies to the Chinese National Standard (CNS) A4 specification at -4- this paper standard (210 X 297 public love) A8B8C8D8 Duiyin Du, printed by the Intellectual Property Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs, applied for a patent scope, and coupled with an amplifier that receives a predetermined voltage signal, and provides a predetermined voltage drop on the first component. 19a The device according to item 18 of the scope of patent application, wherein the voltage drop corresponds to a predetermined voltage signal of the table. 2 0. According to the installation of item 19 in the scope of patent application, the storage unit (C 1) is a capacitor. ) 2 1. The device according to item 20 of the scope of patent application, wherein the length of the first time period is twice the length of the second time period. 2 2. The device according to item 21 of the scope of patent application, wherein the device is included in an integrated circuit, and the capacitor (C 1) is also included in the integrated circuit. 2 3. The device according to item 22 of the scope of the patent application, wherein the output pulse wave signal is used as a feedback signal to couple and control the charge supply circuit. 2 4. A current source that supplies current to the sequential circuit to generate charges across the storage unit, including: a ',) the first resistor (5 4); * b) the amplifier (4 0) coupled to receive A first predetermined voltage signal and providing a voltage drop across the first resistor (54) to generate a first current c) a first current supply circuit coupled to the first resistor (54) to supply a second current; and d) the second current supply circuit is coupled to the first resistor (54) to supply a third current, wherein the ratio of the second and third currents equal to the first current and the ratio of the first current supply circuit to the second current supply circuit Decide that the second paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -5 ----- Order --------- (Please read the Precautions to keep and write this page) A8B8C8D8 6. The scope of patent application and the third current, and the output current generated therein corresponds to the second current. 2 5. The current source according to item 24 of the scope of patent application, wherein the first current supply circuit includes a first transistor (4 2), the second current supply circuit includes a second transistor (4 4), and wherein the first The relative size of the transistor (4 2) and the second transistor (4 4) provides a ratio and determines the 値 of the second and third currents. 2 6 · The current source according to item 25 of the scope of patent application, in which the power source and the current source are in an integrated circuit without using any external components to provide output current. 27. A current source and a threshold voltage generating device to supply an output current and a corresponding threshold voltage signal, including: a) a current generating circuit for generating a first current; b) supplying a first current through Many first elements, each element has a corresponding size, wherein the proportion of the element size determines the amount of current flowing through each X element, and the output current generated therein corresponds to the current flowing through a given element; and c) The voltage generating circuit is coupled to a number of first components to generate a threshold voltage signal corresponding to the output current, so any change in the output current is proportionally reflected in the threshold voltage signal. 2 8. The device according to item 27 of the scope of patent application, wherein the current generating circuit includes a first resistor (5 4) and an amplifier (40) coupled to receive the first predetermined voltage signal, and the first resistor (5 4 ) Provides a voltage drop. (Please read the precautions on the back before copying this page) -------- Order ---------. Printed purple paper printed by the Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Standard (CNS) A4 specification (210 X 297 mm) -6- VI. Patent application scope Can Book 0808 2 9 · The device according to item 28 of the patent application scope 'which straddles the first resistor (5 4) The voltage drop corresponds to the first predetermined voltage signal 0. The device according to item 27 of the patent application 'in which many components include a first predetermined portion supplying a first current and a second predetermined portion supplying a first current The first current supply circuit of the circuit and the second current. The first current divides the first and second predetermined parts. The second current supply circuit, the proportion of the supply circuit determines the first reading. The production & electricity of the printed consumer co-operative cooperative 3 2. The voltage generation circuit 2 has a predetermined partial voltage signal. 3 3. The radio current is also provided by 3 4 · The current source and the threshold components 3 5. The pulse wave and each step are: a) The device includes a level and a device according to item 30 of the scope of the patent application, where the produced current A first predetermined portion corresponding to the first current. The device according to item 31 of the scope of the patent application, wherein the electricity includes a current mapping circuit, which maps the first current, thereby forming a mapped current, which is used to generate a threshold power. A third voltage generating device larger than the first power according to the scope of the patent application includes an output current. A device that generates two terms representing the output of vertical sync pulses of a composite video, where the second predetermined part of the mapping. A three-item device, in which the electrical integration circuit does not require a method for each horizontal synchronization signal in the external signal, including the step-receiving of signals that represent all the synchronization pulses in the composite video signal and vertical synchronization pulses; China National Standard (CNS) A4 Specification (210 X 297 mm) Please fill in this page again. A8 B8 C8 D8 Ministry of Economic Affairs, Temporary Property Bureau, Beiya, Consumer Cooperation, Du Printing 6. Scope of patent application b) Generate representative pulses in the signal The output signal has a first logic voltage level and a second voltage logic level. C) When the output signal is at the first voltage logic level, a current source is used to generate a first current flowing through the first element. The current provides an output current to raise the level of charge stored in the storage unit. The ratio of the first current flowing through the second element and the third element to the second element and the third element determines the current flowing through the second element and the third element. Current 値, and the output current therein corresponds to the current flowing through the second element; and d) when the output signal rises to the second voltage logic level, the charge stored in the storage unit is released Put to a level; e) generate a threshold voltage signal corresponding to the output current, so any change in the output current will be reflected in the threshold voltage signal in proportion to the modulation, where only when the level of the charge exceeds a predetermined level When the threshold level is reached, the step of generating the output signal is started, and the level of the charge rises above the predetermined threshold level to start the step of generating the output signal, including representing each horizontal cycle pulse in the output signal pulse wave and Every other vertical sync pulse. 36. The method according to item 35 of the scope of patent application, wherein the second f element includes a second transistor and the third element includes a third transistor, wherein the relative size of the second transistor and the third transistor Provide a ratio 'This ratio determines the current 値 through the second and third elements. 37. The method according to item 36 of the scope of patent application, wherein the step of generating a threshold voltage signal includes mapping a current flowing through the third element 'to form a mapped current ^ and using the mapped current to generate a threshold voltage signal. (Please read the note $ on the back before filling in this page) i — — — —II ^ «1— I ϋ ϋ I Ac This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)- 8-震 08 VI. Patent application scope 3 8. According to the method of item 37 of the patent application scope, the reflection current / / of the radiation current is proportionally larger than the current flowing through the third element #. 3 9. — A device for generating an output signal representing each horizontal sync pulse and every Nth vertical sync pulse in a composite video signal, wherein the first time period exists between the horizontal sync pulses and the second time period Existing between N vertical synchronization pulses, the device includes: a) (the level of the storage unit (C1) for storing the charge b) the charge! The circuit should be coupled to the storage unit (C 1) for raising the charge level. The charge supply circuit includes a current and a source, which provides an output current by generating a first current flowing through the first element, wherein the supplied first current flow Through the second and third elements, the ratio of the second and third elements determines the current flowing through the second and third elements, where the desired output current corresponds to the current flowing through the second element; c) the voltage generating circuit is coupled to The charge supply circuit generates a threshold voltage signal corresponding to the output current. Therefore, any changes in the output current will be proportionally reflected in the threshold voltage signal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics. (20) is coupled to the storage unit (C1) and the voltage generating circuit to determine when the level of charge exceeds a predetermined threshold level, wherein the charge supply circuit will raise the charge level to exceed the predetermined level in a third time period Threshold voltage signal level; and e) an output generating circuit coupled to the monitoring circuit for generating an output pulse representing horizontal and vertical synchronous pulses Signal, in which the output pulse wave signal is generated only when the level of charge exceeds a predetermined threshold voltage signal level ° 40. According to the device of the scope of patent application No. 39, 'where the third paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) 7〇 ^ Printed by A8 B8, C8 __D8 in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The scope of patent application is shorter than the first time period but greater than the second time period, resulting in charge The level rises above a predetermined threshold voltage signal level to generate an output pulse signal corresponding to each horizontal sync pulse and every Nth vertical sync pulse in the composite video signal. 41. The device according to item 40 of the scope of patent application, wherein the second element includes a second transistor (4 2), the third element includes a third transistor (4 4), and wherein the second transistor (4 2) .) The relative magnitude with the third transistor (4, 4) provides a ratio that determines the current 値 through the second and third elements. 4 2. The device according to item 41 of the scope of patent application, wherein the voltage generating circuit includes a current map: circuit_: it maps the current flowing through the third element to form a first mapped current, which is used to generate a threshold voltage signal. 4 3. The device according to item 42 of the scope of the applied specialty, wherein the storage unit (C 1) is a capacitor. The device according to item 43 of the scope of patent application, wherein the length of the first time period g is twice the length of the second time period. 4 5. The device according to item 44 of the scope of the patent application, wherein the devices are included in a integrated circuit, and the capacitor (C 1) is also included in the integrated circuit. 4, 6. The device according to item 45 of the scope of the patent application, wherein the output pulse signal is regarded as a feedback signal and is coupled to control the charge supply circuit. t 4 7. —A current source and a threshold voltage generating device for supplying a current and a threshold voltage signal to a sequential circuit to generate a charge across the storage unit and a threshold voltage signal equivalent to the charge 'includes : ------------------- ^ ---- 1 ---- MIVT (please read the note ^. On the back before filling this page) Applicable to Chinese National Standard < CNS) A4 Specification (210 X 297 mm) -10- VI. Patent Application Bow) First Resistor (5 4 >;,, < Please read the precautions on the back first (Fill in this page) b) the amplifier (40) is coupled to receive the first predetermined voltage signal, and provides a voltage drop across the first resistor (54) to generate a second current 〆, »c) the first current supply circuit Coupled to a first resistor (54) to supply a second current; and d) a second current supply circuit is coupled to the first resistor to supply a third current, wherein combining the second and third currents is equal to the first current, And the ratio of the first current supply circuit to the second current supply circuit determines the 値 of the second and third currents, and the output generated therein The current corresponds to the second current; and e) the voltage generating circuit is coupled to the second current supply circuit to generate a threshold voltage signal corresponding to the output current, so any change in the output current will be proportionally reflected in the threshold voltage signal Inside. Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs have cooperated with each other to print the number 4 8 · According to the patent application No. 47 of the device, wherein the first power supply circuit should include the first transistor (4 2), the second current The supply circuit includes a second transistor (44), and the relative size of the first transistor (42) and the second transistor (4 4) provides a ratio that determines the 値 of the second and third currents. 49. The device according to item 48 of the patent application, wherein the voltage-producing circuit includes a current mapping circuit that maps a third current to form a mapped current for generating a threshold voltage signal. 5 0 · According to the device of the scope of patent application No. 49, the mapping current therein is also proportionally increased to greater than the third current ° 5.1. According to the device of the scope of patent application No. 50, the electricity-11- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) A8 B8 · C8 D8 VI. Patent application scope The current source and threshold voltage generating device are included in an integrated circuit without any external components The "output" and "threshold voltage" signals are output in total. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -12- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)