WO1998047173A1 - Transistor mos a fort gradient de dopage sous sa grille - Google Patents
Transistor mos a fort gradient de dopage sous sa grille Download PDFInfo
- Publication number
- WO1998047173A1 WO1998047173A1 PCT/FR1998/000751 FR9800751W WO9847173A1 WO 1998047173 A1 WO1998047173 A1 WO 1998047173A1 FR 9800751 W FR9800751 W FR 9800751W WO 9847173 A1 WO9847173 A1 WO 9847173A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- nitrogen
- type
- substrate
- conductivity
- mos transistor
- Prior art date
Links
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 26
- 238000002513 implantation Methods 0.000 claims abstract description 17
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 125000004429 atom Chemical group 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention relates generally to the formation of a very thin epitaxial layer on a more heavily doped substrate. It applies in particular to the manufacture of MOS transistors. It relates more particularly to very small MOS transistors in which the length of the gate is much less than a micrometer, for example from less than 0.1 ⁇ m to approximately 0.5 ⁇ m.
- FIG. 1 very schematically shows a sectional view of a conventional MOS transistor.
- This MOS transistor is formed in an active area of a monocrystalline silicon substrate 1 delimited by a thick oxide region 2.
- This thick oxide region has been represented as corresponding to a region obtained by growth of oxide according to a process says LOCOS. It could correspond to any known type of delimitation of active zones, for example digging of the surface of the silicon and filling of oxide.
- the MOS transistor comprises a gate 4 provided with lateral spacers 5, commonly made of silicon oxide or silicon.
- the gate 4 is separated from the silicon surface by a layer of gate oxide 6.
- the drain and the source are represented as being of the LDD type, that is to say comprising more weakly doped regions 10 and 11 extending to the limits of the grid and more heavily doped regions 12 and 13 extending substantially to the limits of the spacers.
- the regions 10 and 11 are formed by implantation using the grid 4 as a mask, and the regions 12 and 13 are formed by implantation as the mask the grid 4 widened by the spacers 5.
- the substrate is of type P and the regions 10 to 13 of type N.
- the operating mode of such MOS transistors is well known.
- grid 4 When a voltage is applied to grid 4, the type of apparent conductivity of the surface substrate reverses under the grid region and an inversion or depletion layer is formed which constitutes a channel region between regions 10 and 11. This channel provides conduction between the source and the drain if a suitable voltage is applied between source and drain.
- this MOS transistor is subject to various parasitic effects and in particular to the phenomenon of piercing (in English "punch through").
- the piercing phenomenon takes place in particular when the doping under the gate is such that, for a certain gate voltage, the inverted zone under the gate extends deep between the heavily doped source and drain regions 12 and 13. This piercing effect causes that, if the voltage remains applied between source and drain while the gate voltage is interrupted, the MOS transistor does not turn back on.
- the drain-substrate and source-substrate junctions are relatively deep and this piercing phenomenon can be avoided by known means.
- the dimensions of the MOS transistor become clearly submicronical (that is to say that the length of the gate becomes less than a micrometer, for example of the order of less than 0.1 ⁇ m to approximately 0.5 ⁇ m)
- all the dimensions of the transistor are reduced accordingly and in particular the junctions become very shallow.
- the junction depth xl of regions 10 and 11 can be of the order of 50 nm (500 angstroms) and the junction depth x2 of regions 12 and 13 can be of around 200 nm. Under such conditions, the piercing phenomenon is particularly acute.
- One of the known means for avoiding piercing consists in producing in the channel zone a lower weakly doped upper region followed by a more heavily doped region (see EP-A-0530046 of SGS-Thomson Microelectronics, Inc). Then, when the gate is excited, the depletion zone is limited to the thickness of the least doped region and there is no inversion of the most doped region. This means that one seeks to obtain a vertical doping profile under the grid such as that represented by the curve 20 of FIG. 2 with a first doping level cl when the depth is less than xO, the depth xO being less than the junction depth x1, and a second significantly higher doping level c2 at least in a determined region beyond the depth xO.
- Another object of the present invention is to apply this method to the manufacture of a very small MOS transistor (less than 0.1 to 0.5 micrometer of gate length).
- the present invention also relates to a MOS transistor obtained by the method of the present invention.
- the present invention provides a method of manufacturing a zone of the first type of conductivity with a steep doping gradient in the direction of the thickness, comprising the steps consisting in providing a monocrystalline semiconductor substrate, coating the substrate with a thin oxide layer, implant nitrogen in the upper surface of the substrate, the nitrogen dose being between 5 10 13 and 5 10 15 at./cm 2 , anneal, and make grow an epitaxial layer with a lower doping level than the substrate, or intrinsic.
- this method consists in using a substrate of any conductivity type and in carrying out a nitrogen implantation and an implantation of dopant atoms of the first type of conductivity. quickly, before making an epitaxial layer of the first type of conductivity with a low doping level, or intrinsic.
- the dose of nitrogen is between 1 and 10 10 1 ⁇ at./cm 2 . and more preferably between 3 and 7 ÎO 1 ⁇ at./cm 2 .
- nitrogen is implanted at an energy of the order of 10 keV.
- the epitaxial layer has a thickness of the order of 30 to 60 nm. This method applies to the manufacture of the area located under the gate of an MOS transistor from a substrate of the first type of conductivity.
- the present invention also relates to an MOS transistor of the LDD type comprising, under its gate area, a first lightly doped region followed by a second region of the same type of conductivity with a higher doping level with a large doping gradient between the two. regions, in which the interface zone between the two regions contains nitrogen atoms.
- the first region extends over a depth substantially equal to or less than the depth of the lightly doped LDD type drain and source regions.
- FIG. 1 described previously represents schematically a sectional view of an N-channel MOS transistor
- FIG. 2 represents doping profiles
- FIGS. 3A to 3C represent successive stages in the manufacture of an MOS transistor according to the present invention
- FIG. 4 represents a doping profile obtained for a MOS transistor according to the present invention.
- the method according to the present invention provides for forming on the surface of a layer of silicon doped with a first type of conductivity, for example type P, an implantation of nitrogen at low dose while the upper surface of the structure is coated with a thin layer of oxide, then annealing and then growing an epitaxial layer of the same type of conductivity as the substrate but very weakly doped or even intrinsic.
- a first type of conductivity for example type P
- an implantation of nitrogen at low dose while the upper surface of the structure is coated with a thin layer of oxide
- the method provides, after the implantation of nitrogen, to carry out the implantation of a dopant, for example boron to obtain the type of conductivity P, then to carry out an annealing and then only to deposit an epitaxial layer with a lower doping level (quasi-intrinsic) than that resulting from the implantation of boron, the epitaxial layer also being doped with boron, preferably in situ.
- a dopant for example boron
- annealing annealing
- the nitrogen implantation dose will be chosen to obtain the desired effect. It should be sufficient to block an upward exodiffusion of the doping atoms contained in the substrate but should not be too high to avoid creating dislocations in the substrate which would prevent a good quality monocrystalline epitaxial layer from being obtained.
- nitrogen will be implanted at low energy, for example 10 keV, with a dose in the range of 5 10 13 to 5 10 15 at./cm 2 , and preferably in the range of 1 to 10 10 14 at./cm 2 and more preferably in a range of 3 to 7 10 14 at./cm 2.
- the procedure is in an active area of a substrate 1 delimited by thick oxide 2.
- the substrate 1 is initially doped with type P at a concentration of the order of ÎO 1 ⁇ at./cm 3 .
- the substrate is covered with a thin layer of oxide 30.
- Nitrogen atoms are implanted on the surface under 10 keV at a dose of the order of 3 to 7 10 14 at./cm 2 .
- Boron is then implanted at a dose capable of providing after annealing a maximum doping of the order of 10 ---- 8 at./cm 3 .
- Annealing is then carried out, for example at 800 ° C. for 10 minutes.
- the oxide layer 30 is eliminated and a lightly doped P type silicon layer 31 is grown by epitaxy, for example with boron and with a doping concentration. of the order of ÎO 1 ⁇ atoms / cm 3 , or intrinsic.
- This layer may have a very small thickness, for example of the order of 20 to 60 nm.
- FIG. 4 the elements of which are designated by the same references as in FIG. 1.
- xO denotes the thickness of the epitaxial layer 31, xl the depth of regions 10 and 11 and x2 the depth of regions 12 and 13.
- the presence of a lower region including the concentration of dopants has a high gradient compared to that of the epitaxial layer, and extending downwards from the depth xO ensures the desired result of avoiding drilling phenomena.
- the Applicant has carried out tests by manufacturing an epitaxial layer 31 without the implantation of nitrogen and then an epitaxial layer 31 with the implantation of nitrogen according to the present invention and has found that the value a was only of the order of twenty nm in the context of the present invention but became significantly greater than 40 nm when an epitaxial layer 31 was produced without providing for prior implantation of nitrogen.
- MOS transistor of extremely small dimensions, for example a MOS transistor with a gate dimension of 0.12 ⁇ m, for which the values that xO, xl and x2 would be 20, 40 and 70 nm, as shown by way of example in Figure 4.
- the inventors observed on a completed experimental device that the nitrogen was essentially concentrated in the interface zone under the epitaxial layer.
- the transistor according to the present invention will have the desired effects of insensitivity to the piercing phenomenon.
- the invention has been described in the context of a particular example, and in particular in the case where the dopant is boron.
- the dopant is boron.
- the advantages of the present invention are also obtained. However, the results are less good because indium produces dislocations difficult to make up for by annealing.
- the dopants could also be of type N.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/402,853 US6465332B1 (en) | 1997-04-11 | 1998-04-14 | Method of making MOS transistor with high doping gradient under the gate |
EP98920620A EP0974159A1 (fr) | 1997-04-11 | 1998-04-14 | Transistor mos a fort gradient de dopage sous sa grille |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR97/04710 | 1997-04-11 | ||
FR9704710A FR2762138B1 (fr) | 1997-04-11 | 1997-04-11 | Transistor mos a fort gradient de dopage sous sa grille |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998047173A1 true WO1998047173A1 (fr) | 1998-10-22 |
Family
ID=9506002
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR1998/000751 WO1998047173A1 (fr) | 1997-04-11 | 1998-04-14 | Transistor mos a fort gradient de dopage sous sa grille |
Country Status (4)
Country | Link |
---|---|
US (1) | US6465332B1 (fr) |
EP (1) | EP0974159A1 (fr) |
FR (1) | FR2762138B1 (fr) |
WO (1) | WO1998047173A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1139431A2 (fr) * | 2000-03-30 | 2001-10-04 | International Business Machines Corporation | Réduction des effets inversés de canal court |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2794898B1 (fr) | 1999-06-11 | 2001-09-14 | France Telecom | Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication |
TW486750B (en) * | 2000-04-17 | 2002-05-11 | Varian Semiconductor Equipment | Methods for forming ultrashallow junctions in semiconductor wafers using low energy nitrogen implantation |
US9728637B2 (en) | 2013-11-14 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanism for forming semiconductor device with gate |
US9281215B2 (en) * | 2013-11-14 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanism for forming gate |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2301923A1 (fr) * | 1975-02-20 | 1976-09-17 | Siemens Ag | Procede pour l'elimination de composants parasites dans les circuits integres |
EP0253059A2 (fr) * | 1986-03-20 | 1988-01-20 | Hitachi, Ltd. | Procédé pour supprimer la montée de la couche enterrée d'un dispositif semi-conducteur |
EP0530046A1 (fr) * | 1991-08-30 | 1993-03-03 | STMicroelectronics, Inc. | Transistor en circuit intégré |
US5557129A (en) * | 1994-06-22 | 1996-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor MOSFET device having a shallow nitrogen implanted channel region |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6031231A (ja) * | 1983-07-29 | 1985-02-18 | Toshiba Corp | 半導体基体の製造方法 |
-
1997
- 1997-04-11 FR FR9704710A patent/FR2762138B1/fr not_active Expired - Fee Related
-
1998
- 1998-04-14 US US09/402,853 patent/US6465332B1/en not_active Expired - Lifetime
- 1998-04-14 WO PCT/FR1998/000751 patent/WO1998047173A1/fr not_active Application Discontinuation
- 1998-04-14 EP EP98920620A patent/EP0974159A1/fr not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2301923A1 (fr) * | 1975-02-20 | 1976-09-17 | Siemens Ag | Procede pour l'elimination de composants parasites dans les circuits integres |
EP0253059A2 (fr) * | 1986-03-20 | 1988-01-20 | Hitachi, Ltd. | Procédé pour supprimer la montée de la couche enterrée d'un dispositif semi-conducteur |
EP0530046A1 (fr) * | 1991-08-30 | 1993-03-03 | STMicroelectronics, Inc. | Transistor en circuit intégré |
US5557129A (en) * | 1994-06-22 | 1996-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor MOSFET device having a shallow nitrogen implanted channel region |
Non-Patent Citations (1)
Title |
---|
"HIGH PERFORMANCE FET STRUCTURE MADE USING MEDIUM TO LOW TEMPERATURE EPITAXY", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 11, 1 April 1991 (1991-04-01), pages 53 - 55, XP000110307 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1139431A2 (fr) * | 2000-03-30 | 2001-10-04 | International Business Machines Corporation | Réduction des effets inversés de canal court |
EP1139431A3 (fr) * | 2000-03-30 | 2003-08-13 | International Business Machines Corporation | Réduction des effets inversés de canal court |
Also Published As
Publication number | Publication date |
---|---|
FR2762138B1 (fr) | 1999-07-02 |
FR2762138A1 (fr) | 1998-10-16 |
EP0974159A1 (fr) | 2000-01-26 |
US6465332B1 (en) | 2002-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102082191B1 (ko) | 에피택셜 웨이퍼, 접합 웨이퍼 및 이들의 제조 방법 | |
EP1837916B1 (fr) | Procédé de réalisation d'un transistor à canal comprenant du germanium | |
EP0164281B1 (fr) | Procédé de fabrication d'une couche isolante enterrée dans un substrat semiconducteur, par implantation ionique | |
EP2840594B1 (fr) | Recristallisation de blocs de source et de drain par le haut | |
FR2530867A1 (fr) | Dispositifs mos a barriere de schottky et leur procede de fabrication | |
EP1039546A1 (fr) | Dispositif semi-conducteur à courant de fuite réduit et son procédé de fabrication | |
JPH0778998A (ja) | 薄膜トランジスタを具える電子デバイスの製造方法 | |
FR2468208A1 (fr) | Dispositif semiconducteur avec une diode zener | |
WO1998047173A1 (fr) | Transistor mos a fort gradient de dopage sous sa grille | |
FR3067516A1 (fr) | Realisation de regions semiconductrices dans une puce electronique | |
FR2953062A1 (fr) | Diode de protection bidirectionnelle basse tension | |
FR2803101A1 (fr) | Procede de fabrication de composants de puissance verticaux | |
FR3051972A1 (fr) | Procede de realisation d'un transistor comprenant des source et drain obtenus par recristallisation de semi-conducteur | |
EP1328969B1 (fr) | Procédé de formation d'un transistor mos | |
FR2791178A1 (fr) | NOUVEAU DISPOSITIF SEMI-CONDUCTEUR COMBINANT LES AVANTAGES DES ARCHITECTURES MASSIVE ET soi, ET PROCEDE DE FABRICATION | |
FR2593641A1 (fr) | Procede pour fabriquer un transistor a effet de champ a grille isolee. | |
EP4235765A2 (fr) | Procédé amélioré de fabrication d'un circuit intégré comportant un transistor nmos et un transistor pmos | |
FR2766845A1 (fr) | Procede d'epitaxie sur un substrat de silicium comprenant des zones fortement dopees a l'arsenic | |
EP0948038B1 (fr) | Procédé de fabrication d'une diode à avalanche à seuil réglable | |
JP3274038B2 (ja) | 半導体装置 | |
EP0037764B1 (fr) | Structure de dispositif à semiconducteur à anneau de garde, et à fonctionnement unipolaire | |
FR3069702A1 (fr) | Procede de fabrication simultanee de transistors soi et de transistors sur substrat massif | |
EP1033748A1 (fr) | Nouveau transistor à implantation d'indium dans un alliage SiGe et procédés de fabrication | |
EP0065464B1 (fr) | Procédé de fabrication de circuits intégrés de type MOS | |
FR2877141A1 (fr) | Procede de formation de silicium-germanium dans la partie superieure d'un substrat de silicium |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1998920620 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 09402853 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 1998920620 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: JP Ref document number: 1998543567 Format of ref document f/p: F |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1998920620 Country of ref document: EP |