WO1998033274A1 - Power switch circuit - Google Patents

Abstract

A power switch circuit, whose manufacturing cost can be reduced by integrating a control circuit for overheat/overcurrent protection with an insulated-gate semiconductor device such as a power MOSFET (30) or IGBT (insulated-gate bipolar transistor). For high-speed operation, the insulated-gate device is connected at its gate with a MOSFET (32) as a gate resistor, and switches (SW2, SW3) are provided so that a parasitic npn transistor in the MOSFET (32) can never be forward-biased between its emitter and base to prevent the increase in gate-drain leakage and the decrease in allowable drain voltage.

Description

 Specification

Power switch circuit Technical field

 Uses an insulated gate semiconductor device such as a power MOSFET or IGBT (Insulated gate bipolar transistor) and an insulated gate semiconductor device with a built-in control circuit that has its control circuit on the same chip as the power switch element. In particular, the present invention relates to speeding up of a switch circuit in which the power switch element is source-follower connected, prevention of malfunction, and prevention of withstand voltage degradation. Background art

Japanese Patent Application Laid-Open No. 7-52893 discloses an example in which an overheat protection circuit is incorporated on the same chip to improve the reliability of the power MOSFET. In this conventional example, a gate resistor is connected between the external gate terminal and the internal gate terminal, and an M • SFET for a protection circuit is connected between the internal gate terminal and the external source terminal. If the chip temperature rises above the specified temperature, the power MOSFET is turned off before the power MOSFET is destroyed by turning on the MOSFET for protection circuit and flowing a gate current to the resistor. it can. The process employs a self-isolation structure in which a control circuit is formed in the drain region of the power MOSFET to reduce the number of steps. Accordingly, although the process cost is suppressed at low cost, there is a parasitic npn transistor existing between the drain of the protection MOSFET and the drain of the power MOSFET. In view of the above, Japanese Patent Application Laid-Open No. 7-58293 discloses an emitter of the parasitic npn transistor. A diode for interrupting current is connected in series with the MOSFET for the protection circuit, and a diode for preventing breakdown of the diode is connected between an external base terminal and an external source terminal. Accordingly, when the gate terminal becomes a negative voltage with respect to the source terminal, the parasitic npn transistor turns on, thereby preventing a leak current from flowing from the drain terminal to the gate terminal. Protection was realized.

 In the automotive field, in order to construct a power switch circuit, the power MOSFET with built-in n-channel protection circuit is often used in a high-side switch circuit from the viewpoints of low on-resistance and safety. A high-side switch circuit is a circuit in which a power switch is wired to the power supply terminal side and a load is wired to the ground terminal side.The load is wired to the power supply terminal side, and the power switch is wired to the ground terminal side. This is a circuit configuration often used in in-vehicle power switch circuits because it has higher safety than a single-sided switch circuit. This is because, in the case of a single-sided switch circuit, if the load contacts the chassis (ground), overcurrent will continue to flow through the load and cause a fire, etc. This is because no current flows through the load even if it touches the chassis.

The power MOSFET 310 with a built-in control circuit used as the power switch of the high-side switch circuit is an n-channel type element that can obtain a low on-resistance element at a lower cost than the p-channel type. For this reason, the power MOSFET with a built-in protection circuit is used in a source follower connection. To shut off this element, it is necessary to apply a lower voltage to the gate terminal than to the source terminal. Since the power MOSFET with a built-in protection circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 7-582293 is provided with the negative gate voltage protection as described above, a power MOSFET with an n-channel protection circuit with a built-in protection circuit is used. CT / JP 7/0 157

Three

There was a feature that a side switch circuit could be realized.

 On the other hand, in order to increase the frequency of the power M 0 SFET with a built-in control circuit that has improved reliability by incorporating an overheat protection circuit, an example in which a MO SFET is used in place of the above gate resistor is disclosed in Japanese Patent Laid-Open No. 6-244444. No. pp. 147-64. In this embodiment, when the power MOSFET is turned on, the MOSFET instead of the gate resistor is turned on, and when the overheat cutoff circuit operates, the MOSFET instead of the gate resistor is turned off. As a result, the power MOSFET can be turned on at a high speed, and at the same time, the gate current after overheating is prevented from becoming excessive. Disclosure of the invention

 In the circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 7-52893, the gate resistance is usually as high as about 5 to 1 OkQ in order to prevent the current after the overheat protection operation from becoming excessive. Was used. Therefore, there is a problem that the switching speed is limited to about 5 to 10 ns due to the input capacitance of the power MOSFET and the RC time constant of the gate.

In the case of the high-frequency driving method described in Japanese Patent Application Laid-Open No. 6-244444, a MOSF is used instead of a gate resistor, but the drain and power of this 0SF are used. When a negative voltage is applied between the gate terminal and the source terminal of the power MOSFET with built-in control circuit, the parasitic bipolar transistor is turned on. Therefore, there is a problem that a leak current flows from the drain terminal to the gate terminal. However, for the parasitic bipolar transistor built in the MOS FET added in place of the gate resistor, the diode disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 7-52893 was used. There was a problem that the method of preventing parasitic bipolar transistor operation could not be used. This is because, in the above MOS FET added in place of the gate resistor, a bidirectional drain current must flow to turn on and off the power MOSFET, but a diode for preventing parasitic diode operation is connected in series. Otherwise, the power MOSFET cannot be turned off. For this reason, there is a problem that a power switch circuit that operates at high speed using a power MOS FET with a built-in control circuit as a source follower circuit cannot be realized.

 The first object of the present invention is to use a conventional power MOS SFET process to minimize the increase in the process cost and to use a control circuit built-in power MOS FET having a built-in MO SFET in the drain region of the power MO SFET. It is an object of the present invention to provide a power switch circuit using the power MOS FET with a built-in control circuit in a source follower.

 A second object of the present invention is to use a conventional IGBT process to minimize the increase in process cost, to use a IGBT with a built-in control circuit having a MOS FET built in the n-type base region of the IGBT, and to use this IGBT with a built-in control circuit. It is an object of the present invention to provide a power switch circuit used in a mixer follower. In order to achieve the above object, in a power switch circuit according to the present invention,

 It has at least an insulated gate semiconductor device (310) with built-in control circuit, a battery (301), and a load (304),

The insulated gate semiconductor device with built-in control circuit (310) is

The semiconductor substrate is covered with the N-type first impurity region (102), the P-type second impurity region (107) in contact with the first impurity region, and the second impurity region. First transistor including N-type third impurity region (109a) (Power MO S 30) and

A p-type fourth impurity region (104a) in contact with the first impurity region; and n-type fifth and sixth impurity regions (109b) covered by the fourth impurity region. , C), a second transistor (MO SFET 32), a first terminal (1) connected to the first impurity region,

A gate terminal (2) connected to the fifth impurity region (109b) in the second transistor;

A second terminal (3) connected to the third impurity region,

A first switch circuit (SW 2) provided between the gate terminal (2) and the fourth impurity region;

A second switch circuit (S W3) provided between the second terminal (3) and the fourth impurity region;

When the voltage of the gate terminal (2) is negative with respect to the second terminal (3), the second switch circuit (SW3) is turned off and the first switch is turned off. The circuit (SW2) is on and

When the voltage of the gate terminal (2) is positive with respect to the second terminal (3), the second switch circuit (SW3) is turned on and the first switch circuit is turned on. (SW2) is off,

When the voltage of the first terminal (1) is higher than a predetermined positive voltage with respect to the second terminal (3), the second switch circuit (SW3) is turned off and the second switch circuit (SW3) is turned off. 1 switch circuit (SW2) is on,

In the insulated gate semiconductor device (310) with a built-in control circuit, the first terminal (1) is connected to the battery (301), and the second terminal (3) is connected to the load (304). ), And the main current between the first terminal (1) and the second terminal (3) is controlled by the gate terminal (2). is there.

 As a more preferable configuration,

The gate electrode of the first transistor is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and a ground line (6) connected to the second terminal (3);

A protection circuit (21) for detecting the overload state of the first transistor and turning on the third switch circuit and increasing the source-drain resistance of the second transistor is further provided. You only have to have it.

 Also, as another suitable configuration,

The gate electrode of the first transistor of the insulated gate semiconductor device with a built-in control circuit (310) is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and the ground line (6) connected to the fourth impurity region;

A protection circuit that detects an overload state of the first transistor, turns on the third switch circuit, and increases the source-drain resistance of the second transistor; May be further provided.

 When the present invention is configured more specifically,

The third switch circuit (SW1) activates a third transistor (31 or 42) that is turned on by a signal indicating that the protection circuit has detected an overload state of the semiconductor device. You only have to have it.

 Further, if the present invention has a more preferable configuration,

The first transistor with its anode connected to the first Transit gate Further comprising a diode (91 or 89),

The first diode (91 or 89) may be connected in series with the source 'drain path of the third transistor (31 or 42). Further, if the present invention has a more preferable configuration,

The first switch circuit (SW2) is turned on when the voltage of the gate terminal (2) is negative with respect to the second terminal (3). When,

A fifth transistor (40) which is turned on when the voltage of the first terminal (1) is higher than the predetermined positive voltage with respect to the second terminal (3) may be provided.

 When the present invention is configured more specifically,

The fourth transistor (39) is an N-type transistor, and its source / drain path is provided between the gate terminal (2) and the fourth impurity region, and its gate is provided at the gate of the fourth transistor (39). It may be connected to two terminals (3). If the present invention has a more preferable configuration,

The fifth transistor (40) has an N-type transistor whose source / drain path is provided between the gate terminal (2) and the fourth impurity region.

A second diode (83) may be further provided between the gate of the fifth transistor (40) and the first terminal (1).

 When the present invention is configured more specifically,

The second diode (92) is formed by the first impurity region and a P-type seventh impurity region (103c) in contact with the first impurity region. The impurity region is formed between the second impurity region and the first impurity region when the predetermined positive voltage is applied to the first terminal (1). What is necessary is just to form in the position where the depletion layer formed between reaches.

 Further, if the present invention has a more preferable configuration,

The power switch circuit according to any one of claims 1 to 9, wherein the second switch circuit (SW3) is provided between the second terminal (3) and the fourth impurity region. It suffices that a source-drain path is provided, and the gate thereof includes an N-type sixth transistor (38) connected to the gate terminal (2).

 Also, as another suitable configuration,

The above-mentioned insulated gate semiconductor device with built-in control circuit (310)

The N-type first impurity region (102) of the semiconductor substrate, the P-type second impurity region (107) in contact with the first impurity region, and the second impurity region A first transistor (power MOS 30) including an N-type third impurity region (109 a);

The P-type fourth impurity region (104a) in contact with the first impurity region and the N-type fifth and sixth impurity regions (109b, c) a second transistor (MO SFET 32), and a first terminal (1) connected to the first impurity region;

A gate terminal (2) connected to the fifth impurity region (109b) of the second transistor,

A second terminal (3) connected to the third impurity region,

A first switch circuit (SW2) provided between the gate terminal (2) and the fourth impurity region;

A second switch circuit (SW3) provided between the second terminal (3) and the fourth impurity region;

A first terminal provided between the second terminal (3) and the fourth impurity region. And a resistance element (72).

When the voltage at the gate terminal (2) is negative with respect to the second terminal (3), the second switch circuit (SW3) is off and the first switch circuit is turned off. (SW 2) is on,

When the voltage of the gate terminal (2) is positive with respect to the second terminal (3), the second switch circuit (SW3) is turned on and the first switch is turned on. Switch (SW2) is off,

In the insulated gate semiconductor device (310) with a built-in control circuit, the first terminal (1) is connected to the battery (301), and the second terminal (3) is connected to the load (304). ), And the main current between the first terminal (1) and the second terminal (3) may be controlled by the gate terminal (2).

 These more specific configurations and operational effects will be clarified in the following description. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a block diagram of a semiconductor circuit according to a first embodiment of the present invention. FIG. 2 is a sectional structural view of a semiconductor device used in the semiconductor circuit according to the first embodiment of the present invention. '

 FIG. 3 shows a semiconductor circuit according to a second embodiment of the present invention.

 FIG. 4 shows a semiconductor circuit according to a third embodiment of the present invention.

 FIG. 5 shows a semiconductor circuit according to a fourth embodiment of the present invention.

 FIG. 6 shows a semiconductor circuit according to a fifth embodiment of the present invention.

 FIG. 7 shows a semiconductor circuit according to a sixth embodiment of the present invention.

FIG. 8 is a block circuit diagram of a semiconductor device according to a seventh embodiment of the present invention. FIG. 9 is a sectional view of a semiconductor device used in a semiconductor circuit according to a seventh embodiment of the present invention. FIG.

 FIG. 10 shows a semiconductor circuit according to an eighth embodiment of the present invention.

 FIG. 11 is a block circuit diagram of a semiconductor circuit according to a ninth embodiment of the present invention.

 FIG. 12 shows a semiconductor circuit according to a tenth embodiment of the present invention.

 FIG. 13 is a block circuit diagram of a semiconductor circuit according to the eleventh embodiment of the present invention.

 FIG. 14 is a block circuit diagram of a semiconductor circuit according to a 12th embodiment of the present invention.

 FIG. 15 is a sectional structural view of a semiconductor device used in the semiconductor circuit according to the 12th embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

 (Example 1)

 FIG. 1 shows a first embodiment of a semiconductor circuit according to the present invention.

In Fig. 1, 310 is the power M〇SFET with a built-in protection circuit with a built-in protection circuit 21, 304 is a load, 310 is a battery, 310 is a pre-driver, and 310 is its input terminal. . In this circuit, the control circuit built-in power MOSFET 310 used as a power switch is connected to the power supply terminal 303 side of the battery 301 by a source follower, and the load 304 is connected to the ground terminal 302. High side switch circuit connected to the side. A high-side switch circuit is a circuit in which a power switch is wired to the power supply terminal side, and a load is wired to the dunland terminal side.The load is wired to the power supply terminal side, and the power switch is wired to the ground terminal side. Because it is more secure than a single-sided switch circuit, This is a circuit configuration often used in a worst switch circuit. This is because, in the case of a single-sided switch circuit, if the load contacts the chassis (ground), an overcurrent will continue to flow through the load and cause a fire, etc. This is because no current flows through the load even if the load contacts the chassis.

 Also, the power MOSFET with built-in control circuit used as the power switch of the high-side switch circuit uses an n-channel element, which is less expensive than a p-channel type. For this reason, the pre-driver 315 needs to drive the gate terminal 2 by boosting the gate terminal 2 by about 5 V to 10 V from the power supply terminal 303 so that the on-resistance of the power -M 0 SFET 30 is sufficiently reduced. is there. To turn off the power MOSFET 30, lower the gate terminal 2 to ground 302. At this time, it should be noted that if the power MOSFET 30 is turned off at high speed, the gate terminal 2 of the power MOSFET 30 with built-in control circuit is driven more negatively than the source terminal 3. For this reason, the circuit configuration of the power MOSFET 310 with a built-in control circuit requires the following measures.

Control circuit built-in power MO SFET 310 protection circuit 2 1 has a built-in temperature detection circuit and overcurrent detection circuit i ±, even if a positive voltage is applied to the gate terminal. In an overload condition where a large current flows between terminal 1 and source terminal 3, the power M0 SFET 30 is forcibly shut off, or a switch circuit that limits the drain current of the power MO SFET 30 ( SW 1) is provided. ^ 〇 3 £ is the normal power 1 ^ 03? When switching the £ 30, the input signal from the gate terminal 2 to the gate of the power MOSFET 30 To enable high-speed switching. Protection in overload condition The overheating or overcurrent detection circuit built into the circuit 21 operates, and the protection circuit operates to close the switch circuit (SW1) by the signal X. The drain current of the MOSFET 30 can be cut off or limited to prevent device destruction. This circuit is characterized in that when the protection circuit operates, the voltage of the node 10 is reduced to increase the on-resistance of the MOSFET 32. As a result, when the protection circuit operates to cut off or limit the drain current of the power MOSFET 30, the gate current from the gate terminal 2 becomes less likely to flow, and the switch circuit (SW The charge in the gate of the power MOSFET 30 is released via 1). In this case, even when the on-resistance of the switch circuit (SW 1) is high, the MOSFET 32 suppresses the gate current, so that the power 0 SFET 30 can be cut off at high speed and the protection circuit operates. The characteristic is that the power consumption can be reduced because the gate current can also be reduced after the aging. On the other hand, as will be described later with reference to FIG. 2, the control circuit built-in power MOSFET 310 forms the control circuit 20 using a normal power MOSFET process in order to reduce the process cost. Therefore, although there is an advantage that the control circuit can be built in at a low process cost, the power M 0 SFET drain 102 is a collector and the control circuit MO SFET 32 is a drain area 109. b is an emitter, and a parasitic npn transistor 29 based on the body region 104 a of the MOSFET 32 which is a MOSFET for a control circuit is formed. Therefore, when the gate terminal becomes negative, a forward voltage is applied to the drain region 1 09 b of the MOS FET 32 connected to the gate terminal 2 and the body region 104 a of the MO SFET 32. As a result, there is a problem that the parasitic npn transistor 29 is turned on and a leak current flows from the drain terminal 1 to the gate terminal 2. In this embodiment, in order to solve this parasitic npn transistor problem, a switch circuit (SW 2) for connecting (short-circuiting) the body of the first MOS FET and the gate terminal 2, A switching circuit (SW3) that connects the SFET body 4 and the source terminal 3 is provided.

 If the voltage at gate terminal 2 is positive, SW 2 is off and SW 3 is on. Normally, when the voltage of the gate terminal 2 is positive, the power MOSFET 30 is turned on, the voltage of the drain terminal 1 with respect to the source terminal 3 rises, and the voltage of the gate terminal 2 becomes the drain terminal 1 It is made larger than the voltage of. Therefore, if SW 2 is kept on, a forward bias is applied to the PN junction between the body 4 of the MOS FET 32 and the drain terminal 1. That is, the collector-emitter of the parasitic npn transistor 29 is forward-biased, and the parasitic npn transistor 29 operates in the reverse direction. This causes a problem that a leak current flows from the gate terminal 2 to the drain terminal 1. Therefore, SW 2 is turned off and SW 3 is turned on, so that the body 4 of the MOSFET 32 has the same potential as the source terminal 3. Thus, there is a feature that the reverse operation of the parasitic npn transistor 29 can be prevented. On the other hand, when the voltage of the gate terminal 2 is negative with respect to the voltage of the source terminal 3, SW2 is turned on and SW3 is turned on. As a result, the body 4 of the MOSFET 32 has the same potential as the gate terminal 2 and prevents the parasitic npn transistor 29 from turning on. By doing so, the present embodiment is characterized in that a leak current from the drain terminal 1 to the gate terminal 2 can be prevented.

The measures described above are taken into account in Japanese Patent Application Nos. 7-2323297 and 8-2343573. However, the switching means (SW2 and SW3) operate by the voltage applied between the gate terminal 2 and the source terminal 3. Therefore, it has been newly discovered that when the voltage between the gate terminal 2 and the source terminal 3 is substantially equal, both SW 2 and SW 3 are turned off or become high impedance. That is, the base 4 of the parasitic npn transistor 29 has a floating or high impedance. Therefore, when a high voltage is applied to the drain terminal 1 when the voltage between the gate terminal 2 and the source terminal 3 is substantially equal, the parasitic npn transistor becomes the original drain of the power MOSFET 30. Base voltage lower than withstand voltage (approximately 70 V) Collector-emitter withstand voltage BV ceo (approximately 20 to 30 V when emitter is open) or open when emitter is open or It was found that there was a risk that a breakdown would occur at a value close to that, and a large current would flow from the drain terminal 1 to the gate terminal 2. Therefore, in the present invention, the voltages of the gate terminal 2 and the source terminal 3 are substantially equal to each other so that the parasitic npn transistor does not break down due to the collector breakdown voltage BV ceo, and the drain terminal 1 has a margin for the BV ceo. The second switching means (SW2) is also turned on when a positive voltage of about 10 to 20 V or more is applied. Thus, the withstand voltage between the collector and the emitter of the parasitic npn transistor 29 is equal to the withstand voltage between the drain and the source of the primary MOS FET 30. The withstand voltage between the collector and the emitter BV ces (base layer) If there is a short-circuit between the transmitters). Therefore, it is possible to prevent the drain MOS transistor 30 from deteriorating in drain withstand voltage. Here, when a positive voltage of about 10 to 20 V or more is applied, the second switching means (SW2) is turned on, but if the value is smaller than BV ceo, There is no problem in theory.

In other words, in this embodiment, an intelligent power MOSFET incorporating a protection circuit for improving reliability in a low-cost process can be operated at high speed, and even when the gate-source becomes negative, the operation of the parasitic element can be reduced. Prevent negative Gate voltage protection can be built in, and furthermore, even with such additional functions, the drain-source breakdown voltage of the power MOSFET does not decrease.

 FIG. 2 is a cross-sectional structure of the MOS FET 32 and the power MOSFET 30 shown in FIG. In FIG. 2, the resistivity of antimony or arsenic is 0.02 Ω · en! On a high-concentration n-type semiconductor substrate 101 of about 0.02 Ω · cm, a Ν-type epitaxial layer having a resistivity of about 1 to 2 Ω · cm is formed on the order of 10 βm.

 The part where the MO SFET 30 is formed has a gate oxide film 105 a of about 50 nm, a polycrystalline silicon gate layer 106 a formed thereon, and a polycrystalline silicon gate layer 106. The first p-type p-type diffusion layer 103 a with a depth of 6 m and a dose of about 1 E 15 square cm between the patterns a and the polycrystalline silicon gate layer 106 a are used as masks. Self-aligned depth of 2; / m, body p-type diffusion layer 107 with a dose of 5E13 square cm and depth 0.4 urn, dose 1E16Z square cm The source n-type diffusion layer 109 a is provided. In addition, a high concentration P-type diffusion with a depth of 0.5 im and a dose of about 1E15 square cm is used to obtain a uniform contact between the body 107 and the aluminum electrode 112a. A layer 11'0a is provided, and an aluminum electrode layer 112a serving as a source electrode is formed on the polycrystalline silicon gate layer 106a via an insulating layer 111. I have.

Further, a second p-type impurity layer 104 a having a body depth of 5 ^ m and a dose amount of about 2 E 13 no square cm is formed in the portion where the MOS FET 32 is formed. And a high-concentration n-type impurity layer 109 b and a high-concentration n-type diffusion layer 109 c serving as a drain impurity layer and a source impurity layer, respectively. High-concentration p-type impurity layer formed 110b Is provided. In addition, 106 b formed in the same process as 106 a is used as the gate electrode of the MOSFET for the protection circuit, and 108 is a dose of about 5 E 12 Z square cm for improving the drain withstand voltage. It is a low-concentration n-type offset region. The aluminum electrode layers 112b, 112c, and 112d are the drain electrode, source electrode, and body electrode of the M MSFET 32, respectively. Reference numeral 105b denotes a field oxide film having a thickness of about 1 / xm formed by selective oxidation.

 The control circuit built-in power M 0 SFET 310 uses a normal power MO SFET process to reduce the protection cost of the protection circuit MO SFETs such as the MOS SFET 32 to reduce the process cost. It is a self-separated structure formed in the pixel layer 102. This has the advantage that the control circuit can be built in at low cost, as in the conventional power MOSFET process, but as shown in Fig. 1, the drain terminal 1 of the power MOSFET is connected to the collector and the MOSFET 32 The drain region 109 b of the MOS FET 32 is used as an emitter, and a parasitic npn transistor 29 based on the body region 104 a of the MOSFET 32 is formed. However, in the semiconductor circuit of the present invention, as described with reference to FIG. 1 above, by controlling the voltage of the body 4 of the MOS FET 32 by using SW2 and SW3, it is possible to prevent the operation of the parasitic npn transistor 29 by using a power supply with a built-in control circuit. The feature is that MOS FET 310 is used. For this reason, there is a feature that a high-side switch circuit that can drive the load 304 at high speed by connecting the power supply with built-in control circuit MOSFET 310 that can be manufactured using an inexpensive process to the source circuit lower can be realized.

(Example 2) FIG. 3 shows a portion of a power MOS FET 310 with a built-in control circuit of a semiconductor circuit according to a second embodiment of the present invention. That is, in the present embodiment, only the portion of the power MOSFET 310 with a built-in control circuit in the embodiment shown in FIG. 1 is shown by a specific circuit. In addition, the ground 6 in FIG. 1 is an embodiment corresponding to the case of connecting to the source terminal 3 (connection a), and SW1 to SW3 are also shown as specific circuits. In this embodiment, a case is shown in which an overheat protection circuit and an overcurrent protection circuit are incorporated as the protection circuit 21.

 That is, SW 1 is a switch provided to open and close between the internal gate 5 and the source terminal 3 of the power MOSFET 30 so that the power MOSFET 30 does not break down even in an overload condition. It consists of M SFET 31 for protection and MO SFET 42 for overcurrent protection. SW2 is a switch that opens and closes the gate terminal 2 and the body 4 of the MOS FET 32, and turns on when the gate terminal 2 becomes negative with respect to the source terminal 3. It consists of a MOS FET 40 that turns on when the drain terminal 1 has a positive voltage of 10 to 20 V or more with respect to the source terminal 3 when the terminal 2 has almost the same potential. SW3 is a switch that opens and closes the source terminal 3 and the body 4 of the MOSFET 32, and is composed of a MOSFET 38.

At room temperature, when a positive gate voltage of about 5 to 10 V is applied to the gate terminal 2 to turn on the power MOS SFET 30, the MOS SFETs 3, 1, 3, 3, 4, 2, 3, 5 and 3 6, 39, 40 are off, and M〇 SFETs 34, 37, 38, 41 are on. The reason is as follows. That is, the resistor 66 and the diode 82 constitute a constant voltage circuit, and a constant voltage of about 3 V is applied to the cathode of the diode 82. At room temperature, the MOSFET 37 is gated by the resistor 65 and the voltage division of the diode row 81. Is applied with a voltage of 1.5 V or more. For this reason, the MOS FET 37 is on and the MOS SFET 36 is off. Also, the latch circuit composed of resistors 62, 63 and MOSFETs 34, 35 is designed so that the value of resistor 62 is approximately one digit larger than the value of resistor 63, so the gate terminal 2 When a positive voltage is applied, the MOSFET 34 is always on and the MOSFET 35 is off. Therefore, the MOS FET 31 is off. Therefore, when the voltage of the gate terminal 2 is applied, a current flows from the gate terminal 2 to the diode 90 and the resistor 61 to turn on the MOS FET 32 and turn on the gate of the power MOSFET 30. And the power M 0 SFET 30 turns on at high speed. The resistor 60 is provided to reduce a potential difference between the gate terminal 2 and the internal gate terminal 5 in a steady state. Further, the capacitor 25 is provided for increasing the gate voltage of the MOS FET 32 more quickly by the bootstrap effect when increasing the voltage of the gate terminal 2. When turning off the power MOSFET 30 by setting the gate terminal 2 to zero volts, the power can be released not only through the MOSFET 32 but also through the diode 80. MO SFET 30 can be shut off at high speed.

The overcurrent protection operation is as follows. That is, when the drain current increases, the drain current of the current sensing MOSFET 43 for monitoring the drain current of the power MOSFET 30 increases. As a result, the voltage drop at the resistor 70 increases and the MOSFET 42 starts to turn on. As a result, the MOS FET 31 is turned on, and the voltage of the internal gate 5 of the power MOSFET 30 is reduced (the resistance of SW 1 is reduced). This prevents the drain current of the power MOSFET 30 from becoming excessive. The overheat protection operation is as follows. That is, the chip temperature is below the specified temperature. When the temperature rises, the MOS FET 37 is turned off because the voltage drop of the diode string 81 in which the forward voltage decreases due to the temperature rise decreases. As a result, the MOS FET 36 is turned on, and the state of the latch circuit composed of the MOS FETs 34, 35 and the resistors 62, 63 is inverted. As a result, the internal gate voltage 5 of the MOS FET 30 is reduced (the resistance of SW 1 is reduced). This shuts off the power MOSFET 30.

 In the present embodiment, the overcurrent protection and the overheat protection described above are activated, and the voltage 10 of the gate 10 of the MOS FET 32 is lowered even when the voltage of the internal gate 5 of the power MOSFET 30 is lowered. The feature is that the on-resistance of the MOS FET 32 is increased. As a result, high-speed operation can be achieved without significantly reducing the on-resistance of the switch SW1, which is provided to cut off or limit the drain current of the power MOSFET, such as the MOSFET 31 and the MOSFET 42. There is an effect that the protection circuit can operate. In addition, there is an effect that it is not necessary to flow an excessive gate current.

In the present embodiment, the MOSFET whose source is connected to the source terminal 3, that is, MO SFET 31, MO SFET 42, and MO SFETs 33 to 37 are disclosed in Japanese Patent Application Laid-Open No. 7-58293. By using the disclosed method, i.e., the diodes 91, 89, 90, 88 ', there exists between the drain of the above MOS FET and the drain of the power MOS FET 30. To prevent the operation of the parasitic npn transistor and protect the negative gate voltage, and to prevent the operation of the parasitic npn transistor of the MOS SFET 32 whose source is not connected to the source terminal 3, MO SFETs 39, 40 , Using 3 8. That is, when the external gate terminal 2 becomes negative, the MOS FETs 39 and 40 as SW2 are turned on and the MOS FET 38 as SW3 is turned off. Therefore, MO SFET 3 2 The body voltage 4 becomes the same potential as the gate terminal voltage 2 to prevent the base-emitter of the parasitic npn transistor 29 shown in FIG. 1 from being forward-biased. In the present embodiment, such a negative gate voltage protection has an effect that a leak current from the drain terminal 1 to the gate terminal 2 can be cut off even when the MOS FET 32 is built in for high-speed operation. .

Further, in this embodiment, when the threshold voltages of the MOS FETs 39, 38, and 40 are set to 1 V, for example, the MOSFETs 38, 39 , 40 are all turned off. Therefore, when the gate terminal 2 is near zero volts, the base of the parasitic npn transistor 29 described in FIG. 1 is in an open state or close to an open state. Therefore, the collector-emitter breakdown voltage of the parasitic npn transistor 29 is not the BV ces breakdown voltage (about 70 V) when the base and the emitter are short-circuited, but the BV ces breakdown voltage when the base is open. There is a possibility that the voltage will drop near the ceo breakdown voltage (about 20 to 30 V). Therefore, in this embodiment, when the drain terminal 1 becomes higher in potential than the source terminal 3 and the MOS SFET 40 as the SW 2 is turned on, the gate terminal 2 and the body 4 of the MO SFET 32 are short-circuited. It is. As a result, the withstand voltage between the collector and the emitter of the parasitic npn transistor 29 is set to the BV ces withstand voltage when the base and the emitter are short-circuited (at about 70 V, the drain of the (Same as the source-to-source breakdown voltage). When the breakdown voltage of the diodes 83 and 84 is 10 V, respectively, and the resistance of the resistor 67 is 400 kQ or more, the drain leakage current flowing through the resistor 67 is reduced by the drain voltage. It is cut off to about 20 V, and it can be suppressed to less than l OOA (= (60 V-2 X 10 V) / 400 kΩ) even when the drain voltage is 60 V. Here, diode 84 is used as gate protection for MOSFET 40. Work even.

 Therefore, in the present embodiment, as described in the first embodiment, the intelligent power MOS FET incorporating the protection circuit for improving the reliability by a low-cost process can be operated at high speed, and furthermore, the gate-source can be improved. It has a built-in negative gate voltage protection to prevent the operation of the parasitic element even when the voltage becomes negative.Furthermore, even with such a function, the drain-source breakdown voltage of the power MOSFET does not deteriorate. is there. The diodes and resistors used in this embodiment are preferably formed using a polycrystalline silicon layer used for MOS FET gates so that a parasitic element is not formed.

 This embodiment also has a feature that a high-side switch circuit that drives the load 304 at a high speed by connecting the power MOS built-in power control MOSFET 310 that can be manufactured using an inexpensive process to a source follower can be realized. is there.

(Example 3)

 FIG. 4 shows a portion of the power MOSFET 310 of the control circuit built-in of the semiconductor circuit according to the third embodiment of the present invention. That is, also in this embodiment, only the portion of the control circuit built-in power MOSFET 310 in the embodiment shown in FIG. 1 is shown by a specific circuit. Also, the ground 6 in FIG. 1 is an embodiment corresponding to the case of connecting to the source terminal 3 (connection a), and SW 1 and SW 2 are also shown by specific circuits. In this embodiment, FIG. 3 shows an embodiment in which a diode 90 is used instead of the MSFET 38 used as SW3. This embodiment also shows a case where an overheat protection circuit and an overcurrent protection circuit are incorporated as the protection circuit 21.

In this embodiment, when the voltage of the gate terminal 2 is positive, the voltage of the body 4 of the M〇SFET 32 becomes almost the voltage of the source terminal 3 via the diode 93. Therefore, the difference between the body voltage of the MO SFET 32 and the voltage of the source terminal 3 is likely to be larger than that in the case where the M0 SFET 38 is used. As described in Examples 1 and 2, a high-side switch circuit that drives the load 304 at high speed by connecting the power M 内 蔵 SFET 310 with a source follower that can be manufactured using an inexpensive process. There is a feature that can be realized.

(Example 4)

 FIG. 5 shows a control circuit built-in power MOSFET 3010 of a semiconductor circuit according to a third embodiment of the present invention. That is, also in the present embodiment, only the portion of the control circuit built-in power MOSFET 310 in the embodiment shown in FIG. 1 is shown by a specific circuit. This embodiment is an embodiment corresponding to the case where the ground 6 shown in FIG. 1 is connected to the body 4 of the MOS FET 32 (connection b), and SW 1 to SW 3 are shown by specific circuits. . This embodiment also shows a case where an overheat protection circuit and an overcurrent protection circuit are incorporated as the protection circuit 21.

In this embodiment, the negative gate voltage protection diodes 88, 91 used to prevent the operation of the parasitic npn transistors existing in the MOSFETs 31, 33 to 37 shown in FIG. 3 are used. The figure shows a case in which the third switching means (SW 3), which is the third switching means (SW 3), is used, and the negative gate voltage protection is performed by the same method as that of the MOS FET 32. In this embodiment, the diode 90 is left. This is because the gate of the MOS FET 32 is boosted at a high speed in the normal ON operation of the MOS FET 30 due to the bootstrap effect of the capacitor 25. Therefore, if this bootstrap effect is not expected, diode 90 and capacitor 25 Is unnecessary.

 Also in this embodiment, as described in the first and second embodiments, the load 304 is driven at a high speed by connecting the power source built-in control circuit M〇SFET 310, which can be manufactured using an inexpensive process, to the source follower. The feature is that a high-side switch circuit can be realized.

In addition, the power MOS FET 310 with a built-in control circuit of the present embodiment uses a low on-resistance element as the MOS FET 38 to reduce the drain-source voltage of the MO SFET 38 as shown in FIGS. It can be lower than the anode-cathode voltage of the negative gate voltage protection diodes 88, 91 used in the above. Therefore, even if the voltage of the gate terminal 2 decreases by this voltage, the overheat protection circuit using the MOSFETs 33 to 37 can operate normally. In other words, there is an effect that the operation margin of the gate voltage can be expanded, and the voltage of the internal gate terminal 5 after the overheat protection circuit operates can be made lower than before, so that the ability to cut off the drain current can be increased. There is also the effect. Therefore, there is also a feature that a power switch circuit having a wide operation margin of the gate voltage of the control circuit built-in power MOSFET 310 and having a high drain current limiting effect after the protection circuit operates can be realized.

(Example 5)

FIG. 6 shows a power MOS FET 310 with a built-in control circuit of a semiconductor circuit according to a fifth embodiment of the present invention. That is, also in this embodiment, only the portion of the control circuit built-in power M 0 SFET 310 in the embodiment shown in FIG. 1 is shown by a specific circuit. This embodiment is also an embodiment corresponding to the case where the ground 6 shown in FIG. 1 is connected to the body 4 of the M〇SFET 32 (connection b), and SW 1 to SW 3 are shown by specific circuits. It is. In this embodiment, The case where the overheat protection circuit and the overcurrent protection circuit are incorporated as the protection circuit 21 is shown.

 In the embodiment 5 shown in FIG. 6, the SW 2 is configured using the MO SFET 39 and the MO SFET 40, whereas in the present embodiment, the SW 2 is configured only with the MO SFET 40. This is an example. In the present embodiment, the negative gate voltage protection ability is lower than that of the fifth embodiment, but there is an effect that the area occupied by the protection circuit can be reduced because the MOS FET 39 shown in FIG. 5 is not required. In this embodiment as well, as described in the first and second embodiments, a high-speed circuit for driving the load 304 at a high speed by connecting the power MOSFET 310 with a built-in control circuit, which can be manufactured using an inexpensive process, to the source follower. The feature is that a switching circuit can be realized.As described in the fourth embodiment, the operating margin of the gate voltage of the control circuit built-in MOS FET 310 is wide, and the drain current after the protection circuit operates is reduced. Another feature is that a power switch circuit with a high limiting effect can be realized.

(Example 6)

 FIG. 7 shows a portion of the power MOSFET 310 of the control circuit built-in of the semiconductor circuit according to the sixth embodiment of the present invention. That is, in this embodiment, only the portion of the control circuit built-in power MOSFET 310 in the embodiment shown in FIG. 1 is shown by a specific circuit. This embodiment is an embodiment corresponding to the case where the ground 6 shown in FIG. 1 is connected to the source terminal 3 (connection a), and SW1 to SW3 are shown by specific circuits. Also, in this embodiment, a case is shown in which the overheat protection circuit and the overcurrent protection circuit are incorporated as the protection circuit 21.

In this embodiment, the ground 6 shown in FIG. 1 is connected to the source terminal 3 (connection a), but the body of the M〇 SFETs 31 and 33 to 37 is MO SF Connected to body 4 of ET 32. For this reason, the negative gate voltage protection diodes 88, 91 used in Fig. 1 etc. to prevent the operation of the parasitic npn transistor existing in the MOSFETs 31, 33, 37-37 must be used. Negative gate voltage protection is performed using the third switching means (SW3), the MOS SFET 38, in the same manner as the MOS SFET 32 (a method of short-circuiting between the emitter and base of the parasitic npn transistor). ing. This is the same as the case of the fourth embodiment shown in FIG. In this embodiment, since the sources of the MOS SFETs 31 and 33 to 37 are connected to the source terminal 3, the drain current of the MO SFETs 31 and 33 to 37 does not flow through the MOSFET 38. Therefore, compared to the case of the fifth embodiment shown in FIG. 6, the body 4 of the MO SFET 32 can be easily formed without reducing the ON resistance of the MO SFET 38 (without increasing the area occupied by the element). There is an advantage that it can be controlled. In other respects, in the case of this embodiment as well, as described in Embodiments 1 and 2, the control circuit built-in power M 0SFET 310 that can be manufactured using an inexpensive process drives the load 304 at high speed. This has the effect that a high-side switch circuit can be realized without deterioration of the withstand voltage. Further, as described in the fourth embodiment, the operation margin of the gate voltage of the power MOSFET 310 with a built-in control circuit is wide and the protection circuit is Another feature is that a power switch circuit with a high drain current limiting effect after operation can be realized.

(Example 7)

FIG. 8 shows a seventh embodiment of the semiconductor device according to the present invention. In this embodiment, as shown in the cross-sectional view of FIG. 9, an embodiment in which SW 2 is controlled using the node 7 of the floating p-type diffusion layer 103 c is shown. In this embodiment, when a voltage of about 10 V is applied to the drain terminal 1, the power M 0 SF The depletion layer formed between the p-type diffusion layer 103a, which is the body of the ET30, and the n-type epitaxial layer 102, is designed to reach the floating p-type diffusion layer 103c. The feature is that SW2 is turned on by this. A parasitic diode 92 is formed between the floating node 7 and the n-type epitaxial layer 102, but the withstand voltage of this diode is the same as the drain withstand voltage of the MOSFET 30. It does not matter. In this embodiment, when the withstand voltage of the parasitic diode is set to be equal to the withstand voltage of the drain of the power MOSFET 30, the resistor provided to reduce the leakage current from the drain terminal 1 in FIG. 7 is unnecessary. In the case of this embodiment as well, as described in Embodiment 1, a high-side switch that drives the load 304 at high speed by connecting the power MOSFET 310 with a built-in control circuit that can be manufactured using an inexpensive process to the source follower. The feature is that a switch circuit can be realized.

(Example 8)

 FIG. 10 shows a part of a control circuit-built-in MOS FET 310 of a semiconductor circuit according to an eighth embodiment of the present invention. That is, in the present embodiment, only the portion of the control circuit built-in power MOSFET 310 in the embodiment shown in FIG. 8 is shown by a specific circuit. This embodiment is an embodiment corresponding to the case where the ground 6 shown in FIG. 1 is connected to the source terminal 3 (connection a), and SW1 to SW3 are shown by specific circuits. Also, in this embodiment, a case is shown in which the overheat protection circuit and the overcurrent protection circuit are incorporated as the protection circuit 21.

This embodiment is a circuit in which a parasitic diode 92 formed by an n-type epitaxial layer 102 and a p-type diffusion layer 103c instead of the polycrystalline diode 83 in FIG. 3 is formed. . In this embodiment, as described above, the breakdown voltage of the diode 92 is In this case, the resistor 67 provided for reducing the leakage current from the drain terminal 1 in FIG. 3 and the like is unnecessary when the power MOS FET 30 has the same drain withstand voltage. In this embodiment, as described in the seventh embodiment, when the drain voltage becomes, for example, 10 V or more, the depletion layer formed between the p-type diffusion layer 103a and the n-type epitaxial layer 102 becomes a floating layer. The floating node 7 goes to 10 V to reach the p-type diffusion layer 103 c of the floating (not because of the breakdown of the parasitic diode 92). Therefore, even when the gate terminal 2 and the source terminal 3 have almost the same voltage, the MO SFET 40 is turned on as in the circuit of FIG. 3, and the body 4 of the MO SFET 32 has the same voltage as the gate terminal 2. The degradation of the breakdown voltage between the drain and source due to the parasitic npn transistor can be prevented. Therefore, in the case of this embodiment, as described in the first and second embodiments, the power MOSFET 310 with a built-in control circuit, which can be manufactured using an inexpensive process, is connected to the source follower to drive the load 304 at high speed. It has the feature that a high-side switch circuit can be realized.

(Example 9)

 FIG. 11 shows a ninth embodiment of the semiconductor circuit according to the present invention. In this embodiment, as a means for preventing the body of the MOS FET 29 from becoming floating when the gate terminal 2 and the source terminal 3 have substantially the same voltage in the first embodiment, This is an embodiment in which a resistor 72 is provided between the source and the source terminal 3 to prevent degradation of the drain-source breakdown voltage due to the parasitic npn transistor 29. Therefore, in the case of the present embodiment, it is not necessary to control the SW 2 by the drain voltage to prevent the body of the MOSFET 29 from floating as in the first embodiment.

The value of resistor 72 should be about 5 times larger than the on resistance of SW 2 and SW 3. As a result, in this embodiment as well, as described in the first embodiment, the power MOSFET 310 with a built-in control circuit that can be manufactured using an inexpensive process is connected to the source follower to drive the load 304 at high speed. The feature is that a high-side switch circuit can be realized.

(Example 10)

 FIG. 12 shows a part of a control circuit built-in power MOS FET 310 of a semiconductor circuit according to a tenth embodiment of the present invention. That is, in the present embodiment, only the portion of the control circuit built-in power M 0 S FET 310 in the embodiment shown in FIG. 11 is shown by a specific circuit. This embodiment is an embodiment corresponding to the case where the ground 6 shown in FIG. 1 is connected to the source terminal 3 (connection a), and SW1 to SW3 are shown by specific circuits. Also, in this embodiment, a case where an overheat protection circuit and an overcurrent protection circuit are incorporated as the protection circuit 21 is shown. In this embodiment, since it is not necessary to control the SW 2 by the drain voltage to prevent the body of the MOS FET 29 from becoming floating, the resistors 67 to 70 and the MOS SFETs 40 and 41 in FIG. The diodes 83 and 84 are not required, and instead, the resistor 72 is provided to prevent the body of the MOSFET 29 from floating. As a result, in this embodiment as well, as described in the first and second embodiments, the power MOS SFET 310 with a built-in control circuit, which can be manufactured using an inexpensive process, is connected to the source follower, and the load 304 is connected. The feature is that a high-side switch circuit that can be driven at high speed can be realized.

In this embodiment, when a positive voltage is applied to the gate terminal 2 and the impedance between the body 4 of the MOS FET 32 and the source terminal 3 does not need to be reduced, the M 0 SFET 3 It is also possible to remove 8 is there. (Example 11)

FIG. 13 shows a first embodiment of the semiconductor circuit according to the present invention. In this embodiment, reference numerals 311 and 312 denote the power MOS FETs 310 with built-in control circuits shown in FIGS. 1 and 3 to 8 and 10 to 12, respectively. Also, 304 is a load, 310 is a battery, 311 and 314 are a part of the control circuit, and 316 and 317 are parts of the control circuit built-in MO SFET. Pre-drivers for driving 311, 312 and power MOSFETs 313, 314, and 307 and 308 are input terminals of the pre-driver. This circuit is an H-bridge circuit that uses a control circuit built-in power MOSFET 311 and 312 used as a power switch as an upper arm element. Also in this embodiment, since the power MOS SFETs 311 and 312 with a built-in control circuit are connected to the source follower, the on-resistance of the power MOS SFET 30 is controlled by the pre-driver circuits 316 and 317. It is necessary to drive the gate terminal 2 by boosting it from 5 V to 10 V from the power supply terminal 303 so that the voltage drops sufficiently. In order to turn off the power MOSFETs 311 and 312 with the built-in control circuit, the gate terminal 2 is lowered to ground 302. At this time, it should be noted that as described in the first embodiment, when the control circuit built-in power MO SFETs 311 and 312 are turned off at high speed, the control circuit built-in power MO SFETs 311 and 312 Although the gate terminal 2 is driven more negatively than the source terminal 3, the control circuit built-in MFETSFETs 311 and 312 that can be manufactured using an inexpensive process are used in the first to tenth embodiments. By adopting the circuit configuration shown in (1) and (2), similarly to the case of the high-side switch circuit, there is a feature that the bridge circuit as shown in this embodiment can be realized and can be driven at high speed. (Example 12)

FIG. 14 shows a twelfth embodiment of the semiconductor circuit according to the present invention. This embodiment is an embodiment in which an IGBT 50 is used in place of the power MOSFET 30 shown in FIGS. 1, 3 to 8 and 10 to 12. In FIG. 14, 11 is a collector terminal, 12 is a gate terminal, and 13 is an emitter terminal. The MOSFET 32 is provided for high-speed switching of the IGBT 50 as in the case of Fig. 1, and the IGBT 50 is used instead of the power MOSFET 30 for the power switch. The only difference is that the other circuit configurations are the same. FIG. 15 shows a cross-sectional structure of an IGBT incorporating the protection circuit of the present invention. The difference between Fig. 15 and Fig. 2 is that a p-type substrate 201 is used as the substrate, and a small number of p-type substrates 201 from the p-type substrate 201 to the n-type epitaxial layer 102 acting as the n-type base region. The only difference is that an n-type buffer region 202 having a higher concentration than the n-type epitaxial layer 102 is provided in order to suppress carrier injection. Further, in the case of this embodiment, as is apparent from the cross-sectional structure of FIG. 15 in place of the parasitic npn transistor, between the collector terminal 11 of the IGBT 50 and the drain of the MOS FET 32, as shown in FIG. The parasitic thyristor 52 shown in 4 is formed. Therefore, when a negative voltage is applied to the gate terminal 12 ', the parasitic thyristor 52 is turned on, and a leak current may flow from the collector terminal 11 to the gate terminal 12. In other words, when the IGBT 50 is used instead of the power MOSFET 30, a problem occurs due to the parasitic thyristor 52 instead of the parasitic npn transistor 29, and the countermeasures are taken by the power MOSFET described above. The same method as for 30 can be used. That is, by controlling the body 4 of the MOSFET 32 using the SW 2 and SW 3 shown in FIG. 1 of the first embodiment, the negative gate voltage protection of the IGBT 50 is achieved. When the gate terminals 1 and 2 reach the base 4 floating of the thyristor 52 near the zero port, the effective collector-emitter voltage of the IGBT 50 deteriorates due to the latch-up of the thyristor 52. Is prevented. In other words, even when an IGBT is used like the semiconductor circuit of the present invention described using the power MOSFET in the first embodiment, a completely similar circuit can be configured, and the process cost is low and high-speed operation is achieved. The feature is that a power switch circuit using an IGBT with a built-in control circuit of an emitter follower that protects the negative gate voltage and prevents deterioration of the withstand voltage between the collector and the emitter can be realized.

 Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment.For example, in the above-described embodiment, all the MOS SFETs and IGBTs including the power MOS SFET are described as n-channel type. However, the same effect can be obtained even if all the devices are of the p-channel type, and it goes without saying that many design changes can be made without departing from the spirit of the present invention.

 As is clear from the embodiments described above, according to the present invention, for example, a high-side switch using a power MOSFET or IGBT as a power switch element in which a control circuit such as an overheat protection circuit or an overcurrent protection circuit is built in a self-isolation structure. This has the effect that high-speed operation of switch circuits and bridge circuits can be realized by preventing malfunctions due to parasitic npn transistors and parasitic thyristors.

Claims

The scope of the claims

1. Insulated gate type semiconductor device with built-in control circuit (310), battery (310) and load (304) at least.

The above-mentioned insulated gate semiconductor device with built-in control circuit (310)

N-type first impurity region (102) of the semiconductor substrate, P-type second impurity region (107) in contact with the first impurity region, and N covered by the second impurity region Transistor including a third impurity region of type (109a)

(Power MO S 30) and

A p-type fourth impurity region (104a) in contact with the first impurity region; and n-type fifth and sixth impurity regions (109b) covered by the fourth impurity region. , C), a second transistor (MO SFET 32), a first terminal (1) connected to the first impurity region,

A gate terminal (2) connected to the fifth impurity region (109b) in the second transistor,

A second terminal (3) connected to the third impurity region,

A first switch circuit (SW2) provided between the gate terminal (2) and the fourth impurity region;

A second switch circuit (S W3) provided between the second terminal (3) and the fourth impurity region;

When the voltage of the gate terminal (2) is negative with respect to the second terminal (3), the second switch circuit (SW3) is turned off and the first switch is turned off. The circuit (SW2) is on and

When the voltage of the gate terminal (2) is positive with respect to the second terminal (3), the second switch circuit (SW3) is turned on and the first switch is turned on. The circuit (SW2) is off, When the voltage of the first terminal (1) is higher than a predetermined positive voltage with respect to the second terminal (3), the second switch circuit (SW3) is turned off and the second switch circuit (SW3) is turned off. The switch circuit (SW2) of No. 1 is on, and the insulated gate semiconductor device (310) with the built-in control circuit connects the first terminal (1) to the battery (310), The second terminal (3) is connected to the load (304), and the main current between the first terminal (1) and the second terminal (3) is controlled by the gate terminal (2). A power switch circuit characterized by controlling.

 2. The power switch circuit according to claim 1,

The gate electrode of the first transistor is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and a ground line (6) connected to the second terminal (3);

A protection circuit (21) for detecting the overload state of the first transistor, turning on the third switch circuit, and increasing the source-drain resistance of the second transistor. A power switch circuit further provided.

 3. In the power switch circuit according to claim 1,

The gate electrode of the first transistor of the insulated gate semiconductor device (310) with a built-in control circuit is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and a ground line (6) connected to the fourth impurity region;

The overload state of the first transistor is detected and the third switch is turned on. A power switch circuit, further comprising: a protection circuit (21) for turning on a path and increasing a source-drain resistance of the second transistor.

 4. The power switch circuit according to claim 2, wherein the third switch circuit (SW1) is connected to the insulated gate semiconductor device (310) having the built-in control circuit. A power switch circuit comprising a third transistor (31 or 42) that is turned on by a signal indicating that a load state has been detected.

 5. The power switch circuit according to claim 4,

A first diode (91 or 89) having an anode connected to the gate of the first transistor,

A power switch circuit characterized in that the first diode (91 or 89) is connected in series with the source 'drain path of the third transistor (31 or 42).

 6. The power switch circuit according to any one of claims 1 to 5, wherein the first switch circuit (SW2) is configured such that the voltage of the gate terminal (2) is equal to the voltage of the second terminal (3). ), A fourth transistor (39) that is turned on when it has a negative polarity with respect to

A fifth transistor (40) that is turned on when the voltage of the first terminal (1) is higher than the predetermined positive voltage with respect to the second terminal (3). Power switch circuit.

 7. In the power switch circuit according to claim 6,

The fourth transistor (39) comprises an N-type transistor, and its source / drain path is provided between the gate terminal (2) and the fourth impurity region, and its gate is Be connected to the second terminal (3) A power switch circuit characterized by the following.

 8. The power switch circuit according to claim 6, wherein the fifth transistor (40) has a source and a drain path connected to the gate terminal (2) and the fourth impurity. It consists of an N-shaped transistor provided between the area and

A power switch circuit further comprising a second diode (83) provided between the gate of the fifth transistor (40) and the first terminal (1).

 9. In the power switch circuit according to claim 8,

The second diode (92) is formed by the first impurity region and a P-type seventh impurity region (103c) in contact with the first impurity region. The impurity region is located at a position where a depletion layer formed between the second impurity region and the first impurity region reaches when the predetermined positive polarity voltage is applied to the first terminal (1). A power switch circuit characterized by being formed in a power switch.

 10. The power switch circuit according to any one of claims 1 to 9, wherein the second switch circuit (SW3) includes the second terminal (3) and the fourth impurity region. A power drain path is provided between the gate terminal and the gate terminal, and the gate includes an N-type sixth transistor (38) connected to the gate terminal (2). Switch.

11. The power switch circuit according to any one of claims 1 to 9, wherein the second switch circuit (SW3) is connected between the second terminal (3) and the fourth impurity region. The second switch circuit (SW3) has a diode (92) between the second terminal (3) and the fourth impurity region. Switch circuit.

1 2. The power switch circuit according to claim 2, wherein a resistance element connected between a source and a drain of the second transistor (32).

 (60) A power switch circuit further comprising:

 1 3. The power switch circuit according to claim 2, wherein the gate of the first transistor (30) and the gate of the second transistor (32) A power switch circuit, further comprising a connected capacitor (25).

 1 4. Insulated gate semiconductor device with built-in control circuit (310) and battery (3

0 1) and load (3 0 4)

The above-mentioned insulated gate semiconductor device with built-in control circuit (310)

P-type first impurity region (102) of the semiconductor substrate, N-type second impurity region (107) in contact with the first impurity region, and P-type impurity region covered by the second impurity region. Transistor including a third impurity region of type (109a)

(Power MO S 30) and

An N-type fourth impurity region (104a) in contact with the first impurity region; and a P-type fifth and sixth impurity region (109b) covered by the fourth impurity region. , C), a second transistor (MO SFET 32), a first terminal (1) connected to the first impurity region,

A gate terminal (2) connected to the fifth impurity region (109b) in the second transistor,

A second terminal (3) connected to the third impurity region,

A first switch circuit (S W2) provided between the gate terminal (2) and the fourth impurity region;

A second terminal provided between the second terminal (3) and the fourth impurity region. And a switch circuit (SW3).

When the voltage of the gate terminal (2) is positive with respect to the second terminal (3), the second switch circuit (SW3) is off and the first switch is turned off. The circuit (SW2) is on and

When the voltage of the gate terminal (2) is negative with respect to the second terminal (3), the second switch circuit (SW3) is turned on and the first switch is turned on. The circuit (SW2) is off,

When the voltage at the first terminal (1) is higher than a predetermined negative voltage with respect to the second terminal (3), the second switch circuit (SW3) is turned off and the second switch circuit (SW3) is turned off. The switch circuit (SW 2) of No. 1 is on, and the insulated gate semiconductor device (310) with a built-in control circuit connects the first terminal (1) to the battery (310), The second terminal (3) is connected to the load (304), and the main current between the first terminal (1) and the second terminal (3) is controlled by the gate terminal (2). A power switch circuit characterized in that:

 1 5. In the power switch circuit according to claim 14,

The gate electrode of the first transistor is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and a ground line (6) connected to the second terminal (3);

A protection circuit (21) for detecting the overload state of the first transistor, turning on the third switch circuit, and increasing the source-drain resistance of the second transistor. A power switch circuit further provided.

1 6. In the power switch circuit according to claim 14,

The gate electrode of the first transistor of the insulated gate semiconductor device with a built-in control circuit (310) is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and the ground line (6) connected to the fourth impurity region;

A protection circuit (21) for detecting the overload state of the first transistor, turning on the third switch circuit, and increasing the source-drain resistance of the second transistor. A power switch circuit characterized by comprising:

 1 7. In the power switch circuit according to claim 15 or 16,

The third switch circuit (SW 1) is turned on by a signal indicating that an overload state of the insulated gate semiconductor device (310) with a built-in control circuit is detected. A power switch circuit characterized by comprising (1) or (2).

 1 8. In the power switch circuit according to claim 17,

Further comprising a first diode (91 or 89) having its gate connected to the first transition gate;

A power switch circuit characterized in that the first diode (91 or 89) is connected in series with the source 'drain path of the third transistor (31 or 42).

 1 9. In the power switch circuit according to any one of claims 14 to 18,

The first switch circuit (SW2) is connected to the gate terminal (2). A fourth transistor (39) that is turned on when the second terminal (3) has a positive polarity with respect to the second terminal (3);

A fifth transistor (40) that is turned on when the voltage of the first terminal (1) is higher than the predetermined negative voltage with respect to the second terminal (3). Power switch circuit.

 20. In the power switch circuit according to claim 19,

The fourth transistor (39) is a P-type transistor, and its source / drain path is provided between the gate terminal (2) and the fourth impurity region. A power switch circuit characterized by being connected to two terminals (3).

 21. In the power switch circuit according to claim 19 or 20,

The fifth transistor (40) has an N-type transistor whose source and drain paths are provided between the gate terminal (2) and the fourth impurity region.

A power switch further comprising a second diode (83) provided between the gate of the fifth transistor (40) and the first terminal (1). circuit. '

 2 2. In the power switch circuit according to claim 21,

The second diode (92) is formed by the first impurity region and an N-type seventh impurity region (103c) in contact with the first impurity region. The impurity region is located at a position where a depletion layer formed between the second impurity region and the first impurity region reaches when the predetermined negative voltage is applied to the first terminal (1). A power switch circuit characterized by being formed in a power switch.

2 3. In the power switch circuit according to any one of claims 14 to 22,

The second switch circuit (SW3) has a source / drain path provided between the second terminal (3) and the fourth impurity region, and the gate is connected to the gate terminal (SW3). A power switch circuit comprising a P-type sixth transistor (38) connected to 2).

2 4. In the power switch circuit according to any one of claims 14 to 22,

The second switch circuit (SW3) is connected between the second terminal (3) and the fourth impurity region. The second switch circuit (SW3) is connected to the second terminal. A power switch circuit having a diode (92) between (3) and the fourth impurity region.

 2 5. In the power switch circuit according to claim 15,

A resistance element connected between the source and the drain of the second transistor (32)

 (60) A power switch circuit further comprising:

 2 6. In the power switch circuit according to claim 15 or 25,

The gate of the first transistor (30) and the gate of the second transistor (30)

A power switch circuit further comprising a capacitor (25) connected between the gate of (32) and the gate of (32).

 27. Insulated gate semiconductor device with built-in control circuit, battery and load at least

The above-mentioned insulated gate semiconductor device with built-in control circuit (310)

N-type first impurity region (102) of the semiconductor substrate and the first impurity region A first transistor including a P-type second impurity region (107) in contact with the semiconductor substrate and an N-type third impurity region (109a) covered by the second impurity region

(Power MO S 30) and

A p-type fourth impurity region (104a) in contact with the first impurity region; and n-type fifth and sixth impurity regions (109b) covered by the fourth impurity region. , C), a second transistor (MO SFET 32), a first terminal (1) connected to the first impurity region,

A gate terminal (2) connected to the fifth impurity region (109b) in the second transistor,

A second terminal (3) connected to the third impurity region,

A first switch circuit (SW2) provided between the gate terminal (2) and the fourth impurity region;

A second switch circuit (S W3) provided between the second terminal (3) and the fourth impurity region;

A first resistive element (72) provided between the second terminal (3) and the fourth impurity region;

When the voltage of the gate terminal (2) is negative with respect to the second terminal (3), the second switch circuit (SW3) 'is off and the first switch is turned off. Switch (SW2) is on,

When the voltage of the gate terminal (2) is positive with respect to the second terminal (3), the second switch circuit (SW3) is turned on and the first switch is turned on. The circuit (SW2) is off,

In the insulated gate semiconductor device (310) with a built-in control circuit, the first terminal (1) is connected to the battery (301), and the second terminal (3) is connected to the load (304). ) And the first terminal (1) by the gate terminal (2). ) And the second terminal (3), wherein the main current is controlled.

 2 8. In the power switch circuit according to claim 27,

The gate electrode of the first transistor is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and a ground line (6) connected to the second terminal (3);

A protection circuit (21) for detecting the overload state of the first transistor, turning on the third switch circuit, and increasing the source-drain resistance of the second transistor. A power switch circuit further provided.

 2 9. The power switch circuit according to claim 28, wherein:

The gate electrode of the first transistor of the insulated gate semiconductor device (310) with a built-in control circuit is connected to the sixth impurity region,

A third switch circuit (S W1) provided between the gate electrode of the first transistor and a ground line (6) connected to the fourth impurity region;

A protection circuit (21) for detecting the overload state of the first transistor, turning on the third switch circuit, and increasing the source-drain resistance of the second transistor. A power switch circuit characterized by comprising:

 30. In the power switch circuit according to claim 28 or 29,

The third switch circuit (SW1) is an insulated gate half-type circuit with a built-in control circuit. A power switch circuit comprising a third transistor (31 or 42) that is turned on by a signal indicating that an overload state of the conductor device (310) has been detected.

 31. In the power switch circuit according to claim 30,

A first diode (91 or 89) having an anode connected to the gate of the first transistor,

A power switch circuit characterized in that the first diode (91 or 89) is connected in series with the source 'drain path of the third transistor (31 or 42).

 3 2. In the power switch circuit according to any one of claims 27 to 31,

The first switch circuit (SW2) is connected to a fourth transistor (3) that is turned on when the voltage of the gate terminal (2) is negative with respect to the second terminal (3). 9) A power switch circuit comprising:

3 3. In the power switch circuit according to claim 32,

The fourth transistor (39) is an N-type transistor, and its source / drain path is provided between the gate terminal (2) and the fourth impurity region, and its gate is provided at the gate of the fourth transistor (39). A power switch circuit characterized by being connected to two terminals (3).

 3 4. In the power switch circuit according to any one of claims 27 and 33,

In the second switch circuit, a source / drain path is provided between the second terminal (3) and the fourth impurity region, and the gate is connected to the gate terminal (2). A power switch circuit characterized by comprising an N-type sixth transistor (38) connected to the power supply circuit.

3 5. In the power switch circuit according to any one of claims 27 and 33,

The second switch circuit (SW3) includes a diode switch (92) between the second terminal (3) and the fourth impurity region. .

 3 6. In the power switch circuit according to claim 28,

A power switch circuit further comprising a second resistance element (60) connected between a source and a drain of the second transistor (32).

 3 7. In the switch circuit according to claim 28 or 36,

A power switch further comprising a capacitor (25) connected between the gate of the first transistor (30) and the gate of the second transistor (32). Switch.

 3 8. Insulated gate semiconductor device with built-in control circuit (310) and battery (3

0 1) and load (3 0 4)

The above-mentioned insulated gate semiconductor device with built-in control circuit (310)

The semiconductor substrate is covered with the P-type first impurity region (· 102), the Ν-type second impurity region (107) in contact with the first impurity region, and the second impurity region. A first transistor including a Ρ-type third impurity region (109a)

(Power MO S 30) and

An N-type fourth impurity region (104a) in contact with the first impurity region; and a P-type fifth and sixth impurity region (109b) covered by the fourth impurity region. , C), a second transistor (MO SFET 32), a first terminal (1) connected to the first impurity region, A gate terminal (2) connected to the fifth impurity region (109b) in the second transistor,

A second terminal (3) connected to the third impurity region,

A first switch circuit (SW 2) provided between the gate terminal (2) and the fourth impurity region;

A second switch circuit (SW3) provided between the second terminal (3) and the fourth impurity region;

A first resistive element (72) provided between the second terminal (3) and the fourth impurity region;

When the voltage of the gate terminal (2) is positive with respect to the second terminal (3), the second switch circuit (SW3) is off and the first switch is turned off. The circuit (SW2) is on and

When the voltage of the gate terminal (2) is negative with respect to the second terminal (3), the second switch circuit (SW3) is turned on and the first switch is turned on. The circuit (SW2) is off,

In the insulated gate semiconductor device (310) with a built-in control circuit, the first terminal (1) is connected to the battery (301), and the second terminal (3) is connected to the load (304). ), And the main current between the first terminal (1) and the second terminal (3) is controlled by the gate terminal (2).

 3 9. In the power switch circuit according to claim 38,

The gate electrode of the first transistor is connected to the sixth impurity region,

A third switch circuit (SW1) provided between a gate electrode of the first transistor and a ground line (6) connected to the second terminal (3); When,

A protection circuit (21) for detecting the overload state of the first transistor, turning on the third switch circuit, and increasing the source-drain resistance of the second transistor. A power switch circuit further provided.

 40. In the power switch circuit according to claim 39,

The gate electrode of the first transistor of the insulated gate semiconductor device with a built-in control circuit (310) is connected to the sixth impurity region,

A third switch circuit (SW 1) provided between the gate electrode of the first transistor and the ground line (6) connected to the fourth impurity region.

) When,

A protection circuit (21) for detecting the overload state of the first transistor, turning on the third switch circuit, and increasing the source-drain resistance of the second transistor. A power switch circuit further provided.

 41. In the power switch circuit according to claim 39 or 40,

The third switch circuit (SW1) is turned on by a signal indicating that an overload state of the insulated gate semiconductor device (310) with a built-in control circuit is detected. 31. A power switch circuit characterized by having the following.

 4 2. In the power switch circuit according to claim 41,

A first diode (91 or 89) having the anode connected to the gate of the first transistor,

The source 'drain path of the third transistor (31 or 42) and A power switch circuit characterized in that the first diode (91 or 89) is connected in series.

 4 3. In the power switch circuit according to any one of claims 38 to 41,

The first switch circuit (SW2) is connected to a fourth transistor (3) which is turned on when the voltage of the gate terminal (2) is positive with respect to the second terminal (3). 9) A power switch circuit comprising:

4 4. In the power switch circuit according to claim 43,

The fourth transistor (39) is an N-type transistor, and its source / drain path is provided between the gate terminal (2) and the fourth impurity region. A power switch circuit connected to the second terminal (3).

 4 5. In the power switch circuit according to claim 38 or 44,

In the second switch circuit, a source / drain path is provided between the second terminal (3) and the fourth impurity region, and the gate is connected to the gate terminal (2). A power switch circuit comprising a P-type sixth transistor (38) connected to the power switch circuit.

 4 6. In the power switch circuit according to any one of claims 38 and 44,

The second switch circuit (SW3) has a diode (92) between the second terminal (3) and the fourth impurity region. .

 47. In the power switch circuit according to claim 39,

The transistor is connected between the source and the drain of the second transistor (32). A power switch circuit further comprising a second resistance element (60).

 4 8. In the power switch circuit according to any one of claims 39 and 47,

The gate of the first transistor (30) and the gate of the second transistor (30)

A power switch circuit further comprising a capacity (25) connected between the gate and the gate of (2).

 49. In the power switch circuit according to any one of claims 1 to 48, the first transistor (30) has the first terminal (1) as a drain terminal and the second transistor (3) as the first transistor (30). A power switch circuit characterized in that it is a power MOSFET having a source terminal.

 50. The power switch circuit according to any one of claims 1 to 48, wherein the first impurity region (102) and the first terminal (1) are provided between the first impurity region (102) and the first terminal (1). And an eighth impurity region (202) having the same conductivity type as the first impurity region and having a higher impurity concentration than the first impurity region in contact with the impurity region (102) A power switch circuit, further comprising a ninth impurity region (201) having a conductivity type opposite to that of the first impurity region. '

 51. The power switch circuit according to claim 50,

The first transistor (30) is an insulated gate bipolar transistor having the first terminal (1) as a collector terminal and the second terminal (3) as an emitter terminal. Power switch circuit.