WO1998033213A1

WO1998033213A1 - Method for manufacturing semiconductor device

Info

Publication number: WO1998033213A1
Application number: PCT/JP1998/000346
Authority: WO
Inventors: Seiji Ishikawa; Takaaki Kumazawa; Jun Nakazato
Original assignee: Hitachi, Ltd.
Priority date: 1997-01-29
Filing date: 1998-01-28
Publication date: 1998-07-30
Also published as: JPH10214870A

Abstract

A method for manufacturing a semiconductor device aimed at increasing a yield rapidly by determining management criteria for inspection results, inspection processes, inspection regions, etc., without a delay. The influence of defects generated in trial production on a yield is analyzed for each region of generation of defects and for each productive process and the size of a fatal defect, regions of generation of defects, observation images of the defects, and inspection means are put in order as advance checking items for each productive process. In mass production line, semiconductor devices are inspected based on the advance checking items to increase a yield.

Description

Description Semiconductor device manufacturing method Technical field

The present invention relates to a manufacturing technique for improving a semiconductor device manufacturing yield, and more particularly to a semiconductor device manufacturing method for efficiently managing a semiconductor device manufacturing line and improving the manufacturing yield.

Background art

Semiconductor devices are manufactured by forming a pattern by repeating a film forming process, an exposing process, an etching process, and the like, and stacking these in multiple layers. The processing dimensions of patterns formed on semiconductor devices are fine, and products with dimensions already less than 1 m are widely sold.

In semiconductor devices having such characteristics, defective products are liable to occur if foreign matter is mixed in during the manufacturing process, or if the pattern is chipped or deformed due to a malfunction of the manufacturing device. Therefore, in the field of semiconductor device manufacturing, it is very important to improve the production efficiency by controlling the manufacturing situation and reducing the ratio of defective products, and improving production efficiency.

In general, when a defective product occurs during the manufacture of a semiconductor device, problems are identified by examining the defective portion and the history of processing the defective portion to improve the yield. The history here refers to the processing unit, processing date and time, processing conditions (set value / actual value), the quality of the lot before and after, the monitoring result of the processed equipment, and the like.

As a method of examining a defective part of a defective product, there is a method called a so-called fail bit analysis as disclosed in Japanese Patent Application Laid-Open No. Sho 61-243,378. this Is to analyze the location of the defect in the chip by looking at the position of the bit that does not work, and from the array of defective cells, it is possible to determine where in the stack of layers the defect is Can be calculated. However, fail-bit analysis can be performed only after the semiconductor device wafer processing step is completed and electrical characteristics can be measured. Therefore, the fail bit analysis has a disadvantage that even if a product defect occurs during the manufacturing process, the defect cannot be detected until the wafer processing process is completed. ,

Therefore, it is effective to insert an inspection process during manufacturing to detect foreign matter and defects in the appearance of patterns, analyze the state of occurrence, and take early measures. This method is described in detail in JP-A-3-44054. This is to improve the yield by grasping the characteristics of the process in which many foreign particles and appearance defects occur and the pattern of their occurrence from the result of the foreign particle appearance inspection.

However, in the above-mentioned conventional technology, in what process the foreign matter appearance inspection and the like are performed, which area on the wafer is inspected, with what accuracy (sensitivity) the inspection is performed, what kind of standard (management standard) ) Needs to be determined. After setting the predetermined inspection conditions and starting mass production of the semiconductor devices, the optimum inspection conditions are determined while changing the inspection conditions as needed, so that the efficiency required until the data necessary for the analysis is collected. Good inspection is not possible.

Recently, it has been required to manufacture new semiconductor devices at an early stage and at a low cost, and inspection standards must be established earlier than ever. Delays in establishing inspection standards will affect production yields and increase costs. In general, the period for manufacturing a semiconductor device usually takes several tens of days. Therefore, according to the above-mentioned conventional technology, it takes a considerable number of days from the start of production to the establishment of an inspection standard. An object of the present invention is to improve the manufacturing yield by effectively inspecting a semiconductor device being manufactured. Disclosure of the invention

According to the present invention, in order to achieve the above object, necessary inspection information is acquired during a prototype period before mass production of semiconductor devices is started, and semiconductor devices are mass-produced using the inspection information. In other words, by analyzing the area where defects occurred in the prototype and the impact on the yield for each generation process, for example, pre-check the size of fatal defects, the generation area, observation images, and inspection means for each defect generation process In mass production, inspections are performed based on the pre-check items to determine the management criteria for inspection results, inspection process, inspection area, etc. in semiconductor device manufacturing without delay, and improve yield. Do it quickly. Specifically, a step of manufacturing a semiconductor device on a first manufacturing line, a step of inspecting the semiconductor device by an inspection device provided on the first manufacturing line, and an inspection result of the semiconductor device Generating manufacturing line management information from the following; setting an inspection device on a second manufacturing line based on the generated manufacturing line management information; manufacturing a semiconductor device on the second manufacturing line; The above object is achieved by including a step of inspecting a semiconductor device manufactured on the second manufacturing line by an inspection device set based on the manufacturing line management information.

As a result, based on the inspection information obtained during the prototyping period, inspection standards for mass production, for example, locations to be inspected particularly on a wafer can be effectively set without delay, so that stable production at a mass production site can be performed quickly. It can be realized, and the yield can be improved.

The present invention will be described more specifically. A step of manufacturing a semiconductor device on a first manufacturing line, and an appearance / foreign matter inspection provided on the first manufacturing line Detecting a defect on a wafer forming the semiconductor device by the device; detecting an electrical characteristic of a chip of the wafer forming the semiconductor device by a probe inspection device provided on the first manufacturing line; A step of determining a chip having a defect from the detection result of the external appearance / foreign matter inspection apparatus; and a step in which electrical characteristics are defective among the chips determined to have the defect based on the detection result of the probe inspection apparatus. Calculating the rate at which the ratio becomes less than a predetermined value, and calculating the inspection frequency of the wafer on which the processing of the step at which the rate becomes a predetermined value or more is completed in the second manufacturing line. The above object is achieved by including a step of manufacturing a semiconductor device at a frequency equal to or higher than the inspection frequency of a completed wafer.

As a result, it is possible to judge a process that is likely to cause a defective product due to a defect before mass production starts, and a relatively large number of wafers processed in the relevant process are sampled and inspected. The generation can be suppressed and the yield can be improved.

Similarly, a step of manufacturing a semiconductor device on a first manufacturing line; a step of detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line; Detecting the electrical characteristics of a chip of a wafer forming the semiconductor device by using a probe inspection device provided in the first manufacturing line; and a detection result of the appearance / foreign matter inspection device and the probe. Calculating the correlation between the number of defects and the yield based on the detection result of the inspection device; and determining the management criteria of the inspection device provided in the second manufacturing line by determining the number of foreign substances whose yield is within a predetermined value. Setting a semiconductor device on the second manufacturing line; and managing the semiconductor device manufactured on the second manufacturing line by an inspection device that has set the management standard. If Sonaere and can improve walking Tomah Li can be set to effective number of foreign matters to be managed by the inspection apparatus before starting mass production. In this case, the appearance / foreign matter inspection apparatus determines a size of a defect on a wafer, calculates a correlation between the number of defects and a yield for each predetermined defect size, and provides an inspection apparatus capable of detecting the defect size. It is preferable to set the number of defects for each defect size for setting the yield to be within a predetermined value as a control standard of the set inspection apparatus, which is set in the second production line.

Also, the appearance / foreign matter inspection apparatus determines a type of a defect on a wafer, calculates a correlation between the number of defects and a yield for each predetermined defect type, and provides an inspection apparatus capable of detecting the type of the defect. It is preferable to set the number of defects for each type of defect for which the yield is within a predetermined value as a management standard for the set inspection apparatus.

Similarly, a step of manufacturing a semiconductor device on the first manufacturing line, and detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line. Calculating the defect occurrence density on the wafer from the detection result of the appearance / foreign matter inspection device, so that the inspection device provided in the second manufacturing line inspects an area where the defect occurrence density is equal to or more than a predetermined value. Setting, manufacturing a semiconductor device on the second manufacturing line, and inspecting an area of the set semiconductor device with an inspection device provided on the second manufacturing line. For example, since the area on the wafer to be inspected by the inspection apparatus can be set before mass production starts, the area where defects are likely to occur can be effectively managed, and the yield can be reduced without lowering the throughput. It is possible to improve the.

In this case, the appearance / foreign matter inspection apparatus determines the size of the defect on the wafer, calculates the defect occurrence density on the wafer for each predetermined size, and the defect occurrence density of any one of the defect sizes is equal to or more than a predetermined value. In this case, it is preferable to set an inspection device capable of detecting a defect size that is equal to or larger than the predetermined value in the second production line. Further, the appearance / foreign matter inspection apparatus determines the type of the defect on the wafer, calculates the defect occurrence density on the wafer for each predetermined defect type, and determines whether the defect occurrence density of any of the defect types is a predetermined value. In this case, it is preferable to set an inspection apparatus capable of detecting the type of the defect having the predetermined value or more in the second production line.

According to another aspect of the present invention, a step of attaching a defect of a predetermined size to the shape of each step in the process of manufacturing a semiconductor device and simulating a subsequent manufacturing process; and attaching the defect. A step of storing a connection relation of each part constituting the simulated shape; a connection relation of each of the stored parts; and a connection relation of each part constituting the simulated shape without generating a defect. A step of judging an object having an inconsistent connection relationship as abnormal; and setting an inspection apparatus capable of detecting a defect of a predetermined size for a step judged as abnormal by the simulation, and The above object can be achieved by including steps for manufacturing a conductor device. As a result, all phenomena can be simulated before mass production starts, and by predicting and managing phenomena that become defective due to the attachment of defects, the yield at mass production bases can be improved.

In this case, it is preferable that the defect attachment positions are made different from each other and simulated, and the inspection area of the inspection apparatus is set so as to inspect the attachment position determined as abnormal.

In addition, it is preferable to simulate the defects with different sizes, and to set an inspection apparatus capable of detecting the size of the defects in a process determined as abnormal. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a system diagram of the present invention, and FIG. 2 is an operation form of the present invention. FIG. 3 is a diagram showing an example of information obtained from the appearance / foreign matter inspection device, FIG. 4 is a diagram showing coordinates on a wafer, and FIG. FIG. 6 is a diagram showing an example of information obtained from a probe inspection apparatus, FIG. 6 is a diagram showing an example of information on a wafer, FIG. 7 is a diagram showing an established PF for each process, and FIG. Fig. 8 shows the established PF for each process, Fig. 9 shows the correlation between yield Y and established Y, and Fig. 10 shows the correlation between yield Y and established Y. FIG. 11 is a flowchart showing an example of an operation mode of the present invention. FIG. 12 is a diagram showing a problem occurrence situation for each process, and FIG. FIG. 14 is a flowchart showing an example of an operation mode of the present invention. FIG. 14 is a correlation diagram between the yield Y and the number N of defects, and FIG. FIG. 15 is a flow chart showing an example of an operation mode of the present invention. FIG. 16 is a view showing a defect occurrence region on a wafer. FIG. 17 is a defect chart on a wafer. FIG. 18 is a diagram showing information on the generation area, FIG. 18 is a diagram showing an appearance foreign matter inspection device of the present invention, and FIG. 19 is a diagram showing an example of a display screen of the present invention; FIG. 20 is a flowchart showing an example of an operation mode of the present invention, FIG. 21 is a diagram showing an example of a simulation result of the present invention, and FIG. FIG. 23 is a diagram showing information on a simulation result, FIG. 23 is a diagram showing information on a simulation result of the present invention, FIG. 24 is a system diagram of the present invention, and FIG. FIG. 4 is a flowchart showing an example of an operation mode of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a system diagram showing the concept of the present invention. Figure 1 consists of the first stage of prototype production, which establishes the optimal manufacturing conditions for the designed device, and the second stage of mass production, which is premised on actual sales as a product. Prototype 1 and mass production 2 may be performed on the same line, or may be performed on different lines. However, there may be some overlap in time. It is natural that the prototype 1 is performed before the mass production 2.

Prototype 1 consists of various types of manufacturing equipment 15 that performs processes such as film formation, exposure, and etching on the input wafer, and a quality inspection device 3 (for example, wafers) that inspects the quality of the wafers processed by the manufacturing equipment. Foreign matter / visual inspection equipment 4) for inspecting defects or foreign matter on the surface, probe inspection equipment 5 for inspecting the electrical characteristics of wafers after all wafer processing steps have been completed, and results of quality inspection equipment 3 (foreign matter) Check item generation station 9 that collects the appearance inspection 4 results and manufacturing results (probe inspection 5 results) to generate the necessary inspection information, and accumulates the inspection information generated by the check generation item station 9 It consists of database 10.

The mass production base 2 includes various manufacturing apparatuses 15 for performing processes such as film formation, exposure, and etching on the input wafers, and a quality inspection apparatus 3 for inspecting the quality of wafers processed by the manufacturing apparatuses (for example, wafers). Foreign matter / visual inspection equipment 4) for inspecting the above defects or foreign matter, probe inspection equipment 5 for inspecting the electrical characteristics of wafers after all wafer processing steps are completed, and inspection information generated in prototype 1 are stored. It is composed of a database 11 and a guide station 12 for outputting a management standard, a process to be inspected, a place on a wafer to be inspected, and the like from the inspection information stored in the database.

The database 10 of the prototype 1 and the database 12 of the mass production base 2 are connected via a communication line 14. The databases provided for the prototype 1 and the mass production base 2 are not necessarily required. There is no problem as long as the guidance station 12 of the mass production base outputs necessary information based on the inspection information generated in the step 9. For example, the databases of the prototype 1 and the mass production base 2 may be integrated, or the information of the prototype 1 may be transferred to the mass production base 2 via a storage medium.

Next, an example of managing the mass production site 2 based on the inspection information (process to be inspected) acquired in the prototype 1 will be described.

Fig. 2 is a flowchart from the acquisition of inspection information (process to be inspected) in prototype 1 to the application of the inspection information to mass production 2.

First, in prototype 1, a semiconductor device is manufactured using various manufacturing apparatuses 15 (step 101).

The quality inspection device 3 acquires quality information from the wafer being manufactured and transmits it to the check item generation station 9 (step 102). In the present embodiment, the defect // "on the wafer and / or the number of foreign substances are acquired by using the foreign substance / visual inspection apparatus 4.

As shown in Fig. 3, the inspection results of the foreign matter / visual inspection device 4 are: product type, process name, lot number, wafer number, defect coordinates (x, y), defect type, defect size, observation image, It includes items such as defect occurrence sites. FIG. 3 shows information on the wafer number 1 stored in the lot number L001 of the semiconductor device HM001, and after the processing in the process P1, the defect coordinates (100, 002) are shown. (0 0) indicates that a defect of defect type A and defect size 10 was detected. However, the type and size of the defect are not necessarily required, and it is sufficient that the presence or absence of a defect can be determined. Here, the defect coordinates are, as shown in FIG. 4, set parallel (X-axis 22) and perpendicular (Y-axis 23) with respect to the flat part (referred to as orientation flat 21) of wafer 20. It is. However, this is only an example, and other coordinate systems may be used, and even if there is no orientation flat on the wafer itself, it is sufficient if the coordinate system is described in a coordinated manner. On the other hand, the probe inspection device 5 acquires the electrical characteristics of each chip from the wafer and sends it to the check item generation station 9 (step 103). As shown in FIG. 5, the inspection result of the probe inspection device 5 includes the product name, the slot number, the wafer number, the chip coordinates (m, n), and information on the quality of the corresponding chip. Here, the chip coordinate means the chip position on the wafer. FIG. 5 shows information on the wafer number 1 stored in the lot number L001 of the semiconductor device HM001, and the pass / fail status of each chip after the process P1 is indicated by “1” and “0”. ". For example, for the chip at the chip position (1,3), "1" is displayed, indicating that the chip is defective.

Next, the check item generation station 11 uses the inspection result of the foreign matter / visual inspection apparatus 4, information on the chip layout of the wafer stored in advance, and equations (1) and (2) to determine on which chip the defect is located. It is determined whether there is (Step 104). The information on the chip layout of the wafer may include information on the chip horizontal width XW, the chip vertical width YL, the number of horizontal chips, and the number of vertical chips as shown in the product type information table 30 shown in FIG. It should be noted that the present invention is not limited to the equations (1) and (2), but it is only necessary to be able to determine which chip has a defect detected by the foreign matter / appearance detection device 4. The calculated chip coordinates (m ′, n ′) must correspond to the coordinates of the probe inspection device 5.

m '= [x / XW] + 1 ... Equation (1) n' = [y / YL] + 1 ... Equation (2)

(m ', n'): chip coordinates

(x, y): defect coordinates

[X] indicates the largest integer not exceeding X.

Next, the chip coordinates (m ', n') with the defect determined in step 1 ), And the probability PF that a chip having a defect becomes a defective product is calculated by using the determination result of good / bad for each chip (m, n), which is the detection result of the probe inspection device 5, and Equation (3). (Step 105). The calculation of the probability PF that a chip having a defect becomes a defective product is performed on wafers inspected in the same process in the same product type.

P F = (number of defective chips in defective chips) / (number of defective chips)

Formula (3) By this, a chip failure rate Daraf 40 per process as shown in FIG. 7 can be created. Here, the horizontal axis 41 indicates the process, and the vertical axis 42 indicates the probability PF of a defective chip becoming a defective product. In this case, the value of PF in process P4 is close to 1.0. This indicates that if a defect occurs, the probability of becoming a defective chip is high. Note that, without preparing the chip failure rate graph 40 for each process shown in FIG. 7, the failure occurrence table 50 shown in FIG. Should be recorded as PF

Next, the yield Y is defined by equation (4), and a correlation diagram 70 between the established PF on the same wafer and the yield Y as shown in FIG. 9 is created, and from these plots The linear regression equation 73 is obtained (step 106).

Y = (number of good chips) / (number of target chips) ... Equation (4) In the check item generation step 9, the information on the established PF and yield Υ is analyzed as shown in Fig. 10 Record as Table 90. In this analysis result table 90, the product name, the process name, the lot number, the wafer number, and PF and Y are included.

As described above, the inspection information required at the mass production site 2 in the prototype 1 (PF value of each process shown in Fig. 8, established PF shown in Fig. 10 and yield) (Correlation information with Y).

Next, at the mass production site 2, the guidance station 12 determines the inspection process and the inspection conditions based on the already acquired established PF, the established PF and the correlation between the yield Y (step 107). In other words, at the guidance station 12 of the mass production base 2, the desired yield is set using FIG. 10, and the corresponding established PF is calculated from the linear regression equation 73, and the established PF is calculated. The manufacturing equipment in the above processes will be managed mainly. Specifically, the inspection frequency of the inspection device or the inspection area is increased for a process having an established PF equal to or higher than a predetermined value.

By increasing the inspection frequency and / or the inspection area of the inspection equipment and inspecting processes that have a large effect of causing a defective chip due to defects (processes with a large established PF), defects can be prevented. Since it is possible to manage a manufacturing apparatus that performs the process, the number of defective chips due to defects can be reduced and the yield can be improved.

Next, Fig. 11 shows another example of extracting the process to be inspected from the inspection information collected in prototype 1.

First, in prototype 1, a semiconductor device is manufactured using various manufacturing apparatuses 15 (step 201).

Next, if a problem occurs during manufacturing, the process and the type of the problem are registered in the check item generation station 9 and the number of occurrences is recorded (step 202). Here, the type of problem refers to a problem due to a device structure or a problem due to a manufacturing apparatus. Fig. 12 shows an example of stored data. (1) This means that the chip width XW and chip height YW are used in the following equations (1) and (2). When drawing a diagram showing a wafer as shown in FIG. Number and the number of horizontal chips are required. In many cases, as shown in Fig. 4, the chip arrangement is such that the chips are processed for each row. The numbers are different. Therefore, it is better to specify an area that is not actually processed in the area enclosed by the number of vertical chips and the number of horizontal chips. Problems caused by the device structure include, for example, a large difference in level of the underlying layer, which makes it difficult to focus at the time of exposure depending on the location, and that a desired pattern cannot be processed. In such a case, it is necessary to closely observe the deviation from the desired shape and take measures. Therefore, observation using SEM is preferable. The problem caused by the manufacturing apparatus is, for example, that foreign matter is generated from the apparatus and the foreign matter adheres to the wafer and cannot be processed into a desired shape. Unlike problems caused by the device structure, it is not known when a device failure will occur, so it is necessary to increase the inspection frequency and quickly detect that a device failure has occurred.

Next, in the guidance station 12 of the mass production base 2, based on the accumulated data, a setting is made so as to focus on the processes in which the number of times of occurrence of the problem is equal to or more than a predetermined number (step 203).

For example, if there are many problems due to the device structure, manage them with a SEM visual inspection device with good inspection sensitivity, and if there are many problems due to the manufacturing equipment, manage them by increasing the inspection frequency (step 204). .

In this way, if processes that are likely to cause problems from the start of mass production are managed using the most appropriate inspection equipment according to the type of problem, the same problem that occurred in prototype 1 can be discovered early, and the yield can be reduced. Can be improved.

In addition, by associating this information with the area on the wafer to be inspected (the area where the problem occurred) and the inspection sensitivity required for the inspection equipment, the inspection can be effectively performed in a part of the wafer, so that throughput is reduced. The yield can be improved without lowering the yield.

Next, an example of acquiring inspection information (conditions to be inspected) in prototype 1 and applying the inspection information to mass production 2 will be described with reference to FIG. In FIG. 13, steps 301 to 303 are the same as those in FIG.

In FIG. 13, in step 304, the check item generation step 9 is based on the inspection result of the foreign matter / visual inspection device 4 and the inspection result of the probe inspection device 5, as shown in FIG. Then, a correlation diagram 60 between the number N of foreign matters and the yield Y is created, and a linear regression equation 73 is obtained from these plots. Note that the yield Y is calculated using the above equation (4).

As described above, the prototype 1 generates the information (correlation information between the number N of foreign particles and the yield Y shown in Fig. 14) required at the mass production site 2.

Next, at the guidance station 12 of the mass production base 2, the inspection conditions are determined based on the correlation between the number N of foreign particles already obtained and the yield Y (Step 305).

In other words, at the mass production base 2, the desired yield is set using FIG. 14 and the number N of corresponding foreign substances is calculated from the linear regression equation 63. The manufacturing apparatus is managed so as not to generate the above foreign matter. In this case, it is desirable to add the sensitivity of the inspection device used in prototype 1 as information and to perform inspection with the same sensitivity as prototype 1.

If the conditions (management standards) to be controlled in each process and the power before mass production are known, stable mass production can be performed at an early stage and the yield can be improved.

For example, if foreign matter having a size of about a pattern processing dimension is generated at the time of film formation by the foreign matter / visual inspection apparatus 4, the management of the film forming apparatus is strict. In addition, when the gate processing accuracy is poor and the desired shape is not obtained, and the desired transistor characteristics cannot be obtained, it is necessary to control the shape after the gate processing. In this case, even a difference of about 110 in the processing dimension may greatly affect the characteristics. Next, an example of acquiring inspection information (area to be inspected) in prototype 1 and applying the inspection information to mass production 2 will be described.

Fig. 15 is a flowchart from the acquisition of inspection information (inspection area) in prototype 1 to the application of the inspection information to mass production base 2. Steps 401 to 402 are the same as those shown in FIG. 2, and a description thereof will be omitted.

In FIG. 15, as shown in FIG. 16, the defect position 101 is spotted on the area indicating the wafer from the inspection result during the manufacture of the prototype 1 (detection result of the foreign matter / visual inspection device 4) ( Step 4 0 3). At this time, J inspection results for a plurality of wafers performed in the same process may be superimposed. As shown in FIG. 16, an area in which the position of a defect is spotted on a region indicating a wafer is referred to as a defect map 100. A virtual mesh 102 is drawn on the defect map, and a number (p, q) is assigned to each mesh. Which mesh each defect belongs to is determined in the same manner as in equations (1) and (2) (step 404). Where L is the mesh pitch.

p = [x / L] + 1 ... Equation (5) q = [y / L] + 1 ... Equation (6) From the results of Equations (5) and (6), the number of defects N (p , Q) (step 4 05). In this case, as shown in FIG. 16, the process name 103 and the defect type 104 may be indicated together. Check item generation station 9 records this result in the format shown in Fig. 17. In FIG. 17, a defect map table 110 records a product name, a process name, a defect type, and a defect-prone area.

Inspection information is acquired in prototype 1 as described above.

Next, at the guidance station 12 of the mass production base 2, an inspection area is set based on the above-described inspection information (step 406). That is, equation (7) , A constant threshold D is set, and an area that satisfies the relationship of equation (7) is checked. Here, a defect map may be created for each defect type. L is arbitrary, but is preferably about 1Z10, which is the chip width XW. D is preferably 2 to 3 times the average defect density per sheet.

N (p, q) / (LXL x J)> D ... Equation (7) Since the area (P, q) that satisfies Equation (7) has a high defect generation density, it is necessary to suppress the generation of defects in that area. If this is the case, the occurrence of defects on the entire wafer can be suppressed, and the yield can be improved. In particular, when the prototype 1 and the mass production base 1 are on the same production line, defects caused by the production equipment can be suppressed, and the yield can be greatly improved.

The area to be inspected described so far is provided to an inspection apparatus 140 as shown in FIG. The inspection device 140 includes a data interface 144, a control unit 142, an inspection stage 144, a detection unit 144, a man-machine interface 144, and a display unit 146. Based on the area (p, q) to be inspected received by the data interface 141, the control unit 142 calculates the stage control amount and controls the inspection stage 143. As a result, the inspection device 140 automatically inspects the area (P, q) to be inspected. Further, it is preferable that the inspection apparatus 140 inspects a predetermined number of points on the wafer in addition to the area (p, q) to be inspected. As a result, the wafer can be inspected uniformly, and a partial area on the wafer can be inspected with emphasis.

As shown in Fig. 19, the display area 1 46 displays the inspection area 1 5 1 and the defect detection position 1 5 2 in the guidance screen 1 50, and detects it during the prototype 1 in the relevant inspection area. It is preferable to display the image 153 of the detected defect and the image 154 of the defect detected in the mass production 2 together. As a result, the defect image detected during prototype production is compared with the defect image detected during mass production, and it is generated in mass production. It can be determined whether the defect was experienced during prototyping.

As described above, the inspection device 140 has high inspection efficiency because the area to be inspected is previously determined for each product type, process, and defect type.

Next, FIG. 20 shows an example in which the process to be inspected at the mass production site 2 is determined based on the inspection result during the production of the prototype 1 during the production.

First, after the layers corresponding to each photomask have been formed in prototype 1, a virtual defect is generated by a cross-sectional shape simulator, and after the defect occurs, a normal manufacturing process is performed to determine whether the device shape is normal. (Step 501). Defects to be generated are handled at various defect sizes and defect locations. Sectional shape simulators that generate virtual defects (foreign matter) are already commercially available and are easy to implement. For example, there is PRA D I S E W O R L D of NTT FANET SYSTEMS CO., LTD. The method of assigning the parameter of the defect size is 1 to 2, the same, 3 to 2, and 2 times the minimum processing line width of each layer. The attachment position is randomly generated in the simulated area. Let S F be the number of occurrences here.

Next, a method of determining the normal Z abnormality of the device shape will be described.

A simulated normal shape is prepared in advance without generating a defect, and the connection relation of each part is recorded (step 502). This can be recorded by assigning a serial number to each part and linking the two parts as a set.

On the other hand, after a defect is generated and simulated, the connection relation of each part is recorded (step 503). Here, the connection with the defect is omitted.

Next, comparing the connection relationship at the time of the defect occurrence with the connection relationship of the normal shape, if the connection at the time of the defect occurrence is different from the connection at the normal shape, it is determined that an abnormality has occurred in the shape ( Step 5 0 4). An example of a simulation See Figure 21. In Fig. 21, a defect 122 is generated on the normal site 1 2 1, and as a result, the site 123 is split into the site 123 and the site 124, and a new site 122 and a new site are generated. Here is an example where 1 24 concatenations are generated. Figure 22 shows the connection in this case. In FIG. 22, the connection relation at normal time is (121, 123), and the connection relation at the time of defect attachment is (122, 123) and (122, 124). At check item generation station 9, the connection relationship shown in FIG. 22 is compared to determine that a shape abnormality has occurred.

In this way, the number of occurrences AF of the shape abnormality is determined, and the abnormality occurrence rate AP is calculated using the equation (8). That is, the abnormality occurrence rate AP is simulated for each layer and each defect size (step 505).

A P = AF / SF ... Equation (8) The check item generation station 9 records the result as a simulation result table 130 as shown in FIG. In FIG. 23, the vertical 13 1 is the layer, the horizontal 13 2 is the defect size, and the corresponding AP is recorded in each cell 1 33.

Inspection information is acquired in prototype 1 as described above.

Next, at the guidance station 12 of the mass production base 2, inspection conditions are set based on the above-described inspection information (step 506). In other words, if the desired yield Y 0 is set, and there are n layers listed on the vertical axis in FIG. 23, the process having 1-AP less than the n-th root of Y 0 will be emphasized. inspect. Specifically, it is managed by an inspection device that can detect the defect size for the relevant process. This means that if the n-th layer AP is written as AP (n), Y 0 is

Y 0 = (1-AP (1)) (1-AP (2))

(1-AP (n))

… Write equation (9), and the nth root of Y 0 and 1—AP (i) (where i is a number from 1 to n) The fact that 1-AP (i) is smaller than that indicates that there is a higher probability that a defect will occur. Therefore, it is necessary to manage foreign substances larger than the size that would cause a problem in the performance of the product by simulation or the like.

As a result, it is possible to grasp how large a defect should be managed in each layer, so that stable mass production can be performed early and the yield can be improved. In addition, since various problems that may occur at the mass production base can be considered in advance by simulation, unexpected unexpected problems can be prevented.

Finally, a more specific example is shown below.

For example, in Fig. 21, a simulation was performed assuming a failure caused by the device, and a simulation result was obtained in which a foreign substance of, for example, 1 μπι size caused a problem in product performance in the contact hole forming process. If so, the result is registered in the pre-check item data base 10. The contents to be registered are the assumed failure (whether due to the device or the device structure), the process name, the size of the foreign material in question, the shape obtained by simulation and the image ID indicating the shape, and Phenomenon, area to be inspected. However, in the case of simulation, it is often not possible to obtain information on a region to be inspected on a wafer. This data is copied to the pre-check database 11 to generate a pre-check list. The pre-check list specifies the type of inspection based on the assumed failure. Here, a defect due to the device is assumed, so a foreign substance inspection is performed. The phenomenon is a non-opening of the contact hole, and the management size is, for example, 1 μπι. It also manages image IDs so that simulation shapes can be searched. If no information is available on the area to be inspected, the entire wafer should be inspected. This pre-checklist at Guidance Station 1 2 1 Based on 3 above, the contents such as inspection type (foreign matter inspection), management standard (foreign matter size 1 ^ πι or more), inspection process (for contact hole formation process), and inspection location (for the entire wafer) are specified.

In addition, based on the actual cases, the detected means, phenomena, size, image ID, location where they occurred, etc. are registered in the pre-check item database 10. Based on this information, a preliminary checklist 13 is generated. In this case, since the short circuit between wirings was found at the chip position (12, 13) (13, 14) by SEM, the guidance station instructs to inspect the corresponding process and the corresponding location by SEM. .

FIG. 25 shows the flow of this processing. Whether this is a simulation or an actual case, if registered as a pre-check item, the subsequent processing is the same.

In the example described so far, the check item generation station 9 performs the analysis based on the inspection result.However, the check item generation station 9 simply collects the inspection results, and the guidance station 12 performs all the analysis. There is no problem to do. Industrial applicability

As described above, according to the present invention, based on the inspection information acquired during the trial production period, the inspection standards at the time of mass production can be effectively set, so that stable production at the mass production base can be realized early and the semiconductor It can be used in equipment manufacturing lines to improve yield.

Claims

The scope of the claim; manufacturing the semiconductor device on the first manufacturing line;

Inspecting the semiconductor device with an inspection device provided on the first manufacturing line;

Generating production line management information from the inspection result of the semiconductor device;

Setting an inspection device in a second production line based on the generated production line management information;

Manufacturing a semiconductor device on the second manufacturing line; and inspecting the semiconductor device manufactured on the second manufacturing line by an inspection device set based on the manufacturing line management information. And a method of manufacturing a semiconductor device.

. Manufacturing a semiconductor device on a first manufacturing line;

A step of detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line;

A step of detecting electrical characteristics of chips on a wafer forming the semiconductor device by a probe inspection device provided on the first manufacturing line; and determining a chip having a defect from the detection result of the appearance / foreign matter inspection device. Steps

Calculating, from the detection result of the probe inspection device, a ratio of the electrical characteristics of the chip determined to have the defect to be defective; and the ratio is equal to or more than a predetermined value in the second manufacturing line. Manufacturing the semiconductor device by setting the inspection frequency of the wafers for which the processing of the process has been completed to be equal to or higher than the inspection frequency of the wafers for which the processing of the process for which the ratio is less than the predetermined value has been completed. A method for manufacturing a semiconductor device.

. Manufacturing a semiconductor device on a first manufacturing line;

Detecting electrical characteristics of chips on a wafer forming the semiconductor device by a probe inspection device provided on the first manufacturing line; detecting results of the appearance / foreign matter inspection device and detection results of the probe inspection device; Calculating the correlation between the number of defects and the yield from:

Setting a management criterion of the inspection device provided in the second production line to the number of foreign substances whose yield is within a predetermined value;

Manufacturing a semiconductor device on the second manufacturing line, and managing the semiconductor device manufactured on the second manufacturing line by an inspection device that has set the management standard. A method for manufacturing a semiconductor device.

The appearance / foreign matter inspection apparatus determines a size of a defect on a wafer, calculates a correlation between the number of defects and a yield rate for each predetermined defect size, and provides an inspection apparatus capable of detecting the defect size to the second type. 4. The manufacturing method of a semiconductor device according to claim 3, wherein the number of defects for each defect size whose yield is within a predetermined value is set as a management criterion of the set inspection apparatus. Method.

5. The appearance and foreign matter inspection device determines the type of defect on the wafer,

A correlation between the number of defects and the yield is calculated for each predetermined defect type, an inspection device capable of detecting the type of the defect is set in the second manufacturing line, and the yield is set as a management standard of the set inspection device. 5. The method for manufacturing a semiconductor device according to claim 3, wherein the number of defects is set for each defect type within a predetermined value.

6. manufacturing semiconductor devices on a first manufacturing line; A step of detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line;

Calculating the defect occurrence density on the wafer from the detection result of the appearance / foreign matter inspection device;

Setting an inspection apparatus provided in the second manufacturing line to inspect an area where the defect occurrence density is equal to or more than a predetermined value;

A step of manufacturing a semiconductor device on the second manufacturing line, and a step of inspecting an area of the set semiconductor device by an inspection device provided in the second manufacturing line. Construction method.

The appearance / foreign matter inspection device determines the size of the defect on the wafer, calculates the defect occurrence density on the wafer for each predetermined size, and when the defect occurrence density of any of the defect sizes is equal to or more than a predetermined value, 7. The method for manufacturing a semiconductor device according to claim 6, wherein an inspection device capable of detecting a defect size equal to or larger than the predetermined value is set in the second manufacturing line.

The appearance / foreign matter inspection device determines the type of defect on the wafer, calculates the defect occurrence density on the wafer for each predetermined defect type, and when the defect occurrence density of one of the defect types is equal to or higher than a predetermined value. 8. The method according to claim 6, wherein an inspection device capable of detecting the type of the defect having the predetermined value or more is set in the second manufacturing line.

Attaching a defect of a predetermined size to the shape of each step in the process of manufacturing the semiconductor device and simulating the subsequent manufacturing process;

Connection of each part constituting the simulated shape by attaching the defect Memorizing the relationship;

Comparing the stored connection relation of each part with the connection relation of each part constituting the simulated shape without generating a defect, and judging that the connection relation does not match is abnormal;

A method of manufacturing a semiconductor device by setting an inspection device capable of detecting a defect of a predetermined size for a process determined to be abnormal by the simulation.

10. The inspection area of the inspection apparatus according to claim 9, wherein the defect attachment positions are made different and simulated, and an inspection area of the inspection device is set so as to inspect the attachment position determined to be abnormal. Semiconductor device manufacturing method.

10. The inspection apparatus according to claim 9 or 1, wherein the defect is simulated with different sizes, and an inspection apparatus capable of detecting the size of the defect is set for a process determined to be abnormal. 9. The method for manufacturing a semiconductor device according to item 0.