WO1998028745A1 - Memoire inscriptible remanente a capacite de programmation rapide - Google Patents

Memoire inscriptible remanente a capacite de programmation rapide Download PDF

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Publication number
WO1998028745A1
WO1998028745A1 PCT/US1997/019209 US9719209W WO9828745A1 WO 1998028745 A1 WO1998028745 A1 WO 1998028745A1 US 9719209 W US9719209 W US 9719209W WO 9828745 A1 WO9828745 A1 WO 9828745A1
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WO
WIPO (PCT)
Prior art keywords
memory
programmed
reference level
memory cells
program
Prior art date
Application number
PCT/US1997/019209
Other languages
English (en)
Inventor
Andrew J. Hurter
Edward M. Doller
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to AU49966/97A priority Critical patent/AU4996697A/en
Publication of WO1998028745A1 publication Critical patent/WO1998028745A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Definitions

  • the present invention relates to memory devices. More particularly, this invention relates to programming of a nonvolatile writeable memory. BACKGROUND OF THE INVENTION
  • Nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories (“EEPROMs”) and flash Erasable and Electrically Programmable Read-Only Memories (“flash EPROMs” or “flash memories”).
  • EEPROMs Electrically Erasable Programmable Read-Only Memories
  • flash EPROMs flash Erasable and Electrically Programmable Read-Only Memories
  • Non-volatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
  • Writability or programmability, enables the computing system to be reprogrammed. This is useful, for example, for upgrading the system, or for correcting bugs in the code.
  • FIG. 1 is a block diagram of a prior art nonvolatile writeable memory device 20.
  • Memory device 20 stores data using nonvolatile memory cells within memory array 22.
  • the threshold voltages of the nonvolatile memory cells can be altered during programming, thus permitting storage of analog voltage levels, as is well known in the art.
  • Memory array 22 may include any type of memory cell with programmable threshold voltages, such as memory cells with trapping dielectric or floating gates. In one embodiment, memory array 22 is comprised of flash memory cells.
  • Vpp is the erase/program power supply for memory device 20.
  • memory device 20 acts as a read only memory.
  • the data stored at an address indicated by address lines 24 is read from memory array 22 and is output to the external user via data lines 26.
  • X decoder 28 selects the appropriate row within memory array 22 in response to address signals applied to address lines 24. For this reason, X decoder 28 is also called row decoder 28.
  • Y decoder 30 selects the appropriate column within memory array 20 in response to address signals from address lines 24. Because of its function, Y decoder 30 is also called column decoder 30.
  • Data output from memory array 22 is coupled to Y decoder 30, which passes the data on to sensing circuitry 32.
  • Sensing circuitry 32 determines the state of data presented to it using reference cell array 34. Sensing circuitry 32 then passes the results of its analysis back to Y decoder 30.
  • control engine 36 controls the erasure and programming of memory array 22. In another embodiment, control engine 36 also controls the programming of multilevel cells.
  • a multilevel cells is a cell that can store three or more charge states, as is well-known in the prior art.
  • control engine 36 includes a processor or microcontroller that is controlled by microcode stored in on-chip memory. However, the particular implementation of control engine 36 does not affect the present method of programming memory cells.
  • Control engine 36 manages memory array 22 via control of row decoder 28, column decoder 30, sensing circuitry 32, reference cell array 34 and voltage switch 38.
  • Voltage switch 38 controls the various voltage levels necessary to read, program and erase memory array 22.
  • Vcc is the device power supply and Vss is ground.
  • Vpp is the program/erase voltage used to program or erase data stored within memory array 22. Vpp may be externally supplied or internally generated.
  • command interface 40 User commands for reading, erasure, and programming are communicated to control engine 36 via command interface 40.
  • the external user issues commands to command interface 40 via three control pins: output enable OEB, write enable WEB and chip enable CEB.
  • FIG. 2 is a diagram showing a prior art memory cell of the memory array 22 in terms of a threshold voltage, Vt.
  • the state of the memory cell may be defined in terms of the memory cell threshold voltage level or the drain current.
  • Memory cell threshold voltage Vt, and drain current Id are approximately related to each other by the expression: Id ⁇ Gm x (Vg - Vt) for Vd > Vg - Vt, where
  • Gm is the transconductance of the memory cell
  • Vg is the memory cell gate voltage
  • Vd is the memory cell drain voltage
  • Vt is the memory cell threshold voltage
  • the memory cell has associated with it, a programmed-reference level and an erased-reference level. If the charge stored on the floating gate of the memory cell corresponds to a Vt below the erased reference level, then the memory cell is defined to be in an "erased" state. If the charge stored on the floating gate of the memory cell corresponds to a Vt above the programmed- reference level, then the memory cell is defined to be in a "programmed" state.
  • a read reference level is typically used to read from the memory cell. If the Vt of the memory cell is higher than the read reference level, then the read indicates the memory cell is in a "programmed" state. If the Vt is below the erased reference voltage, then the read indicates the memory cell is in an "erased” state.
  • a memory cell is typically programmed by applying a program pulse to store charge on the floating gate of the memory cell.
  • a program verify cycle is then performed to ensure that the Vt of the memory cell is above the programmed reference level.
  • Vt is not above the programmed reference level, then one or more subsequent program pulses are applied to the memory cell, as needed, until the Vt of the memory cell is above the programmed reference level.
  • the memory Because the number of program pulses required to ensure that the Vt of the memory cell is above the programmed reference level is indeterminate, the memory has a long program latency time. Thus, the memory is not able to store data at a high transfer rate because the memory cannot guarantee that it will be able to store data by using a predetermined number of program pulses.
  • a method and apparatus for programming a nonvolatile writeable memory is described.
  • One or more memory cells of a block of memory cells of the nonvolatile writeable memory is programmed using no more than one program pulse.
  • the memory cells of the block of memory cells having a threshold voltage in an intermediate region below a programmed reference level and above an erased reference level are identified. These identified memory cells are programmed with one or more program pulses to raise the threshold voltage of the corresponding memory cell up to the programmed reference level.
  • Figure 1 is a block diagram of a prior art nonvolatile writeable memory device 20.
  • Figure 2 is a diagram showing a prior art memory cell of the memory array 22 in terms of a threshold voltage, Vt.
  • Figure 3 is a diagram showing the different charge regions of a memory cell according to one embodiment of the present invention.
  • Figure 4 shows a flow chart illustrating the steps taken by the memory in identifying memory cells in the intermediate region 62 (Fig. 3)
  • Figure 5 shows a representative sense amp which is used to determine the Vt of a memory cell.
  • Figure 6 shows the results of a read from a first group of memory cells at the programmed reference level being compared with the results of a read from the same first group of memory cells at the nominally programmed reference level.
  • Figure 7 illustrates a memory device having an external fast programming pin.
  • a method and apparatus for allowing the fast programming of memory cells of a memory array is described.
  • the memory cells are programmed with a single program pulse. This allows the memory to accept data at a rate corresponding to the latency of the single program pulse.
  • the memory cells that were programmed with the single program pulse are checked to determine if any of the memory cells have a threshold voltage over an erased reference level but below a programmed reference level. Any memory cell found in this intermediate region is provided with one or more program pulses until each memory cell has a threshold voltage above the programmed reference level.
  • the invention may be expanded to provide an initial program cycle of any number of program pulses, as long as the initial program cycle has a predefined latency time.
  • Figure 3 is a diagram showing the different charge regions according to the present invention. If a memory cell has a Vt above a programmed reference level 50, then the memory cell is in a programmed state 60. If the memory cell has a Vt below the erased reference level 54, then the memory cell is in an erased state 66.
  • the region between the programmed reference level 50 and the erased reference level 54 is comprised of an intermediate region 62 and a guardband region 64.
  • the read reference level typically resides within the intermediate region 62.
  • the invention searches for memory cells having a Vt within the intermediate region, as will be explained in further detail. Once these memory cells have been identified, then each of these memory cells is programmed to raise the Vt of that memory cell up to the programmed reference level.
  • the programmed reference level is approximately 5.3 V
  • the erased reference level is approximately 3.1 V.
  • Figure 4 shows a flow chart illustrating the steps taken by the memory in identifying memory cells in the intermediate region 62 (Fig. 3).
  • the flow chart starts at a block 80, from which it continues at block 82.
  • a first group of memory cells each having a stored charge over a first reference level is identified.
  • Operation continues at block 84, at which a subset of the first group of memory cells is determined, wherein the subset of the first group of memory cells has a stored charge less than a second reference level.
  • each of the memory cells of the subset is programmed until each memory cell has a stored charge over the second reference level. Operation terminates at block 88.
  • the process may be performed successively on each memory cell to determine whether that particular memory cell needs to be programmed before checking the next memory cell.
  • Figure 5 shows a representative sense amp which is used to determine the Vt of a memory cell.
  • Each memory cell of the memory array is compared against a reference cell to determine whether the Vt of the memory cell is higher or lower than that of the reference cell, as is well-known in the prior art.
  • a "nominally programmed" reference cell is created corresponding to the erased reference level of the memory cell plus a guardband 64. This nominally programmed reference level is compared against each memory cell to determine whether any of the memory cells need to be programmed up to the programmed state 60.
  • a guardband of approximately 400 mV was experimentally determined to be a sufficient buffer to prevent erased memory cells from erroneously being determined to be in the intermediate region yet still able to capture any "nominally programmed" memory cells.
  • either a read reference cell or an erased reference cell is used to emulate a new nominally programmed reference cell.
  • the gate voltage of the reference circuit Vgr can be modified from the gate voltage of the memory cell Vga in order to emulate a reference circuit corresponding to a different Vt by the formula:
  • Vgr Vga - guardband, for the erased reference cell.
  • Vga 5.0 V and the guardband is 400 mV, then Vgr is 4.6 V.
  • Figure 6 shows the results of a read from a first group of memory cells at the programmed reference being compared with the results of a read from the same first group of memory cells at the nominally programmed reference. In this case, the comparison is done via an XOR gate. Any differences between the two results indicate that at least one of the memory cells has fallen into the intermediate region and is not sufficiently programmed. The indicated memory cell(s) is then programmed to the programmed reference level.
  • Figure 7 illustrates a memory device having an external fast programming pin.
  • the fast programming pin When the fast programming pin is asserted then the memory performs in a fast programming mode of operation.
  • the memory device may, either in addition to or alternatively, allow a fast programming command to be written to the command interface 140 to initiate the fast programming mode.
  • the memory has a fast programming mode and a standard programming mode.
  • the program verify is used after each write to a memory cell to guarantee that the threshold voltage of the memory cell is above the programmed reference level.
  • the fast programming mode the memory uses the initial program cycle to quickly program a block of memory cells, where a block can be any number of memory cells. Subsequently, for example, upon exiting the fast programming mode, the memory checks the block of memory for memory cells in the intermediate region. The memory cells in the intermediate region are programmed with one or more program pulses until they have a threshold voltage above the programmed reference level. In one embodiment, the memory check is automatically performed when the memory is idle.
  • a separate command or pin is used to search for memory cells in the intermediate region, as is described in copending application
  • Nonvolatile Writeable Memory which is assigned to the common assignee of this application.
  • the checking for memory cells having threshold voltages in the intermediate region can be deferred until it is convenient to do the checking.

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Abstract

Un procédé et un appareil présentent une capacité de programmation rapide d'une mémoire inscriptible rémanente. Une ou plusieurs cellules de mémoire d'un bloc de cellules de mémoire de la mémoireinscriptible rémanente est/sont programmé(es) par une seule impulsion de programme. Les cellules de mémoire du bloc de cellules de mémoire présentant une tension de seuil dans une région intermédiaire (62) inférieure à un niveau de référence programmé (54) et supérieur à un niveau de référence d'effacement (50) sont identifiées. Ces cellules de mémoire identifiées sont programmées avec une ou plusieurs impulsions de programme afin d'élever la tension de seuil de la cellule correspondante jusqu'au niveau de référence programmé (52).
PCT/US1997/019209 1996-12-20 1997-10-23 Memoire inscriptible remanente a capacite de programmation rapide WO1998028745A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU49966/97A AU4996697A (en) 1996-12-20 1997-10-23 Nonvolatile writeable memory with fast programming capability

Applications Claiming Priority (2)

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US77039796A 1996-12-20 1996-12-20
US08/770,397 1996-12-20

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WO1998028745A1 true WO1998028745A1 (fr) 1998-07-02

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