WO1998025303A1 - Chip scale ball grid array for integrated circuit package - Google Patents
Chip scale ball grid array for integrated circuit package Download PDFInfo
- Publication number
- WO1998025303A1 WO1998025303A1 PCT/US1997/005489 US9705489W WO9825303A1 WO 1998025303 A1 WO1998025303 A1 WO 1998025303A1 US 9705489 W US9705489 W US 9705489W WO 9825303 A1 WO9825303 A1 WO 9825303A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- nonpolymer
- package
- support structure
- conductive
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Definitions
- This invention relates generally to integrated circuit packaging, and more specifically to ball grid arrays.
- this invention relates to a 0 chip scale ball grid array design employing a flex tape having a nonpolymer support structure.
- BGA Ball grid array
- TAB tape automated bonding
- flexible s circuitry typically consists of copper traces on a thin polyimide substrate.
- Electrically conductive leads may be laminated on one or both sides of tne TAB tape.
- This BGA design is commonly referred to as a Tape BGA 0 (TBGA) .
- the circuitry on the tape has leads which are connected to a semiconductor die through any of the conventional methods such as wire bonding, thermocompression bonding, or flip chips. If the circuitry is present on both sides of the tape, s electrically conducting vias may extend through the tape from one layer of circuitry to another.
- solder bumps are sometimes deposited directly onto tne surface of an IC itself and used for attachment to tne PCB (commonly referred to as direct chip attach or flip chip; .
- direct chip attach or flip chip commonly referred to as direct chip attach or flip chip; .
- tne 5 deposition of solder balls requires a number of costly process steps.
- This underfill is required to reduce thermal stress 0 which is caused oy the low thermal expansion of a die relative to the typically much higher expansion of a PCB ("thermal mismatch stress") .
- Deposition of this underfill is a costly process which eliminates the ability to rework the component. Consequently, if any ⁇ defects are found, a valuable PCB must be thrown out.
- Another class of BGA packages have been developed. This class of BGA package may be referred to as a chip scale ball grid array or a chip scale package (CSP) . Chip scale packages are so called because the total package size is similar or not much larger than the size of the IC itself.
- solder ball terminals are typically disposed underneath a semiconductor die in order to reduce package size.
- a CSP is a product developed by TESSERA called "MICRO BGA.”
- This product consists of a flexible circuit with a soft compliant elastomer layer (or elastomer pad) between the die and the circuit.
- This elastomeric member consists of polymer materials such as silicone and is typically about 5-7 mils thick.
- One purpose of the elastomer is to obtain suitable reliability by minimizing thermal mismatch stress between the die and the PCB without the need for expensive underfill material.
- elastomer material which meets industry requirements of low moisture absorption, low outgassing, and the ability to withstand cleaning solvents commonly used in the industry.
- silicone is known to breakdown with some typically used cleaning solvents, and polymer materials in general tend to absorb and outgas moisture. If moisture absorption is too high, rapid outgassing of this moisture at reflow temperatures will cause voids to form at component interfaces and even bursting of the package. For example, moisture may release from polymer materials in a tape and become trapped within the die attachment adhesive. Voids may then be formed when this trapped moisture expands during board assembly heating operations, typically causing cracking and package failure. Formation of such voids may be particularly acute during reflow attachment to a PCB.
- the TESSERA "MICRO BGA" design employs a metal frame adhered to the outer edge of a strip of parts to allow strip format processing.
- the use of such frames is not convenient and adds to the final cost of a product because it increases the complexity and number of components in a tape processing design, as well as requires additional steps to attach and remove the frames during processing. Therefore, although strip format processing has typically been used for integrated circuit packaging, no convenient strip format chip scale package design current exists.
- the disclosed method and apparatus relate to chip scale ball grid arrays for integrated circuit packaging. These products may be used to provide low cost chip scale packages that offer improved reliability and which facilitate processing.
- a nonpolymer layer or support structure is used between a semiconductor die and accompanying circuitry.
- a nonpolymer layer may be used to provide a substantially rigid and planar surface, as well as to separate or decouple the die from a substrate, such as a printed circuit board (PCB) .
- adhesive materials are also employed between a nonpolymer support structure and adjacent components of a chip scale package assembly for purposes of attachment and to further decouple a die and substrate.
- the nonpolymer support structure reduces thermal stress. Because the support structure is nonpolymeric, void creation between the support structure and a die is substantially eliminated.
- the nonpolymer support structure also offers sufficient rigidity to allow integrated circuit processing in strip formats. When employed as a layer that is thinner and less rigid than a support structure layer, nonpolymer material acts to substantially eliminate the formation of voids, among other things .
- this invention is a package for an integrated circuit including an intermediate circuit having an array of electrical interconnects and at least one nonpolymer layer having first and second sides.
- the first side of the nonpolymer layer is structurally coupled to the integrated circuit, and the second side of the nonpolymer layer is structurally coupled to the intermediate circuit.
- this invention is a method of forming a package for an integrated circuit including the steps of providing an intermediate circuit including an array of electrical interconnects, and providing at least one nonpolymer layer having a first side adapted for structural coupling to an integrated circuit. This method also includes the step of structurally coupling the second side of the nonpolymer layer to the intermediate circuit.
- this invention is an electronic package including a flexible tape having a patterned conductive layer and at least one patterned dielectric layer.
- the package also includes at least one nonpolymer support structure having first and second sides. The first side of the support structure is structurally coupled to the second side of the conductive layer of the flexible tape.
- this invention is an electronic package, including a patterned conductive layer having first and second sides and an outer lateral boundary.
- the conductive layer is patterned to form an electrically conductive region having peripheral conductive features disposed around a circumference of the outer lateral boundary for electrical connection to a semiconductor device.
- the package also includes a patterned dielectric layer having first and second sides and an outer lateral boundary with a smaller circumference than the circumference of the patterned conductive layer.
- the dielectric layer is patterned to form a plurality of openings extending through the dielectric layer, with each of the openings being configured to receive a solder ball.
- the first side of the conductive layer is joined to the second side of the dielectric layer so that the plurality of openings in the dielectric layer are aligned with at least part of the electrically conductive region of the conductive layer, and so that the peripheral conductive features of the conductive layer extend beyond the outer boundary of the dielectric member.
- a substantially rigid nonpolymer support structure having first and second sides, and having an elastic modulus greater than about 1 Mpsi.
- the first side of the support structure is structurally coupled to the second side of the conductive layer.
- the first side of a semiconductor device is structurally coupled to the second side of the nonpolymer support structure.
- the semiconductor device includes a plurality of electrical contact sites, with at least one of the contact sites being electrically coupled to the peripheral conductive features of the conductive layer.
- a plurality of solder balls are disposed on the first side of the dielectric layer, with each of the solder balls positioned in one of the plurality of openings in the dielectric layer and electrically connected to the conductive region of the conductive layer.
- FIG. 1 is a cross-sectional representation of a conventional chip scale package design of the prior art .
- FIG. 2 is a cross-sectional representation of another conventional chip scale package design of the prior art.
- FIG. 3 is a cross-sectional representation of a chip scale package design according to one embodiment of the disclosed method and apparatus.
- FIG. 3A is a cross-sectional representation of another chip scale package design according to one embodiment of the disclosed method and apparatus .
- FIG. 3B is a cross-sectional representation of another chip scale package design according to one embodiment of the disclosed method and apparatus.
- FIG. 3C is a cross-sectional representation of another chip scale package design according to one embodiment of the disclosed method and apparatus.
- FIG. 3D is a cross-sectional representation of another chip scale package design according to one embodiment of the disclosed method and apparatus.
- FIG. 4 is a cross-sectional representation illustrating lamination of adhesive layers to a thin nonpolymer material according to one embodiment of the disclosed method and apparatus.
- FIG. 5 is a top view of a sheet of nonpolymer material that has been laminated with adhesive and punched according to one embodiment of the disclosed method and apparatus.
- FIG. 6 is a top view of the nonpolymer sheet of FIG. 5 with laminated flex circuitry according to one embodiment of the disclosed method and apparatus.
- FIG. 6A is a top view of the nonpolymer sheet of FIG. 5 with an attached wire bonded die according to one embodiment of the disclosed method and apparatus.
- FIG. 7 is a cross-sectional representation of a chip scale package strip positioned in a fixture for bonding according to one embodiment of the disclosed method and apparatus .
- FIG. 8 is a cross-sectional representation of a chip scale package strip positioned in a fixture during overmolding according to one embodiment of the disclosed method and apparatus.
- FIG. 9 is a cross-sectional representation of a chip scale package strip oriented die-side upwards on a fixture for encapsulation according to one embodiment of the disclosed method and apparatus.
- FIG. 10 is a cross-sectional representation of a completed chip scale package according to one embodiment of the disclosed method and apparatus.
- FIG. 1 illustrates a conventional chip scale package integrated circuit package design having an elastomer pad 10 placed between a semiconductor die 12 and two piece flexible circuit tape 18.
- the elastomer pad 10 is often applied as part of a tape and may have adhesive layer 16 and adhesive layer 24 disposed on each side.
- a two piece tape is often employed, although tape having three or more layers may also be used.
- two piece flexible circuit tape 18 is attached to elastomer pad 10 by adhesive layer 16 and includes a patterned dielectric (typically polyimide) layer 20 and a patterned conductive layer 21.
- adhesive layers 16 and/or 24 may be absent and elastomer pad 10 applied onto a tape 18, such as by screen printing.
- Two piece flexible tape 18 may be formed, for example, by plating or sputtering a conductive metal layer 21 directly onto a dielectric layer 20.
- Conductive layer 21 may be patterned by selective plating or plate and etch methods .
- Conductive layer 21 is formed, for example, by sputtering conductive metal directly onto dielectric layer 20.
- Dielectric layer 20 is patterned with openings (or vias) 22 for accepting solder balls (or bumps) 14 so that solder balls 14 make electrical contact with patterned conductive layer 21.
- adhesive layer 16 may deform (or be compressed) between the patterned conductive material of layer 21 and elastomer pad 10, while at the same time filling spaces between elastomer pad 10 and dielectric layer 10 in those areas where patterned conductive material is not present.
- adhesive layer 16 may be a thickness of about 2 mils before deformation and be compressed to a thickness of between about 0.5 mil and about 1.5 mils between patterned conductive layer 21 and elastomer pad 10.
- Semiconductor die 12 is attached to elastomer pad 10 by adhesive layer 24.
- inner lead bonding is provided between circuit leads 42 and die pads 44. Edges of the semiconductor die 12, including the inner lead bonding areas, are encapsulated with encapsulant 46 which is contained within encapsulant dams 48.
- elastomer pad 10 is typically an elastomer with a relatively low modulus that is employed to isolate or "decouple" the integrated circuit from solder joints made to a PCB or other substrate in an attempt to reduce the stress on the solder joint and increase circuit reliability over periods of thermal cycling.
- selection of a suitable elastomer is often difficult. This is because it is difficult to find elastomer materials which meet the stringent requirements of integrated circuit packaging.
- processes for attaching elastomer pads to other circuit components are typically rife with challenges, such as achieving accurate placement or dealing with the typical messiness of screen printing and curing.
- Typical elastomer materials utilized include silicone based materials and low modulus epoxies .
- FIG. 2 shows another conventional chip scale package integrated circuit design using three layer flexible circuit tape and x punched" vias.
- a relatively thick dielectric layer 220 is bonded to a patterned conductive circuit layer 216 using an adhesive layer 217 to form a three layer tape.
- a relatively thick polymer covercoat layer 211 is deposited directly onto three layer tape 218 and attached to semiconductor die 212 with adhesive layer
- Covercoat layer 211 is typically a polymeric material having a thinner cross section (around 1 mil) , but higher modulus than the elastomer pad 10 of FIG. 1. Typically, covercoat 211 is an epoxy based material. In this conventional application, the three layer tape/flex circuitry combination is typically configured as a "strip" and is fairly rigid so that the strip may be removed and placed into a fixture for overmolding of a die without bending bond wires 240 during the transfer step.
- voids may form in adhesive layer 224 due to moisture which has released from polymer layers, such as dielectric layer 220 (typically a polyimide) and covercoat 211 upon curing of die attachment adhesive 224 (typically performed at around 150°C) .
- Further creation of voids typically occurs during solder reflow attachment of solder balls 214 to a substrate such as a PCB board 236.
- thermal cracks formed in solder balls 214. Thermal cracks are typically caused by thermal stress generated between die 212 and attached substrate 236. Such thermal cracking may be the cause of premature failure of solder ball joints 238.
- a nonpolymer support structure (or pad) is used between a semiconductor device or integrated circuit (such as a semiconductor die) and accompanying circuitry to provide a substantially rigid and planar surface, and to separate or decouple the die from a substrate, such as a PCB.
- adhesive materials are also employed between a nonpolymer support structure and adjacent components of a chip scale package assembly for purposes of attachment and to further decouple a die and substrate.
- a nonpolymer support structure having a coefficient of thermal expansion (CTE) close to that of the substrate is employed to minimize thermal stress effects on solder joints.
- CTE coefficient of thermal expansion
- FIG. 3 shows a cross-sectional view of a chip scale package design according to one embodiment of the disclosed method and apparatus having a nonpolymeric support structure 50 disposed between a semiconductor die 52 and an intermediate circuit comprising two layer flexible circuit tape (or flex circuit or TAB tape) 58.
- nonpolymer support structure 50 is structurally coupled to the die 52 by means of adhesive layer 64.
- "structurally coupled" means two components are directly coupled or indirectly coupled (e.g., with intervening layers or other components positioned between) using any suitable means (such as by deposition, with adhesive, or other forms of bonding) .
- semiconductor die 52 typically has die bond pads or contacts 84.
- FIG. 3 illustrates an embodiment of a chip scale package design employing two layer flexible circuit tape, it will be understood with benefit of the present disclosure that embodiments employing other types of intermediate circuitry, for example, nonflexible circuit strips or flexible circuit tapes having three or more layers are also possible.
- three layer tape 19 and wire bonding is illustrated in FIG. 3C.
- three layer tape 19 includes dielectric layer 60, conductive layer 59, and second dielectric layer (typically polyimide) 60a.
- Adhesive layer 60b is employed between layers 59 and 60a.
- Intermediate circuitry typically includes an array of interconnects for electrical connection to a substrate, such as a PCB.
- two layer flexible circuit tape 58 typically includes a patterned dielectric layer 60, and a patterned planar conductive layer 59 having individual conductive bonding pads 59a.
- Solder ball conductive pads 59a are typically from about 200 microns to about 600 microns in diameter and have a pitch of between about 300 microns and about 1250 microns .
- Patterned conductive layer 59 may be comprised of any patternable conductive material suitable for forming substantially planar circuitry including, but not limited to, metals or conductors such as silicon and polysilicon, tungsten, titanium, aluminum, aluminum based metals (such as aluminum alloys), copper, and alloys and combinations thereof, etc. (for purposes of this disclosure the term "metals" is defined to include metals, refractory metals, intermetallics, and the like or combinations thereof) . Most typically patterned conductive layer 59 is copper.
- Patterned dielectric layer 60 may be comprised of any patternable dielectric material suitable for insulating conductive layer 59 including, but not limited to, polyimide or polyester.
- dielectric layer 60 is a polyimide, such as "DUPONT KAPTON” or "UBE UPILEX.”
- Patterned conductive layer 59 typically has a thickness of between about 0.5 mils to about 1.5 mils.
- Patterned dielectric layer 60 typically has a thickness of between about 1 mils to about 3 mils.
- conductive solder balls (or bumps) 54 are attached to flexible tape 58 and make electrical contact with individual pads 59a through openings (or vias) 62 patterned in dielectric layer 60. Openings 62 are patterned in a manner complementary with conductive pads 59a so that each opening 60 overlays a respective conductive pad 59a.
- Solder balls 54 may be any shape and dimension suitable for making connection with bonding pads 59a through openings 62. Typically, solder balls 54 are substantially spherical in shape and have a diameter of from about 250 microns to about 750 microns, most typically between about 300 microns and about 600 microns .
- Solder balls are typically reflow attached using conventional ovens such as IR, convection, or vapor phase. Openings 62 are sized and shaped to accept solder balls 54 in such a way that electrical contact may be made with bonding pads 59a. Typically, openings 62 are circular and have a diameter of between about 250 microns and about 600 microns, more typically between about 300 microns and about 500 microns. Conductive solder balls may be constructed of any suitable conductive material including, but not limited to, gold, solder, or copper.
- patterned conductive layer 59 typically has a plurality of bonding leads 82, each of which are electrically coupled to a conductive pad 59a.
- bonding leads 82 are between about 25 microns and about 100 microns in width.
- Bonding leads 82 are for making electrical connection to semiconductor die 52 at die pads 84 by, for example, inner lead bonding, and are therefore configured with a similar pitch as die pads 84 and a length sufficient to allow mating between leads 82 and pads 84.
- leads 82 may also be formed to have pads 83 for wire bonding to semiconductor die 52 using wire bonds 82a as shown in FIG. 3A.
- each bonding lead 82 when each bonding lead 82 is electrically connected to a respective die pad 84, a circuit is completed between each solder ball 54 and a corresponding die pad 84.
- each solder ball 54 When so configured to form a ball grid array, each solder ball 54 is designed to be used as an individual "pin” to electrically connect an individual die pad 84 to a corresponding substrate bonding pad 75 on a substrate 76.
- the pitch of ball grid array 57 as illustrated in FIG. 6, and of corresponding substrate bonding die pads 75 is typically between about 300 microns and about 1250 microns.
- a substrate is a printed circuit board (“PCB"), but may also be any other circuitry including, but not limited to, flex circuitry, silicon, wafers, etc.
- edges of die 52 and inner lead connection areas are typically encapsulated by encapsulant 86 which is contained by encapsulating dams 88.
- Encapsulant 86 may be any suitable encapsulant known to those of skill in the art including, but not limited to, epoxy resin and silicone.
- Encapsulant dams 88 may be any suitable encapsulant containment structure including, for example, epoxy, adhesive tape, etc.
- FIG. 3 illustrates a chip scale package design employing a single patterned conductive layer 59, it will be understood with benefit of the present disclosure that embodiments having two or more patterned (or non- patterned) conductive layers are also possible. In the embodiment of FIG.
- nonpolymer pad 50 may be any material suitably rigid to facilitate processing and/or having a coefficient of thermal expansion close to that of a substrate in order to minimize stress on solder joints. By using such a nonpolymer pad configuration, formation of voids in die attachment adhesive 64 may be reduced or substantially eliminated.
- chip scale package strips including a nonpolymer support structure 10 provide a surface having improved flatness or surface uniformity over conventional elastomer pads. Flatness of a grid array support structure surface is an important factor toward ensuring that all solder balls 54 contact pads 75 on a substrate 76.
- a chip scale package support structure has a coplanarity of about 2 mils or less, most desirably of about 1 mil or less. Such coplanarity is difficult to achieve using conventional soft elastomer pads.
- a nonpolymer support structure provides a more planar surface for solder ball attachment and therefore allows a more reliable connection between a semiconductor die and a substrate.
- a thermally conductive nonpolymer such as a metal sheet or foil
- nonpolymer support structure 50 may also conduct heat efficiently to the solder balls 54.
- thermally conductive nonpolymer typically employed is a metal sheet or foil, with copper being a particularly well suited metal for this purpose.
- a metal sheet may also provide improved electrical shielding of conductor layers 59 and may help minimize crosstalk.
- a metal sheet offers a surface that is suitable for use as a ground plane.
- a metal sheet may also be used to provide a convenient ground plane (or power plane if desired) , such as by direct electrical connection of a solder ball 54a to the metal sheet 53 as shown in FIG. 3B. This may be done, for example, through a via 55 in a conductive pad 59b and the underlying adhesive layer 56 so that selected ground connection solder balls 54a may electrically connect to the metal sheet 53.
- Suitable metal sheets include any patterned metal foil which supplies sufficient rigidity and/or thermal expansion qualities including, but not limited to metal foils made of copper, stainless steel, alloy 42, tungsten, titanium, aluminum, aluminum based metals (such as aluminum alloys), and alloys and combinations thereof, etc. Copper foil may also be coated with a thin plating for bonding to provide good solderability, low cost, and/or reduced oxidation.
- Suitable coatings include, but are not limited to, a surface coating of plated nickel, nickel/boron, black copper oxide, tin/lead (such as a high lead content tin/lead alloy of over about 37% lead, or precious metals, such as silver or gold.
- a nonpolymer support structure is a patterned copper foil having a thickness of between about 4 mils and about 10 mils, more typically between about 5 mils and about 7 mils.
- Copper alloys typically used for lead frames, such as 194, are well suited for this application.
- a chip scale package strip may be handled with typical magazine feeding equipment commonly used for lead frames.
- suitable rigidity it is meant that a modulus greater than about 1 Mpsi (1 x 10 6 pounds per square inch) .
- nonpolymer materials having suitable rigidity include ceramic, and metal foils such as those described above.
- benefits of the disclosed method and apparatus may also be realized using nonpolymer materials having a modulus less than about 1 Mpsi. Such benefits include those described elsewhere herein.
- adhesive layers 56 and 64 may be any adhesive suitable for securing nonpolymer pad 50 to flexible tape 58 and semiconductor die 52.
- adhesive layers 56 and 64 are selected from dielectric materials that act with a nonpolymer pad 50 to isolate or "decouple" die 52 from a substrate (or PCB) 76, thus further relieving stress on solder joints and providing improved reliability.
- Such adhesives also act to provide a small amount of Z-axis compliance for socketing.
- suitable adhesives include, but are not limited to, an acrylate PSA, a thermoplastic polyimide (such as DuPont "KJ” material), a polyolefin, DuPont “PYRALUX”, epoxy resins, and mixtures thereof.
- thermoplastic polyimide is employed as adhesive layers 56 and 64.
- Adhesive may be applied to a nonpolymer pad in any thickness suitable for forming a bond between the elastomer pad and adjacent surfaces, such as a die or circuit tracing.
- adhesive layers 56 and 64 have a thickness of between about 1 mil and about 3 mils, more typically between about 1 mil and about 2 mils.
- a mounting layer 351 may be patterned with a layer of deposited nonpolymer material 350 and employed between a semiconductor die 352 and accompanying circuitry.
- mounting layer 351 may be adhered to two layer flexible circuit tape 318 or other intermediate circuitry with adhesive layer 356, and to semiconductor die 352 with adhesive layer 364.
- embodiments of nonpolymer layer 350 act to reduce or substantially eliminate void formation by substantially preventing moisture from escaping into die attachment adhesive 364.
- a mounting layer patterned with nonpolymer material may be manufactured in many ways including, but not limited to, as a separate tape component, or as attached to a TAB tape. In some cases, the use of a mounting layer patterned with nonpolymer material may be less expensive than embodiments of the nonpolymer support structure previously described. Still referring to FIG.
- nonpolymer layer 350 may be composed of any nonpolymer material suitable for preventing the migration of moisture into adhesive layer 364, including those materials listed for use as a nonpolymer support structure.
- Mounting layer 351 may be any material suitable for patterning or deposition of nonpolymer layer 350, including those dielectric materials listed for use as patternable dielectric materials.
- adhesive layers 356 and 364 may be any suitable adhesive or attachment means, including those listed for use with nonpolymer support structures.
- nonpolymer layer 350 is a copper layer having a thickness of between about 1 ⁇ m and about 20 ⁇ m
- mounting layer 351 is a polyimide layer having a thickness of between about 1 mil and about 3 mils.
- nonpolymer layer 350 is a copper layer having a thickness of between about 5 ⁇ m and about 10 ⁇ m
- mounting layer 351 is a polyimide layer having a thickness of about 2 mils.
- FIG. 3D illustrates the use of a mounting layer 351 patterned with a nonpolymer layer 350 in an application similar to that shown in FIG. 3A for a nonpolymer support structure.
- a conductive nonpolymer layer 350 may be used as a ground plane, power plane or to complete other types of circuit paths, such as in a manner similar to that illustrated in FIG. 3B for a nonpolymer support structure.
- a mounting layer 351 and nonpolymer layer 350 may also be employed with intermediate circuitry having three or more layers, such as similar to the embodiment illustrated in FIG. 3C for nonpolymer support structures.
- more than one nonpolymer layer 350 may be employed.
- a chip scale package device of the disclosed method and apparatus having a nonpolymer support structure may be formed in a number of ways and for use in a number of different applications.
- one method of constructing chip scale package tape having a nonpolymer pad includes the steps of laminating an adhesive onto a roll of nonpolymer material (such as metal foil), punching or stamping the nonpolymer material in a desired shape, and aligning and adhering flexed circuitry (or circuit tracing) to the nonpolymer to form a chip scale package tape (such as in the form of a strip) .
- a chip scale package tape may be formed by punching a nonpolymer material (such as a metal foil) to a desired shape, punching an adhesive film to the same shape, aligning both film and foil with circuitry tracing, and laminating the structure. In either case, alignment of the circuit tracing to a nonpolymer support structure is accurate, yet relatively inexpensive.
- a variety of different steps may be performed using the chip scale package strip or tape just described to form a chip scale package device. These steps may include die attachment, wire and/or inner lead bonding, overmolding and/or solder ball attachment steps.
- assembly of chip scale package devices according to these processes is relatively efficient, straightforward, and cost effective.
- FIG. 4 illustrates lamination of adhesive layers 56 and 64 to both sides of a thin roll of copper sheet (or foil) 50.
- adhesive laminate having a coversheet or release liner
- the release liner is left on the side of adhesive layers 56 and 64 facing away from the copper foil 50.
- Suitable adhesive laminates incorporating release liners include acrylate PSA type adhesives.
- laminate adhesive used to form adhesive layers 56 and 64 is typically applied using roll laminates 100.
- adhesives such as those previously mentioned, may be applied using any suitable method including, but not limited to, screen printing and spray deposition.
- FIG. 5 shows a top view of a nonpolymer sheet 50 that has been laminated with adhesive layers 56 and 64.
- nonpolymer sheet 50 has been punched or stamped to form patterns having die squares 51 surrounded by connection slot regions 110.
- Die squares 51 are configured to have a shape complementary to a semiconductor die 52 and are smaller in area to allow clearance for connection of leads 82 (or wire bonds) to die pads 84 in the connection slot regions 110.
- Connection slots 110 provide space for connection to die pads 84 using inner lead bonding, wire bonding, or other suitable connection methods. Taken together, the dimensions of die squares 51 and connection slots 110, provide individual platforms for semiconductor dies 52.
- stamping or punching operations in the disclosed method may be performed using any punching or stamping method suitable for integrated circuit packaging.
- the nonpolymer sheet can also be patterned by chemical etching, using a steel rule die, or using a chem etched die.
- Tooling holes 112 are also punched in the sheet 50 to aid in the accurate alignment of circuitry .
- flexible tape 58 having vias 62 for accepting solder balls is aligned with the use of tooling holes 112 and laminated to one side of copper sheet 50.
- Lamination of circuitry may be accomplished in a number of ways, including in a roll- to-roll process (such as a roll-to-roll process using sprocket holes), or in a press.
- the release liner prior to lamination the release liner is typically pulled off the adhesive layer 56 and a panel or strip of circuits is laminated to the sheet 50 using tooling holes 112 for alignment.
- other adhesive and lamination methods such as those mentioned previously, may be employed.
- attachment and bonding of an integrated circuit die may continue uninterrupted, or the nonpolymer sheet 50 and the attached flexible tape 58 may be shipped elsewhere for further assembly.
- the nonpolymer sheets 50 and the attached flexible tape 58 are typically cut into a strip format prior to shipping.
- a strip format a single chip scale package strip typically has numerous individual die squares 51.
- further assembly typically involves removal of the second release liner from adhesive layer 64 in preparation for mounting a die onto the nonpolymer sheet 50.
- strips of nonpolymer sheets and attached circuitry are loaded into magazines for processing. Die are then typically placed on the tacky side of the nonpolymer strip (opposite the side with the circuitry) and cured if necessary.
- a die may also be picked and placed onto a roll of nonpolymer sheets (as opposed to a strip), and that a semiconductor die may be placed with its circuitry level adjacent or opposite the nonpolymer sheet.
- the die side of the nonpolymer strip may also be left bare of adhesive and a die attached adhesive (typically epoxy based materials) used for attachment of the die.
- the strips are typically flipped and placed into standard magazines which are loaded into, for example, a wire bond machine or a thermocompression bond machine As shown in FIG. 7, each lead 120 from the tape is bonded to a die pad 122 using, for example, a bonding tool 124.
- a fixture 126 is used to support the tape (including the dies) so as to allow the leads 120 to break at a frangible portion (or notch) 126 during the bonding process.
- the strip may then be overmolded by filling in the slots 110 with encapsulant 132.
- the encapsulant is contained by dam features 130 and cured using a suitable curing method such as, for example, UV or thermal methods.
- the strips may be flipped over onto a fixture surface 140 and the slots 110 filled with encapsulant 132 from the die side of the strip without need for encapsulant dam features. As shown in FIGS.
- a die 52 may also be connected to a circuit trace layer 59 using wire bonds 82a such as, for example, when a semiconductor die is "flipped" so that the circuit layer and die pads of a semiconductor die are oriented in a direction facing away from the support structure.
- wire bonds 82a such as, for example, when a semiconductor die is "flipped" so that the circuit layer and die pads of a semiconductor die are oriented in a direction facing away from the support structure.
- solder balls (or bumps) 54 may next be mounted within openings (or vias) 62 formed, for example, by etching openings within a polyimide layer 60. Solder balls 54 may be attached to strips using any method suitable for forming a secure electrical connection between the balls 54 and the conductive bonding pads 59a including, for example, heating and reflow using any conventional means such as IR, convection, or vapor phase.
- vias 62 may also be processed as plated through holes (PTH) and/or be filled with a separate conducting filler material prior to solder ball attachment.
- a strip or roll may be cut to form single or multiple die chip scale package packages (a single die package 150 is shown in FIG. 10) . This may be accomplished using any suitable excision method such as, for example, punching, cutting, or other similar process .
- chip scale package configurations may also be fabricated using this method, including packages having more than one semiconductor dies.
- non-chip scale package configurations such as conventional BGA packages, may be manufactured using the disclosed method and apparatus concepts.
- the methods just described and illustrated are for manufacturing integrated circuits using a strip format, benefit of these methods may also be obtained when used to manufacture integrated circuits using other processes and formats, including, but not limited to, integrated circuits formed using a roll-to-roll (or reel-to-reel) format. In this way benefits of the disclosed method and apparatus may be realized in formats compatible with existing industry infrastructure and with newer formats currently being employed or developed.
- the aforementioned packaging process may be performed while with a die still in wafer form.
- a nonpolymer sheet may be aligned and adhered directly to a wafer and chip bonding performed.
- slots may then be filled in with encapsulant, solder balls attached, and individual package pieces punched or sawed out.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52554098A JP2001506057A (en) | 1996-12-02 | 1997-04-02 | Chip-scale ball grid array for integrated circuit packages |
DE69730239T DE69730239D1 (en) | 1996-12-02 | 1997-04-02 | CHIP SIZE SOLDER BALL GRID FOR INTEGRATED CIRCUIT PACK |
EP97920070A EP0948814B1 (en) | 1996-12-02 | 1997-04-02 | Chip scale ball grid array for integrated circuit package |
AU24353/97A AU2435397A (en) | 1996-12-02 | 1997-04-02 | Chip scale ball grid array for integrated circuit package |
AT97920070T ATE273564T1 (en) | 1996-12-02 | 1997-04-02 | CHIP SIZE SOLDER BALL GRID FOR INTEGRATED CIRCUIT PACKAGING |
CA002272434A CA2272434A1 (en) | 1996-12-02 | 1997-04-02 | Chip scale ball grid array for integrated circuit package |
HK00102180A HK1023225A1 (en) | 1996-12-02 | 2000-04-10 | Chip scale ball grid array for integrated circuit package. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/759,253 | 1996-12-02 | ||
US08/759,253 US5990545A (en) | 1996-12-02 | 1996-12-02 | Chip scale ball grid array for integrated circuit package |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998025303A1 true WO1998025303A1 (en) | 1998-06-11 |
Family
ID=25054972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/005489 WO1998025303A1 (en) | 1996-12-02 | 1997-04-02 | Chip scale ball grid array for integrated circuit package |
Country Status (12)
Country | Link |
---|---|
US (1) | US5990545A (en) |
EP (1) | EP0948814B1 (en) |
JP (1) | JP2001506057A (en) |
KR (1) | KR100532179B1 (en) |
CN (1) | CN1239589A (en) |
AT (1) | ATE273564T1 (en) |
AU (1) | AU2435397A (en) |
CA (1) | CA2272434A1 (en) |
DE (1) | DE69730239D1 (en) |
HK (1) | HK1023225A1 (en) |
MY (1) | MY119341A (en) |
WO (1) | WO1998025303A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000005765A1 (en) * | 1998-07-22 | 2000-02-03 | Dyconex Patente Ag | Method for producing rewiring substrates for semiconductor chip packages |
WO2000022674A1 (en) * | 1998-10-14 | 2000-04-20 | Minnesota Mining And Manufacturing Company | Tape ball grid array with interconnected ground plane |
WO2001078472A1 (en) * | 2000-04-11 | 2001-10-18 | 3M Innovative Properties Company | Flexible circuit with plated cover layer and overlapping protective layer |
US6462274B1 (en) | 1998-10-31 | 2002-10-08 | Amkor Technology, Inc. | Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages |
Families Citing this family (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2891665B2 (en) | 1996-03-22 | 1999-05-17 | 株式会社日立製作所 | Semiconductor integrated circuit device and method of manufacturing the same |
US20040061220A1 (en) * | 1996-03-22 | 2004-04-01 | Chuichi Miyazaki | Semiconductor device and manufacturing method thereof |
JP3195236B2 (en) | 1996-05-30 | 2001-08-06 | 株式会社日立製作所 | Wiring tape having adhesive film, semiconductor device and manufacturing method |
US6962829B2 (en) * | 1996-10-31 | 2005-11-08 | Amkor Technology, Inc. | Method of making near chip size integrated circuit package |
US6150193A (en) * | 1996-10-31 | 2000-11-21 | Amkor Technology, Inc. | RF shielded device |
US5981314A (en) | 1996-10-31 | 1999-11-09 | Amkor Technology, Inc. | Near chip size integrated circuit package |
WO1998040915A1 (en) * | 1997-03-10 | 1998-09-17 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board |
JP3301355B2 (en) * | 1997-07-30 | 2002-07-15 | 日立電線株式会社 | Semiconductor device, TAB tape for semiconductor device, method of manufacturing the same, and method of manufacturing semiconductor device |
US5888850A (en) * | 1997-09-29 | 1999-03-30 | International Business Machines Corporation | Method for providing a protective coating and electronic package utilizing same |
US6310298B1 (en) * | 1997-12-30 | 2001-10-30 | Intel Corporation | Printed circuit board substrate having solder mask-free edges |
US6574858B1 (en) | 1998-02-13 | 2003-06-10 | Micron Technology, Inc. | Method of manufacturing a chip package |
JP3481117B2 (en) * | 1998-02-25 | 2003-12-22 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
US6166433A (en) * | 1998-03-26 | 2000-12-26 | Fujitsu Limited | Resin molded semiconductor device and method of manufacturing semiconductor package |
US6265776B1 (en) * | 1998-04-27 | 2001-07-24 | Fry's Metals, Inc. | Flip chip with integrated flux and underfill |
US6089920A (en) | 1998-05-04 | 2000-07-18 | Micron Technology, Inc. | Modular die sockets with flexible interconnects for packaging bare semiconductor die |
US6428641B1 (en) | 1998-08-31 | 2002-08-06 | Amkor Technology, Inc. | Method for laminating circuit pattern tape on semiconductor wafer |
US6479887B1 (en) | 1998-08-31 | 2002-11-12 | Amkor Technology, Inc. | Circuit pattern tape for wafer-scale production of chip size semiconductor packages |
JP2000138317A (en) | 1998-10-31 | 2000-05-16 | Anam Semiconductor Inc | Semiconductor device and its manufacture |
TW434850B (en) * | 1998-12-31 | 2001-05-16 | World Wiser Electronics Inc | Packaging equipment and method for integrated circuit |
US6175160B1 (en) * | 1999-01-08 | 2001-01-16 | Intel Corporation | Flip-chip having an on-chip cache memory |
US6377464B1 (en) * | 1999-01-29 | 2002-04-23 | Conexant Systems, Inc. | Multiple chip module with integrated RF capabilities |
US6341418B1 (en) * | 1999-04-29 | 2002-01-29 | International Business Machines Corporation | Method for direct chip attach by solder bumps and an underfill layer |
US6191483B1 (en) * | 1999-05-06 | 2001-02-20 | Philips Electronics North America Corporation | Package structure for low cost and ultra thin chip scale package |
JP3397725B2 (en) * | 1999-07-07 | 2003-04-21 | 沖電気工業株式会社 | Semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor device mounting tape |
JP3521325B2 (en) * | 1999-07-30 | 2004-04-19 | シャープ株式会社 | Manufacturing method of resin-encapsulated semiconductor device |
US6285077B1 (en) * | 1999-08-19 | 2001-09-04 | Lsi Logic Corporation | Multiple layer tape ball grid array package |
JP2001156212A (en) * | 1999-09-16 | 2001-06-08 | Nec Corp | Resin sealed semiconductor device and producing method therefor |
US6656765B1 (en) | 2000-02-02 | 2003-12-02 | Amkor Technology, Inc. | Fabricating very thin chip size semiconductor packages |
US6560108B2 (en) * | 2000-02-16 | 2003-05-06 | Hughes Electronics Corporation | Chip scale packaging on CTE matched printed wiring boards |
US6372539B1 (en) | 2000-03-20 | 2002-04-16 | National Semiconductor Corporation | Leadless packaging process using a conductive substrate |
US6399415B1 (en) * | 2000-03-20 | 2002-06-04 | National Semiconductor Corporation | Electrical isolation in panels of leadless IC packages |
US6686652B1 (en) | 2000-03-20 | 2004-02-03 | National Semiconductor | Locking lead tips and die attach pad for a leadless package apparatus and method |
US6452255B1 (en) | 2000-03-20 | 2002-09-17 | National Semiconductor, Corp. | Low inductance leadless package |
DE10014380A1 (en) * | 2000-03-23 | 2001-10-04 | Infineon Technologies Ag | Device for packaging electronic components |
US6444499B1 (en) * | 2000-03-30 | 2002-09-03 | Amkor Technology, Inc. | Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components |
TW466720B (en) * | 2000-05-22 | 2001-12-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with flash-prevention structure and manufacture method |
US6501170B1 (en) | 2000-06-09 | 2002-12-31 | Micron Technology, Inc. | Substrates and assemblies including pre-applied adhesion promoter |
US6710456B1 (en) | 2000-08-31 | 2004-03-23 | Micron Technology, Inc. | Composite interposer for BGA packages |
JP4570809B2 (en) * | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | Multilayer semiconductor device and manufacturing method thereof |
US6624005B1 (en) | 2000-09-06 | 2003-09-23 | Amkor Technology, Inc. | Semiconductor memory cards and method of making same |
US6809935B1 (en) | 2000-10-10 | 2004-10-26 | Megic Corporation | Thermally compliant PCB substrate for the application of chip scale packages |
US6552436B2 (en) * | 2000-12-08 | 2003-04-22 | Motorola, Inc. | Semiconductor device having a ball grid array and method therefor |
DE10064691A1 (en) * | 2000-12-22 | 2002-07-04 | Infineon Technologies Ag | Electronic component comprises a semiconductor chip with copper conducting pathways for connecting semiconductor electrode surfaces of elements of the chip to copper contact surfaces |
US6770963B1 (en) | 2001-01-04 | 2004-08-03 | Broadcom Corporation | Multi-power ring chip scale package for system level integration |
DE10120408B4 (en) * | 2001-04-25 | 2006-02-02 | Infineon Technologies Ag | Electronic component with a semiconductor chip, electronic assembly of stacked semiconductor chips and method for their production |
US7115986B2 (en) | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
US6861764B2 (en) * | 2001-06-27 | 2005-03-01 | Shinko Electric Industries Co., Ltd. | Wiring substrate having position information |
US6793759B2 (en) * | 2001-10-09 | 2004-09-21 | Dow Corning Corporation | Method for creating adhesion during fabrication of electronic devices |
US6873059B2 (en) * | 2001-11-13 | 2005-03-29 | Texas Instruments Incorporated | Semiconductor package with metal foil attachment film |
US6664615B1 (en) * | 2001-11-20 | 2003-12-16 | National Semiconductor Corporation | Method and apparatus for lead-frame based grid array IC packaging |
US6657134B2 (en) | 2001-11-30 | 2003-12-02 | Honeywell International Inc. | Stacked ball grid array |
SG104291A1 (en) * | 2001-12-08 | 2004-06-21 | Micron Technology Inc | Die package |
SG104293A1 (en) | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
SG115456A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
SG115459A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
US6975035B2 (en) | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG111935A1 (en) | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
SG115455A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
CA2491018C (en) * | 2002-06-28 | 2013-06-18 | Advanced Bionics Corporation | Microstimulator having self-contained power source and bi-directional telemetry system |
US20040036170A1 (en) | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
US6921975B2 (en) * | 2003-04-18 | 2005-07-26 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging, exposed active surface and a voltage reference plane |
US7266869B2 (en) * | 2003-07-30 | 2007-09-11 | Kyocera Corporation | Method for manufacturing a piezoelectric oscillator |
US20050056946A1 (en) * | 2003-09-16 | 2005-03-17 | Cookson Electronics, Inc. | Electrical circuit assembly with improved shock resistance |
JP3929966B2 (en) * | 2003-11-25 | 2007-06-13 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
US7075016B2 (en) * | 2004-02-18 | 2006-07-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Underfilling efficiency by modifying the substrate design of flip chips |
US11081370B2 (en) * | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
DE102004020580A1 (en) * | 2004-04-27 | 2005-11-17 | Infineon Technologies Ag | Method of manufacturing a BGA chip module and BGA chip module |
US7071559B2 (en) * | 2004-07-16 | 2006-07-04 | International Business Machines Corporation | Design of beol patterns to reduce the stresses on structures below chip bondpads |
US8125076B2 (en) * | 2004-11-12 | 2012-02-28 | Stats Chippac Ltd. | Semiconductor package system with substrate heat sink |
JP4343117B2 (en) * | 2005-01-07 | 2009-10-14 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US7968371B2 (en) * | 2005-02-01 | 2011-06-28 | Stats Chippac Ltd. | Semiconductor package system with cavity substrate |
US7316572B2 (en) * | 2005-02-03 | 2008-01-08 | International Business Machines Corporation | Compliant electrical contacts |
US20070018308A1 (en) * | 2005-04-27 | 2007-01-25 | Albert Schott | Electronic component and electronic configuration |
JP4548264B2 (en) * | 2005-08-01 | 2010-09-22 | 株式会社デンソー | Vehicle alternator |
DE102006015222B4 (en) * | 2006-03-30 | 2018-01-04 | Robert Bosch Gmbh | QFN package with optimized pad geometry |
US7788960B2 (en) * | 2006-10-27 | 2010-09-07 | Cummins Filtration Ip, Inc. | Multi-walled tube and method of manufacture |
US7573131B2 (en) * | 2006-10-27 | 2009-08-11 | Compass Technology Co., Ltd. | Die-up integrated circuit package with grounded stiffener |
TWI352406B (en) * | 2006-11-16 | 2011-11-11 | Nan Ya Printed Circuit Board Corp | Embedded chip package with improved heat dissipati |
US7944029B2 (en) * | 2009-09-16 | 2011-05-17 | Sandisk Corporation | Non-volatile memory with reduced mobile ion diffusion |
JP5642473B2 (en) * | 2010-09-22 | 2014-12-17 | セイコーインスツル株式会社 | BGA semiconductor package and manufacturing method thereof |
WO2013095363A1 (en) * | 2011-12-20 | 2013-06-27 | Intel Corporation | Microelectronic package and stacked microelectronic assembly and computing system containing same |
TWI544583B (en) * | 2012-04-18 | 2016-08-01 | 鴻海精密工業股份有限公司 | Chip assembly and chip assembling method |
TWI480989B (en) * | 2012-10-02 | 2015-04-11 | 矽品精密工業股份有限公司 | Semiconductor package and fabrication method thereof |
US20160317068A1 (en) * | 2015-04-30 | 2016-11-03 | Verily Life Sciences Llc | Electronic devices with encapsulating silicone based adhesive |
US10381300B2 (en) * | 2016-11-28 | 2019-08-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package including filling mold via |
CN112180128B (en) * | 2020-09-29 | 2023-08-01 | 珠海天成先进半导体科技有限公司 | Interconnection substrate with elastic conductive micro-bumps and KGD socket based on interconnection substrate |
US11990695B2 (en) | 2022-05-10 | 2024-05-21 | Apple Inc. | Method of reliably bonding solid metal piece to rigid PCB |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5420460A (en) * | 1993-08-05 | 1995-05-30 | Vlsi Technology, Inc. | Thin cavity down ball grid array package based on wirebond technology |
EP0692823A1 (en) * | 1994-07-11 | 1996-01-17 | Sun Microsystems, Inc. | Ball grid array package for an integated circuit |
FR2725305A1 (en) * | 1994-09-12 | 1996-04-05 | Nec Corp | LSI circuit chip package with carrier and underlying substrate |
EP0751561A1 (en) * | 1994-03-18 | 1997-01-02 | Hitachi Chemical Co., Ltd. | Semiconductor package manufacturing method and semiconductor package |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2439478A1 (en) * | 1978-10-19 | 1980-05-16 | Cii Honeywell Bull | FLAT HOUSING FOR DEVICES WITH INTEGRATED CIRCUITS |
US5148265A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5148266A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5241133A (en) * | 1990-12-21 | 1993-08-31 | Motorola, Inc. | Leadless pad array chip carrier |
JPH05160292A (en) * | 1991-06-06 | 1993-06-25 | Toshiba Corp | Multilayer package |
US5311059A (en) * | 1992-01-24 | 1994-05-10 | Motorola, Inc. | Backplane grounding for flip-chip integrated circuit |
US5214845A (en) * | 1992-05-11 | 1993-06-01 | Micron Technology, Inc. | Method for producing high speed integrated circuits |
US5592025A (en) * | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
US5468994A (en) * | 1992-12-10 | 1995-11-21 | Hewlett-Packard Company | High pin count package for semiconductor device |
US5397921A (en) * | 1993-09-03 | 1995-03-14 | Advanced Semiconductor Assembly Technology | Tab grid array |
US5477611A (en) * | 1993-09-20 | 1995-12-26 | Tessera, Inc. | Method of forming interface between die and chip carrier |
US5548091A (en) * | 1993-10-26 | 1996-08-20 | Tessera, Inc. | Semiconductor chip connection components with adhesives and methods for bonding to the chip |
US5473512A (en) * | 1993-12-16 | 1995-12-05 | At&T Corp. | Electronic device package having electronic device boonded, at a localized region thereof, to circuit board |
TW258829B (en) * | 1994-01-28 | 1995-10-01 | Ibm | |
US5528083A (en) * | 1994-10-04 | 1996-06-18 | Sun Microsystems, Inc. | Thin film chip capacitor for electrical noise reduction in integrated circuits |
JP3123638B2 (en) * | 1995-09-25 | 2001-01-15 | 株式会社三井ハイテック | Semiconductor device |
US5674785A (en) * | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
-
1996
- 1996-12-02 US US08/759,253 patent/US5990545A/en not_active Expired - Fee Related
-
1997
- 1997-04-02 AT AT97920070T patent/ATE273564T1/en not_active IP Right Cessation
- 1997-04-02 CA CA002272434A patent/CA2272434A1/en not_active Abandoned
- 1997-04-02 AU AU24353/97A patent/AU2435397A/en not_active Abandoned
- 1997-04-02 WO PCT/US1997/005489 patent/WO1998025303A1/en active IP Right Grant
- 1997-04-02 CN CN97180210A patent/CN1239589A/en active Pending
- 1997-04-02 EP EP97920070A patent/EP0948814B1/en not_active Expired - Lifetime
- 1997-04-02 JP JP52554098A patent/JP2001506057A/en active Pending
- 1997-04-02 DE DE69730239T patent/DE69730239D1/en not_active Expired - Lifetime
- 1997-04-02 KR KR10-1999-7004813A patent/KR100532179B1/en not_active IP Right Cessation
- 1997-11-28 MY MYPI97005743A patent/MY119341A/en unknown
-
2000
- 2000-04-10 HK HK00102180A patent/HK1023225A1/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5420460A (en) * | 1993-08-05 | 1995-05-30 | Vlsi Technology, Inc. | Thin cavity down ball grid array package based on wirebond technology |
EP0751561A1 (en) * | 1994-03-18 | 1997-01-02 | Hitachi Chemical Co., Ltd. | Semiconductor package manufacturing method and semiconductor package |
EP0692823A1 (en) * | 1994-07-11 | 1996-01-17 | Sun Microsystems, Inc. | Ball grid array package for an integated circuit |
FR2725305A1 (en) * | 1994-09-12 | 1996-04-05 | Nec Corp | LSI circuit chip package with carrier and underlying substrate |
Non-Patent Citations (3)
Title |
---|
HAWKINS G ET AL: "THE PBGA: A SYSTEMATIC STUDY OF MOISTURE RESISTANCE", INTERNATIONAL JOURNAL OF MICROCIRCUITS AND ELECTRONIC PACKAGING, vol. 18, no. 2, 1 April 1995 (1995-04-01), pages 122 - 132, XP000522299 * |
MATTHEW L: "DIE GRID ARRAY PACKAGE PROVIDES KGD SOLUTION", ELECTRONIC PACKAGING AND PRODUCTION, vol. 34, no. 6, 1 June 1994 (1994-06-01), pages 40, XP000455309 * |
YOSHITAKA FUKUOKA ET AL: "AN APPLICATION OF THE THERMAL NETWORK METHOD TO THE THERMAL ANALYSIS OF MULTICHIP PACKAGES (PROPOSAL OF A SIMPLE THERMAL ANALYSIS MODEL)", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 28, no. 9, PART 01, 1 September 1989 (1989-09-01), pages 1578 - 1585, XP000072802 * |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000005765A1 (en) * | 1998-07-22 | 2000-02-03 | Dyconex Patente Ag | Method for producing rewiring substrates for semiconductor chip packages |
WO2000022674A1 (en) * | 1998-10-14 | 2000-04-20 | Minnesota Mining And Manufacturing Company | Tape ball grid array with interconnected ground plane |
US6396141B2 (en) | 1998-10-14 | 2002-05-28 | 3M Innovative Properties Company | Tape ball grid array with interconnected ground plane |
US6462274B1 (en) | 1998-10-31 | 2002-10-08 | Amkor Technology, Inc. | Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages |
WO2001078472A1 (en) * | 2000-04-11 | 2001-10-18 | 3M Innovative Properties Company | Flexible circuit with plated cover layer and overlapping protective layer |
US6320137B1 (en) | 2000-04-11 | 2001-11-20 | 3M Innovative Properties Company | Flexible circuit with coverplate layer and overlapping protective layer |
Also Published As
Publication number | Publication date |
---|---|
US5990545A (en) | 1999-11-23 |
EP0948814B1 (en) | 2004-08-11 |
AU2435397A (en) | 1998-06-29 |
CA2272434A1 (en) | 1998-06-11 |
KR100532179B1 (en) | 2005-12-01 |
KR20000057332A (en) | 2000-09-15 |
DE69730239D1 (en) | 2004-09-16 |
CN1239589A (en) | 1999-12-22 |
ATE273564T1 (en) | 2004-08-15 |
MY119341A (en) | 2005-05-31 |
JP2001506057A (en) | 2001-05-08 |
HK1023225A1 (en) | 2000-09-01 |
EP0948814A1 (en) | 1999-10-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5990545A (en) | Chip scale ball grid array for integrated circuit package | |
US5866949A (en) | Chip scale ball grid array for integrated circuit packaging | |
US6395582B1 (en) | Methods for forming ground vias in semiconductor packages | |
EP3288077B1 (en) | Microelectronic package having a bumpless laminated interconnection layer | |
US6388340B2 (en) | Compliant semiconductor chip package with fan-out leads and method of making same | |
US9041211B2 (en) | Semiconductor package and method for manufacturing the semiconductor package embedded with semiconductor chip | |
US6985362B2 (en) | Printed circuit board and electronic package using same | |
US6849945B2 (en) | Multi-layered semiconductor device and method for producing the same | |
US20080111224A1 (en) | Multi stack package and method of fabricating the same | |
JP2003522401A (en) | Stacked integrated circuit package | |
EP1019960A1 (en) | Ball grid array semiconductor package and method for making the same | |
JP2000077563A (en) | Semiconductor device and its manufacture | |
US6441486B1 (en) | BGA substrate via structure | |
US6403460B1 (en) | Method of making a semiconductor chip assembly | |
US6432748B1 (en) | Substrate structure for semiconductor package and manufacturing method thereof | |
US6320250B1 (en) | Semiconductor package and process for manufacturing the same | |
JP3847602B2 (en) | Stacked semiconductor device, method for manufacturing the same, motherboard mounted with semiconductor device, and method for manufacturing motherboard mounted with semiconductor device | |
JP4010615B2 (en) | Semiconductor device | |
JP4115556B2 (en) | Manufacturing method of semiconductor package | |
KR19980068016A (en) | Ball Grid Array (BGA) Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof | |
JPH07326690A (en) | Package for semiconductor device and semiconductor device | |
JPH10326849A (en) | Production of bga-type semiconductor device | |
JP2000252376A (en) | Substrate unit frame for mounting ic chip | |
JP2005228967A (en) | Semiconductor package with supporting metallic reinforcing plate and tab used therefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 97180210.6 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU AM AZ BY KG KZ MD RU TJ TM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
ENP | Entry into the national phase |
Ref document number: 2272434 Country of ref document: CA |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1997920070 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 1998 525540 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1019997004813 Country of ref document: KR |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWP | Wipo information: published in national office |
Ref document number: 1997920070 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1019997004813 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1997920070 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 1019997004813 Country of ref document: KR |