WO1997048041A1 - Appareil et procede permettant de detecter et de decomprimer des instructions a partir d'un jeu d'instructions comprimees de longueur variable - Google Patents

Appareil et procede permettant de detecter et de decomprimer des instructions a partir d'un jeu d'instructions comprimees de longueur variable Download PDF

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Publication number
WO1997048041A1
WO1997048041A1 PCT/US1997/009984 US9709984W WO9748041A1 WO 1997048041 A1 WO1997048041 A1 WO 1997048041A1 US 9709984 W US9709984 W US 9709984W WO 9748041 A1 WO9748041 A1 WO 9748041A1
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WIPO (PCT)
Prior art keywords
instruction
compressed
field
repster
instructions
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Application number
PCT/US1997/009984
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English (en)
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WO1997048041A9 (fr
Inventor
Frank Worrell
Hartvig Ekner
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Lsi Logic Corporation
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Publication date
Priority claimed from US08/659,709 external-priority patent/US5794010A/en
Priority claimed from US08/659,708 external-priority patent/US5905893A/en
Priority claimed from US08/661,003 external-priority patent/US5896519A/en
Application filed by Lsi Logic Corporation filed Critical Lsi Logic Corporation
Priority to JP10501756A priority Critical patent/JP2000512409A/ja
Priority to GB9825726A priority patent/GB2329495B/en
Priority to AU34808/97A priority patent/AU3480897A/en
Publication of WO1997048041A1 publication Critical patent/WO1997048041A1/fr
Publication of WO1997048041A9 publication Critical patent/WO1997048041A9/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag

Definitions

  • TITLE AN APPARATUS AND METHOD FOR DETECTING AND DECOMPRESSING
  • This invention relates to the field of microprocessors and, more particularly, to optimization of the instruction set of a microprocessor
  • Microprocessor architectures may generally be classified as either complex instruction set computing (CISC) architectures or reduced instruction set computing (RISC) architectures
  • CISC architectures specify an instruction set comp ⁇ sing high level, relatively complex instructions
  • microprocessors implementing CISC architectures decompose the complex instructions into multiple simpler operations which may be more readily implemented in hardware
  • Microcoded routines stored in an on-chip read-only memory (ROM) have been successfully employed for providing the decomposed operations corresponding to an instruction
  • ROM read-only memory
  • hardware decoders which separate the complex instructions into simpler operations have been adopted by certain CISC microprocessor designers
  • the x86 microprocessor architecture is an example of a CISC architecture
  • RISC architectures specify an instruction set compnsing low level, relatively simple instructions Typically, each instruction within the instruction set is directly implemented in hardware Complexities asso ⁇ ated with the CISC approach are removed, allowmg for more advanced implementaUons to be designed Additionally, high frequency designs may be achieved more easily since the hardware employed to execute the instructions is simpler
  • An exemplary RISC architecture is the MIPS RISC architecture
  • variable-length instruction sets have often been asso ⁇ ated with CISC architectures while fixed-length instruction sets have been asso ⁇ ated with RISC architectures
  • Va ⁇ able-length instruction sets use dissimilar numbers of bits to encode the various instructions within the set as well as to specify addressing modes for the instructions, etc
  • va ⁇ able-length instruction sets attempt to pack instruction information as effi ⁇ ently as possible into the byte or bytes representing each instruction
  • fixed-length instruction sets employ the same number of bits for each instruction (the number of bits is typically a multiple of eight such that each instruction fully occupies a fixed number of bytes)
  • a small number of instruction formats comp ⁇ sing fixed fields of information are defined Decoding each instruction is thereby simplified to routing bits corresponding to each fixed field to logic designed to decode that field
  • va ⁇ able-length instructions lack the fixed field structure of fixed- length instructions Decoding is further complicated by the lack of fixed fields.
  • RISC architectures employing fixed-length instruction sets suffer from problems not generally applicable to CISC architectures employing variable-length instruction sets Because each instruction is fixed length, certain of the simplest instructions may effectively waste memory by occupying bytes which do not convey information concerning the instruction For example, fields which are specified as "don't care" fields for a particular instruction or instructions in many fixed-length instruction sets waste memory In contrast, va ⁇ able-length instruction
  • RISC architectures do not include the more complex instructions employed by CISC architectures
  • the number of instructions employed in a program coded with RISC instructions may be larger than the number of instructions employed in the same program coded in with CISC instructions
  • Each of the more complex instructions coded m the CISC version of the program is replaced by multiple instructions in the RISC version of the program Therefore, the CISC version of a program often occupies significantly less memory than the RISC version of the program
  • more bandwidth between devices sto ⁇ ng the program, memory, and the microprocessor is needed for the RISC version of the program than for the CISC version of the program
  • the problems outlined above are in large part solved by a microprocessor in accordance with the present invention
  • the microprocessor is configured to fetch a compressed instruction set which comp ⁇ ses a subset of a corresponding non-compressed instruction set
  • the non-compressed instruction set may be a RISC instruction set, such that the microprocessor may enjoy the high frequency operation and simpler execution resources typically asso ⁇ ated with RISC architectures Fetching the compressed instructions from memory and decompressing them within the microprocessor advantageously decreases the memory bandwidth required to achieve a given level of performance (e g instructions executed per second) Still further, the amount of memory occupied by the compressed instructions may be comparatively less than the corresponding non- compressed instructions may occupy
  • the exemplary compressed instruction set descnbed herein is a variable length instruction set
  • two distinct instruction lengths are included 16-bit and 32-bit instructions
  • the 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e g 32 bit) instruction Instructions may be fetched as 16-bit quantities
  • the succeeding 16-bit instruction is concatenated with the instruction having the extend opcode to form a 32-bit extended instruction Extended instructions have enhanced capabilities with respect to non-extended instructions, further enhancing the flexibility and power of the compressed instruction set Routines which employ the capabilities included in the extended instructions may thereby be coded using compressed instructions
  • the compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields Each value coded in the compressed register fields decompresses to a different register within the microprocessor
  • the compressed register fields compnse three bits each Therefore, eight registers are accessible to a particular instruction
  • the select instructions are assigned two opcode encodings One of the opcode encodings indicates a first mapping of repster fields, while the second opcode encoding indicates a second mapping of register fields.
  • the compressed register fields may include relatively few bits while select instructions for which access to additional registers is desired may be granted such access.
  • the register mappings are selected to minimize the logic employed to decompress register fields.
  • the compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.
  • the microprocessor supports programs having routines coded in compressed instructions and other routines coded in non-compressed instructions.
  • the subroutine call instruction within the compressed instruction set includes a compression mode which indicates whether or not the target routine is coded in compressed instructions.
  • the compression mode specified by the subroutine call instruction is captured by the microprocessor as the compression mode for the routine.
  • the compression mode is stored as one of the fetch address bits (stored in a program counter register within the microprocessor). Since the compression mode is part of the fetch address and the subroutine call instruction includes sto ⁇ ng a return address for the subroutine, the compression mode of the calling routine is automatically stored upon execution of a subroutine call instruction. When a subroutine return instruction is executed, the compression mode of the calling routine is thereby automatically restored.
  • An additional feature of one embodiment of the microprocessor is the decompression of the immediate field used for load/store instructions having the global pointer register as a base register.
  • the immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.
  • a subrange of addresses at the lower boundary of the global variable address space is thereby allocated for global variables of compressed instructions.
  • Non-compressed instructions may store global variables in the remainder of the global variable address space.
  • global variable allocation between the compressed and non- compressed routines of a particular program may be relatively simple since the subranges are separate.
  • the present invention contemplates an apparatus for executing instructions from a variable-length compressed instruction set, comprising an instruction decompressor.
  • the instruction decompressor is coupled to receive instructions which are members of the variable-length compressed instruction set, wherein the instruction decompressor is configured to examine an opcode field of a particular instruction.
  • the instruction decompressor is configured to determine that the particular instruction is an extended instruction having a first fixed length if the opcode field is coded as an extend opcode.
  • the instruction decompressor is configured to determine that the particular instruction is a non-extended instruction if the opcode field is coded as a second opcode different than the extend opcode.
  • the present invention further contemplates a method for expanding compressed instructions into decompressed instructions.
  • a compressed instruction is determined to be an extended instruction having a first fixed length if an opcode field of the compressed instruction is an extend opcode. If the opcode field of the compressed instruction is a second opcode different than the extend opcode, the compressed instruction is a non-extended instruction having a second fixed length.
  • the compressed instruction is decompressed into a decompressed instruction.
  • a number of bytes included in the compressed instruction is defined by the first fixed length if the compressed instruction is an extended instruction. Alternatively, the number of bytes is defined by the second fixed length if the compressed instruction is a non-extended instruction.
  • the present invention still further contemplates an apparatus for expanding compressed instructions into decompressed instructions, comprising a first determining means, a second determining means, and a decompressing means.
  • the first determining means determines that a compressed instruction is an extended instruction having a first fixed length if an opcode field of the compressed instruction is an extend opcode
  • the second determining means dete ⁇ mnes that the compressed instruction is a non-extended instruction having a second fixed length if the opcode field of the compressed instruction is a second opcode different than the extend opcode
  • the decompressing means decompresses the compressed instruction into a decompressed instruction A number of bytes included in the compressed instruction is defined by the first fixed length if the compressed instruction is the extended instruction Alternatively, the number of bytes is defined by the second fixed length if the compressed instruction is the non-extended instruction
  • the present invention yet further contemplates a method for executing a program including a first routine and a second routine m a microprocessor
  • a subroutine call instruction is executed within the first routine, wherein the subroutine call instruction indicates that the second routine is to be executed via a target address of the subroutine call instruction
  • An indication within the subroutine call instruction is examined If the indication is in a first state, the second routine is determined to be coded using compressed instructions The second routine is determined to be coded using non-compressed instructions if the indication is in a second state different than the first state
  • the present invention contemplates an apparatus for executing a program including a first routine and a second routine in a microprocessor, comp ⁇ sing an executing means and an examining means
  • the executing means executes a subroutine call instruction within the first routine
  • the subroutine call instruction indicates that the second routine is to be executed via a target address of the subroutine call instruction
  • the examining means examines an indication within the subroutine call instruction
  • the present invention still further contemplates an apparatus for fetching compressed and non- compressed instructions m a microprocessor, comprising a storage device and a mode detector
  • the storage device stores a compression enable indicator Coupled to the storage device
  • the mode detector is configured to detect a compression mode of a target routine upon fetch of a subroutine call instruction specifying the target routine
  • the mode detector is configured to convey the compression mode to a processor core
  • the processor core is configured to fetch compressed instructions if the compression mode indicates compressed
  • the processor core is configured to fetch non-compressed instructions if the compression mode indicates non-compressed
  • the present invention yet further contemplates a microprocessor comp ⁇ sing an instruction decompressor and a processor core
  • the instruction decompressor is coupled to receive compressed instructions which are members of a va ⁇ able-length compressed instruction set
  • the instruction decompressor is configured to decompress each received compressed instruction into a corresponding decompressed instruction.
  • the processor core is configured to execute the decompressed instructions
  • the present invention additionally contemplates a method for executing instruction code
  • Compressed instructions are fetched, wherein the compressed instructions are members of a va ⁇ able-length compressed instruction set
  • the compressed instructions are decompressed m an instruction decompressor, thereby forming co ⁇ esponding decompressed instructions
  • the decompressed instructions are executed in a processor core
  • the present invention still further contemplates an apparatus for executing instruction code, comprising a fetching means, a decompressing means, and an executing means
  • the fetching means fetches compressed instructions which are members of a va ⁇ able-length compressed instruction set
  • the decompressmg means decompresses the compressed instructions, thereby forming co ⁇ esponding decompressed instructions
  • the executing means executes the decompressed instructions
  • the present invention contemplates an instruction decompressor configured to decompress compressed instructions A first one of the compressed instructions is codable to access a first subset of registers defined for a corresponding non-compressed instruction set Additionally, a second one of the compressed instructions is codable to access the first subset of registers and is further codable to access a second subset of registers
  • the present invention further contemplates a method for decompressing compressed instructions A particular compressed instruction having a first register field is decompressed using a first register mapping from compressed register indicators to decompressed register indicators if the particular compressed instruction is encode
  • the present invention contemplates an apparatus for decompressing a compressed register field of a compressed instruction into a decompressed repster field of a decompressed instruction, comprising a first means and a second means
  • the first means is for directly copying at least a portion of the compressed register field into a portion of the decompressed register field
  • the first means is coupled to receive the compressed repster field
  • the second means is for lopcally operating upon the compressed repster field to produce a remaining portion of the decompressed register field
  • the present invention contemplates an instruction decompressor configured to decompress a compressed repster field of a compressed instruction into a decompressed repster field of a decompressed instruction
  • the instruction decompressor forms a first portion of the decompressed repster field by copying at least a portion of the compressed repster field thereto
  • the instruction decompressor includes a lope block which is configured to operate upon the compressed repster field to produce a remaining portion of the decompressed repster field
  • Fig 1 is a block diagram of one embodiment of a microprocessor
  • Fig 2 is a block diagram of a second embodiment of a microprocessor
  • Fig 3 A is a first instruction format supported by one embodiment of the microprocessors shown in
  • Fig 3B is a second instruction format supported by one embodiment of the microprocessors shown in
  • Fig 3C is a third instruction format supported by one embodiment of the microprocessors shown in
  • Fig 3D is a fourth instruction format supported by one embodiment of the microprocessors shown in
  • Fig 4 A is a fifth instruction format supported by one embodiment of the microprocessors shown in
  • Fig 4B is a sixth instruction format supported by one embodiment of the microprocessors shown in Figs 1 and 2
  • Fig 4C is a seventh instruction format supported by one embodiment of the microprocessors shown in
  • Fig 4D is an eight instruction format supported by one embodiment of the microprocessors shown in
  • Figs 5A, 5B, 5C, 5D, and 5E are tables of exemplary instructions using the formats shown in Figs 3A, 3B, 3C, and 3D
  • Figs 6A, 6B, 6C, 6D, 6E, and 6F are tables of exemplary instructions using the formats shown in
  • Fig. 7 is a diagram depicting offsets from an arbitrary register and a global pointer register, according to one embodiment of the microprocessors shown in Figs. 1 and 2.
  • Fig. 8 is a block diagram of exemplary hardware for expanding an immediate field from a compressed instruction to a decompressed instruction.
  • Fig. 9 is a diagram depicting decompressed offsets in accordance with one embodiment of the microprocessors shown in Figs. 1 and 2.
  • Fig. 10 is a flow chart depicting operation of a decompressor for immediate fields according to one embodiment of the microprocessors shown in Figs. 1 and 2.
  • Fig. 11 is a block diagram of exemplary hardware for generating fetch addresses according to one embodiment of the microprocessors shown in Figs. 1 and 2.
  • Fig. 12 is a block diagram showing register decompression logic employed in one embodiment of the microprocessors shown in Figs. 1 and 2.
  • Fig. 13 is a block diagram of an exemplary computer system including the microprocessor for which embodiments are shown in Figs. 1 and 2.
  • Mi ⁇ oprocessor 10A includes an instruction decompressor 12A, an instruction cache 14A, and a processor core 16.
  • Instruction decompressor 12A is coupled to receive instruction bytes from a main memory subsystem (not shown).
  • Instruction decompressor 12A is further coupled to instruction cache 14A.
  • Instruction cache 14A is coupled to processor core 16.
  • mi ⁇ oprocessor 10A is configured to fetch compressed instructions from the main memory subsystem.
  • the compressed instructions are passed through instruction decompressor 12A, which expands the compressed instructions into decompressed instructions for storage within instruction cache 14 A.
  • Many of the compressed instructions occupy fewer memory storage locations than the corresponding decompressed instructions, advantageously reducing the amount of memory required to store a particular program.
  • the bandwidth required to transport the compressed instructions from the main memory subsystem to miCToprocessor 10A is reduced
  • Microprocessor 10 A may be employed within a computer system having a relatively small main memory Relatively large programs may be stored in the mam memory due to the compression of instructions stored therein
  • mi ⁇ oprocessor 10A is configured to execute both compressed and non- compressed instructions on a routme-by-routine basis
  • a routine may be coded using either compressed instructions or non-compressed instructions
  • routines which may not be effi ⁇ entlv coded in the compressed instruction set may be coded using non-compressed instructions, while routines which are effi ⁇ ently coded in the compressed instruction set are so coded
  • Microprocessor 10A may support a particular decompression of the immediate field for load/store instructions using the global pointer register as a base register, in order to support mixing of compressed and non-compressed instructions The particular decompression is detailed further below
  • a compression mode is detected bv instruction decompressor 12A The compression mode identifies the instruction set in which a routine is coded compressed or non-compressed
  • Instruction compression is achieved in mi ⁇ oprocessor 10A by imposing certain limitations upon the available instruction encodings
  • instruction field sizes may be reduced (i e the number of bits within an instruction field may be decreased)
  • the number of available registers may be reduced to form the compressed instruction set
  • a smaller field may be used to encode the repsters used as source and destination operands for the instruction Instruction decompressor 12 A expands the encoded repster field into a decompressed repster field
  • the decompressed repster field is included in the decompressed instruction
  • the compressed instructions use the reduced instruction fields, thereby occupying less memory (1 e fewer bits) than the onpnal instruction encodings defined by the microprocessor architecture employed by processor core 16
  • Instruction decompressor 12 A is configured to accept compressed instructions and to decompress the instructions into the onpnal instruction encodings Each instruction field within a particular compressed instruction is expanded from the compressed field to a corresponding decompressed field within the corresponding decompressed instruction The decompressed instruction is coded in the onpnal instruction format supported by processor core 16
  • Processor core 16 includes circuitry for fetching instructions from instruction cache 14A, decoding the instructions, and executing the instructions
  • the instructions supported by processor core 16 are specified by the mi ⁇ oprocessor architecture employed therein
  • processor core 16 employs the MIPS RISC architecture
  • processor core 16 may employ any mi ⁇ oprocessor architecture Since instruction decompressor 12A decompresses instructions into the onpnal instruction format, processor core 16 may comprise a previously designed processing core In other words, the processmg core mav not require substantial modification to be included within mi ⁇ oprocessor 10A
  • the MIPS RISC architecture specifies an instruction set comprising 32 bit fixed-length instructions
  • a compressed instruction set is defined for mi ⁇ oprocessor 10A which compnses va ⁇ able-length instructions Many of the compressed instructions compnse 16-bit instructions Other compressed instructions comp ⁇ sed 32 bit instructions in conjunction with the extend instruction descnbed below Several 16-bit and 32-bit instruction formats are defined It is understood that, although 16-bit and 32-bit compressed instructions are used in this embodiment, other embodiments may employ different instruction lengths
  • the compressed instructions encode a subset of the non-compressed instructions Instruction encodings supported within the compressed instruction set compnse many of the most commonly coded instructions as well as the most often used registers, such that many programs, or routines within the programs, may be coded using the compressed instructions
  • mi ⁇ oprocessor 10A employs a compression mode If the compression mode is active, then compressed instructions are being fetched and executed Instruction decompressor 12A decompresses the instructions when they are transferred from main memory to instruction cache 14
  • the compressed mode may be inactive When the compression mode is inactive, non-compressed instructions are being fetched and executed Instruction decompressor 12A is bypassed when the compressed mode is inactive
  • the compression mode is indicated by a bit within the fetch address (e g bit 0)
  • the current fetch address may be stored in a PC register 18 within processor core 16 Bit 0 of PC register 18 indicates the compression mode (CM) of mi ⁇ oprocessor 10A
  • instruction cache 14A is a high speed cache memory configured to store decompressed and non- compressed instructions
  • a set associative or direct mapped configuration may be suitable for the embodiment shown in Fig 1
  • Mi ⁇ oprocessor 10B includes an instruction cache 14B coupled to receive instruction bytes from the mam memory subsystem, an instruction decompressor 12B, and processor core 16 Instruction cache 14B is coupled to instruction decompressor 12B, which is further coupled to processor core 16
  • Microprocessor 10B is configured with instruction decompressor 12B between instruction cache 14B and processor core 16
  • Instruction cache 14B stores the compressed instructions transferred from the mam memory subsystem In this manner, instruction cache 14B may store a relatively larger number of instructions than a similarly sized instruction cache employed as instruction cache 14A in mi ⁇ oprocessor 10A
  • Instruction decompressor 12B receives fetch addresses co ⁇ esponding to instruction fetch requests from processor core 16, and accesses instruction cache 14B in response to the fetch request The corresponding compressed instructions are decompressed into decompressed instructions by instruction decompressor 12B The decompressed instructions are transmitted to processor core 16
  • mi ⁇ oprocessor 10B includes a compression mode in one embodiment Instruction decompressor 12B is bypassed when non-compressed instructions are being fetched and executed
  • instruction cache 14B stores both compressed and non-compressed instructions
  • instruction cache 14B typically stores instruction bytes in fixed-size storage locations referred to as cache lines Therefore, a particular cache line may be stonng compressed or non- compressed instructions In either case, a plurality of instruction bytes are stored Therefore, instruction caches 14A and 14B may be of similar construction
  • the compression mode at the time a cache line is accessed determines whether the instruction bytes are interpreted as compressed or non-compressed instructions
  • An alternative configuration for mi ⁇ oprocessor 10B is to include instruction decompressor 12B within the instruction decode lope of processor core 16 The compressed instructions may not actually be decompressed in such an embodiment Instead, the compressed instructions may be decoded directly by the decode lope The decoded instructions may be similar to the decoded instructions generated for the non- compressed instructions which correspond
  • mi ⁇ oprocessor 10 which operates upon compressed instructions
  • instruction cache 14 and instruction decompressor 12 will be used to refer to the corresponding elements of both Figs. 1 and 2 as well as other embodiments of the elements included in other implementations of mi ⁇ oprocessor 10.
  • compressed instruction refers to an instruction which is stored in a compressed form in memory.
  • the compressed instruction is generally stored using fewer bits than the number of bits used to store the instruction when represented as defined in the mi ⁇ oprocessor architecture employed by processor core 16.
  • decompressed instruction refers to the result of expanding a compressed instruction into the original encoding as defined in the mi ⁇ oprocessor architecture employed by processor core 16.
  • non- compressed instruction refers to an instruction represented in the encoding defined by the mi ⁇ oprocessor architecture employed by processor core 16.
  • Non-compressed instructions are also stored in memory in the same format (i.e. non-compressed instructions were never compressed).
  • decompression refers to the process of expanding a compressed instruction into the corresponding decompressed instruction.
  • instruction decompressors 12A and 12B may be configured to simultaneously decompress multiple compressed instructions. Such embodiments of instruction decompressors 12 may be employed with embodiments of processor core 16 which execute multiple instructions per clock cycle.
  • Figs. 3A-3D and 4A-4D depict exemplary instruction formats for 16-bit and 32-bit compressed instructions, respectively, according to one specific embodiment of mi ⁇ oprocessor 10 employing the MIPS RISC architecture. Other instructions formats may be employed by other embodiments.
  • the instruction formats shown in Figs. 3 A-3D each comprise 16 bits in this particular implementation.
  • the instruction formats shown in Figs. 4A-4D each comprise 32 bits in this particular implementation.
  • the compressed instructions encoded using the instruction formats are decompressed into instruction formats as defined by the MIPS RISC architecture for each instruction.
  • Fig. 3 A depicts a first instruction format 20.
  • Instruction format 20 includes an opcode field 22, a first register field 24, a second register field 26, and a function field 28.
  • Opcode field 22 is used to identify the instruction.
  • function field 28 is used in conjunction with certain particular encodings of opcode field 22 to identify the instruction. Effectively, function field 28 and opcode field 22 together form the opcode field for these instructions.
  • function field 28 is used as an immediate field.
  • First register field 24 and second register field 26 identify destination and source registers for the instruction. The destination register is also typically used as a source register for the instruction.
  • first repster field 24 and second repster field 26 two source operands and one destination operand are specified via first repster field 24 and second repster field 26.
  • the notations "RT” and "RS" in first repster field 24 and second repster field 26 indicate the use of the fields in the instruction tables below. Either RT or RS may be a destination repster, depending upon the encoding of the instruction.
  • opcode field 22 comprises 5 bits
  • first register field 24 and second register field 26 comprise 3 bits each
  • function field 28 comprises 5 bits.
  • First register field 24 is divided into two subfields (labeled RT1 and RT0).
  • RT1 comprises two bits in the present embodiment, while RT0 comprises one bit.
  • RT1 is concatenated with RT0 to form first register field 24.
  • Subfield RT1 and second register field 26 are used in certain instructions encoded via instruction format 20 to indicate one of the 32 registers defined by the MIPS RISC architecture.
  • Fig. 3B depicts a second instruction format 30.
  • Instruction format 30 includes opcode field 22, first repster field 24, and second repster field 26 Additionally, a third repster field 32 and a function field 34 are shown Third repster field 32 is generally used to identify the destination repster for instructions using instruction format 30 Therefore, first repster field 24 and second repster field 26 compnse source repsters for instruction format 30 Function field 34 is used similar to function field 28 In the embodiment shown, third repster field 32 comp ⁇ ses three bits and function field 34 compnses two bits
  • a third instruction format 40 is shown in Fig 3C
  • Instruction format 40 includes opcode field 22 and second register field 26, as well as an immediate field 42 Immediate field 42 is used to provide immediate data for the instruction specified by instruction format 40
  • Immediate data is an operand of the instruction, similar to the value stored in a repster specified by first repster field 24 or second repster field 26
  • an add instruction which uses immediate data adds the immediate data to the value stored in the destination repster, and stores the resulting sum into that destination repster
  • immediate field 42 comp ⁇ ses eight bits Immediate field 42 is divided into two subfields (DMM1 and IMM0) in the instruction format shown m Fig 3C
  • the subfields allow second register field 26 to be placed in the same bit positions within instruction format 40 as it is placed in instruction formats 20 and 30
  • second register field 26 is always found m the same position of 16-bit instructions in which it is used Therefore, subfield IMM1 comprises 2 bits and subfield DMM0 compnses 6 bits EvTMl is concat
  • Fig 3D depicts a fourth instruction format 50
  • Instruction format SO includes opcode field 22 and an immediate field 52
  • Immediate field 52 similar to immediate field 42, is used as an operand of the instruction
  • immediate field 52 comp ⁇ ses 11 bits
  • Fig 4A depicts a fifth instruction format 60
  • Instruction format 60 includes opcode field 22, which is coded as the extend instruction Instruction decompressor 12 recognizes the extend instruction opcode within opcode field 22 and treats the current instruction as a 32-bit instruction (I e the 16 bits included m the instruction containing the extend opcode and the 16 bits which would otherwise compnse the next instruction m program order are concatenated to form a 32 bit instruction) Therefore, the compressed instruction can be seen to be a va ⁇ able-length instruction set compnsing 16-bit instructions and 32-bit instructions
  • Instruction format 60 further includes a zero field 62 comprising six bits (coded to all binary zeros), an immediate field 64, and a BR field 66 Instruction format 60 is used to code an extended form of the BR instruction (an unconditional branch instruction), and hence BR field 66 is an opcode field indicating the BR instruction
  • the BR opcode is hexadecimal 02
  • the extended BR instruction has a larger immediate field than the non-extended BR instruction, and therefore may be coded with larger offsets than the non-extended BR instruction
  • the extended BR instruction may be used
  • branches to close instructions may use the non-extended BR instruction
  • Immediate field 64 compnses 16 bits which are used as an offset to be added to the address of the instruction following the BR instruction to create the target address of the branch instruction
  • the non-extended BR instruction by contrast, includes an eleven bit offset (l e it is coded using instruction format 50)
  • Fig 4B depicts an instruction format 70 which is an extended version of instruction format 40
  • Instruction format 70 includes opcode field 22 coded as the extend opcode, as well as an immediate field 72, a first repster field 74, a second repster field 76, and a second opcode field 78
  • First repster field 74 and second repster field 76 compnse five bits each in the embodiment shown Therefore, any repster defined by the MIPS RISC architecture may be accessed using instruction format 70
  • Second opcode field 78 defines the instruction being executed, and compnses 5 bits (similar to opcode field 22)
  • immediate field 72 compnses 12 bits divided into a one bit DMM2 subfield, a five bit IMM1 subfield, and a six bit DMMO subfield Immediate field 72 is formed by concatenating IMM2 with DMM1 and further with IMMO in the embodiment shown
  • An extended instruction format corresponding to instruction format 30 is shown in Fig 4C as an instruction format 80
  • Second opcode field 78 is coded to a particular value to identify instruction format 80 from instruction format 70
  • instruction format 80 is assumed by instruction decompressor 12
  • instruction format 70 is assumed by instruction decompressor 12
  • the particular value compnses hexadecimal 00
  • Instruction format 80 further includes a COP0 bit 86 COP0 bit 86, when set, indicates that certain coprocessor zero instructions (as defined m the MIPS RISC architecture) are being executed
  • the tables of instructions below further define the instructions encoded by setting COP0 bit 86
  • the instructions defined for instruction formats 20, 30, 40, and 50 are capable of performing many of the operations commonly performed in typical programs However, routines may need to perform operations of which these instructions are incapable While most of the instructions in the routine may be coded using instruction formats 20-50, several instructions may require additional encodings For example, access to a repster not included within the subset of available repsters in formats 20-50 may be needed Additional instructions not included in the instructions encoded using formats 20-50 may be needed For these and other reasons, the extend opcode and extended instruction formats 60-80 are defined
  • Instruction decompressor 12 examines opcode field 22 in order to detect the extend opcode
  • the extend opcode is one of the opcodes defined to use instruction format 50 in the present embodiment, although the bits mcluded in immediate field 52 are assigned diffe ⁇ ng interpretations depending upon the extended instruction format coded for the particular extended instruction
  • the extended instruction formats include a second opcode field (e g fields 66 and 78) which identify the particular extended instruction
  • Addition of the extend opcode and extended instruction formats allows for many instructions to be encoded using the na ⁇ ower instruction formats 20-50, but still have the flexibility of the wider extended instruction formats when desired Programs which occasionally make use of the functionality included in the extended instruction formats may still achieve a reduced memory footp ⁇ nt, since these programs may be encoded using compressed instructions and many of the compressed instructions may comprise 16-bit compressed instructions
  • An embodiment of mi ⁇ oprocessor 10 may handle the extended instructions by fetching 16-bit instruction portions and detecting the extend opcode When the extend opcode is detected, a NOP may be transmitted to processor core 16 and the remaining 16-bit portion of the extended instruction may be fetched
  • the extended instruction is decompressed and provided as the next instruction after the NOP
  • instruction decompressor 12 handles cases wherein a portion of the extended instruction is available while a second portion is unavailable For example, two portions of the extended instruction may he within two distinct cache lines within instruction cache 14 Therefore, one portion of the instruction may be fetched from instruction cache 14 while the other portion may not reside within instruction cache 14 The portion mav then need to be stored within instruction decompressor 12 until the remaining portion is available.
  • Fig 4D is an instruction format 90 used to exph ⁇ tly expand the JAL instruction of the MIPS
  • the JAL instruction is often used as a subroutine call instruction
  • Subroutines may be stored m memory at a great distance (address-wise) from the calling routine Therefore, having the largest possible range of relative offsets (via an immediate field 92 comp ⁇ sing 26 bits) is important for the JAL instruction.
  • an exchange bit 94 is mcluded in the instruction encoding
  • the exchange bit is used to indicate the compressed/non-compressed nature of the instructions at the target address If the bit is set, the target instructions are compressed instructions If the bit is clear, the target instructions are non-compressed instructions
  • the value of exchange bit 94 is copied mto bit 0 of the program counter within processor core 16 Bit 0 of the program counter may always be assumed to be zero, since the sixteen bit and thirty-two bit instructions occupy at least two bytes each and instructions are stored at aligned addresses Therefore bit zero is a useful location for sto ⁇ ng the compression mode of the current routine
  • Processor core 16 increments fetch addresses by 2 (instead of 4) when bit 0 is set, thereby fetching 16 bit compressed instructions through instruction decompressor 12
  • Each instruction within the compressed instruction set employed by mi ⁇ oprocessor 10 uses at least one of the instruction formats shown in Figs 3 A-3D and Figs 4 A-4D It is noted that opcode field 22 is included in each instruction format, and is located in the same place within each instruction format The coding of opcode field 22 determines which instruction format is used to interpret the remainder of the instruction. A first portion of the opcode field encodings is assigned to instruction format 20, a second portion of the opcode field encodings is assigned to instruction format 30, etc
  • instruction field refers to one or more bits within an instruction which are pouped and assigned an interpretation as a poup
  • opcode field 22 is compnses a group of bits which are interpreted as the opcode of the instruction
  • first and second repster fields 24 and 26 comprise register identifiers which identify a storage location within processor core 16 which store operands of the instruction
  • immediate field refers to an instruction field in which immediate data is coded Immediate data may provide an operand for an instruction Alternatively, immediate data mav be used as an offset to be added to a repster value, thereby produ ⁇ ng an address Still further, immediate data may be used as an offset for a branch instruction
  • Figs 5A-6F are tables listing an exemplary compressed instruction set for use by one particular implementation of mi ⁇ oprocessor 10
  • the particular implementation employs the MIPS RISC architecture within processor core 16 Therefore, the instruction mnemonics listed in an instruction column 100 of the tables correspond to instruction mnemonics defined in the MIPS RISC architecture (or defined for the instruction assembler, as descnbed m "MIPS RISC Architecture" by Kane and Heinnch, Appendix D, Prentice Hall PTR. Upper Saddle River, New Jersey, 1992, incorporated herein by reference) with the following exceptions CMPI, MOVEI, MOVE, NEG, NOT. and extend These instructions translate to the following MIPS instructions (RS and RT refer to the 16-bit RS and RT)
  • MOVI ADDIU RS $0, s ⁇ mm8 MOV ADD RS, $0, RT
  • first repster field 24, second repster field 26, and third repster field 32 comprise three bits each.
  • Table 1 lists the mapping of the field encodings (listed in binary) to registers in the MIPS RISC architecture for these symbols. Other mappings are also contemplated, as shown further below. Names assigned according to MIPS assembler convention are also listed in Table 1.
  • register fields 24, 26, or 32 are available for use in compressed instructions having registers fields 24, 26, or 32. Because each register field is three bits, only eight registers are available for a given opcode. Instructions which may access all sixteen registers are assigned two opcodes in the instruction tables below. Repster selection is thereby a function of both a repster field and opcode field 22.
  • register fields may be encoded using fewer bits while still providing select instructions which may access a large poup of registers.
  • immediate field decompression for load/store instructions comprises right rotation of the immediate bits by one bit for halfwords and two bits for words, followed by shifting of the immediate bits left by one bit for halfwords and two bits for words.
  • a seven bit immediate field is provided for words and a six bit immediate field for halfwords (in the 16-bit instruction formats).
  • the MIPS RISC architecture defines that data addresses corresponding to load/store instructions are aligned for each instruction included in the exemplary compressed instruction set. Therefore, the least significant bit (for halfwords) and the second least significant bit (for words) may be set to zero. Bits in the compressed immediate field need not be used to specify these bits. Finally, "imm" is post-fixed with a number indicating the number of bits included in the immediate field
  • Opcode field 22 and function field 28 are decompressed as well More particularly, opcode field 22 and function field 28 identify the instruction within the MIPS RISC architecture, in accordance with the tables shown m Figs 5 A-6F The opcode and function fields of the decompressed instructions are coded in accordance with the MIPS RISC architecture definition
  • Figs 5 A and 5B depict a table 110 and a table 112, respectively Tables 110 and 112 list instructions from the exemplary compressed instruction set which use instruction format 20 shown in Fig 3 A Instruction column 100 and operands column 102 are included, as well as an opcode column 106 and a function column 104 Opcode column 104 and function column 106 include hexadecimal numbers, and correspond to opcode field 22 and function field 28, respectively
  • Table 110 includes several instructions which have an " ⁇ mm5" coding m function column 104
  • the " ⁇ mm5" coding appears for the load/store instructions within table 110, and indicates that function field 28 is used as an immediate field for these instructions
  • function field 28 is used in conjunction with opcode field 22 to identify a particular instruction within the compressed instruction set
  • opcode Id is labeled as special m table 110
  • the special instructions have a specific interpretation of function field 28 In particular, if the most significant bit of the function field is clear, then the instruction is defined to be
  • the low order two bits of the s ⁇ mm9 operand are set to zero
  • the destination of the SLT and SLTU instructions shown m table 110 is the t8 register (repster $24) according to one embodiment
  • Table 112 shows an "lmroJ" and " ⁇ mm6" operand for several instructions
  • the ⁇ mm3 operand is coded into second repster field 26, and the " ⁇ mm6" operand is coded into both second repster field 26 and first repster field 24
  • table 112 includes the jump repster (JR) instruction, having second repster field 26 as an operand
  • JR jump repster
  • subfield RT1 of first repster field 24 is used m conjunction with second repster field 26 to specify any of the MIPS RISC architecture repsters for the JR instruction
  • Table 114 lists instructions from the exemplary instruction set which use instruction format 30 shown in Fig 3B Certain instructions within table 114 have hardcoded destination repsters (l e the destination repsters cannot be selected by the programmer, other than by using a different opcode) For these instructions, third repster field 32 is combined with function field 34 to store the function field encoding shown m function column 104 Additionally, an instruction is shown which has an immediate operand in function column 104 and operands column 102 This instruction uses second repster field 26 in conjunction with function field 34 to code the corresponding immediate field used by the instruction
  • Figs 5D and 5E are tables 116 and 118 showing the instructions from the exemplary compressed instruction set which employ instruction formats 40 and 50, respectively It is noted that the extend instruction is shown in table 118 However, the extend instruction actually indicates that the instruction is a 32-bit compressed instruction which uses one of instruction formats 60, 70, or 80
  • Tables 120 and 122 depict those instructions from the exemplary compressed instruction set which are encoded using instruction format 70, shown in Fig 4B
  • Table 120 includes instruction column 100 and operands column 102, and further includes an opcode column 108
  • Opcode column 108 is similar to opcode column 106, except that the opcode encodings shown in opcode column 108 correspond to opcode field 78
  • Table 122 includes an RT column 109 which co ⁇ esponds to first repster field 74
  • the coding of the RT field in the instructions shown in table 122 indicates which instruction is selected
  • the instructions shown m table 122 share a specific encoding in opcode field 78 In one embodiment, the specific encoding is 00 (hexade ⁇ mal)
  • Figs 6C, 6D, 6E, and 6F are tables 124, 126, 128, and 130 which depict instructions from the exemplary compressed instruction set which are encoded according to instruction format 80
  • Tables 124, 126, and 130 include a function column 107 which co ⁇ esponds to encodings of function field 84
  • Table 128 includes an RS, RT column 105 which will be explained in more detail below
  • Operands column 102 for table 124 includes immediate operands for certain instructions The
  • the instructions listed in table 128 are identified via encodings of second repster field 76, as shown in RS, RT column 105 Certain instructions are identified via second repster field 76 in conjunction with first repster field 74 Those instructions for which RS, RT column 105 includes an asterisk for the RT portion are identified via second repster field 76, while those instructions for which RS, RT column 105 does not include an asterisk are identified by second repster field 76 in conjunction with first repster field 74 Instructions which are not identified via first repster field 74 may use first repster field 74 to encode an operand
  • the instructions listed in tables 128 and 130 are instructions for which COP0 bit 86 is set, while instructions listed m tables 124 and 126 are encoded with COP0 bit 86 clear
  • Certain instructions in table 128 include an " ⁇ mm6" operand
  • the " ⁇ mm6" operand is coded into function field 84
  • function field 84 is used to indicate the instructions shown in table 130 when second repster field 76 is coded to lx (hexadecimal), wherein "x" indicates that the low order bits are don't cared.
  • a first addressing window 150 and a second addressing window 152 are shown according to one embodiment of microprocessor 10.
  • a base register represented as Reg. on the left side of addressing window 150.
  • the value of the base register identifies an address within the main memory subsystem.
  • Addressing window 150 represents the range of addresses around the value of the base register which are accessible to a load/store instruction in the non- compressed instruction set according to one embodiment of the non-compressed instruction set.
  • the non- compressed instruction set specifies that load/store instructions form the address of a memory operand via the sum of a value stored in a base register and a sixteen bit signed immediate field.
  • the range of addresses has an upper boundary of 32767 greater than the base register and a lower boundary of 32768 less than the base register.
  • Other embodiments may include larger or smaller ranges.
  • the term "base register” refers to a register which is specified by a load/store instruction as storing a base address, to which the signed immediate field is added to form the address of the memory operand operated upon by the instruction.
  • load/store instructions within the 16-bit portion of the exemplary compressed instruction set include a five bit immediate field. This field is rotated right two bits and then shifted left two bits for word-sized memory operands, forming a seven bit immediate field (the largest of the immediate fields which may be formed using the five bits, according to one embodiment). The seven bit immediate field is then zero extended to form a positive offset from the base register in the co ⁇ esponding decompressed instruction.
  • a subrange 154 of addresses are therefore available for access by compressed instructions. Within addressing window 150, subrange 154 has an upper boundary of 127 peater than the base repster and a lower boundary of the base repster. However, subrange 154 may vary in size from embodiment to embodiment.
  • the global pointer register is a register assigned by software convention to locate an area of memory used for storing global variables.
  • a global variable is a variable which is available for access from any routine within a program.
  • a local variable is typically accessible only to a particular routine or poup of routines.
  • repster $28 is often used as the global pointer register.
  • the area of memory around the global pointer register may therefore be viewed as a table of global variables.
  • Each global variable is assigned an offset within the table.
  • the offset co ⁇ esponds to a particular immediate field value which may be added to the global pointer register in order to locate the global variable.
  • a 64 kilobyte table may be allocated for global variables as shown along the left side of addressing windows 150 and 152.
  • the global variable table includes a section which is accessible to compressed instructions (corresponding to subrange 154) which is between two subranges 156 and 158 accessible to non-compressed instructions.
  • mi ⁇ oprocessor 10 may support programs in which some routines are coded with non-compressed instructions while other routines are coded with compressed instructions. Allocating global variables in a particular propam is complicated by the division of the non-compressed global variable subranges 156 and 158 of addressing window 150. Global variables may be allocated into subrange 158, for example, and then global variable allocation must continue in subrange 156 (for non-compressed instructions). In other words, subrange 154 must be bypassed for global variables accessible to non-compressed instructions.
  • Mi ⁇ oprocessor 10 may employ a decompression of the compressed immediate field for load/store instructions using the global pointer (GP) register which leads to addressing window 152.
  • Addressing window 152 includes a subrange 160 accessible to compressed instructions and a subrange 162 accessible to non- compressed instructions.
  • subrange 162 is a contiguous block of memory.
  • Global variables for access by non-compressed instructions may be allocated into subrange 162, while global variables for access by compressed instructions may be allocated into subrange 160.
  • subrange 160 and subrange 162 form distinct tables of global variables for access by compressed and non-compressed instructions, respectively.
  • Addressing window 152 is achieved by decompressing the compressed immediate field as described above, except that the most significant bit of the decompressed immediate field is set.
  • the decompressed immediate field is 8000 (in hexadecimal). Since the decompressed immediate field is interpreted as a signed field for load/store instructions, the 8000 value is the most negative number available in the decompressed immediate field. Other encodings of the compressed immediate field are decompressed into negative numbers which form subrange 160. Subrange 160 forms the lower boundary of the range of addresses represented by addressing window 152 as shown in the embodiment of Fig. 7.
  • memory operand refers to a value stored in a memory location within the main memory subsystem. Load instructions may be used to transfer the memory operand to a register within mi ⁇ oprocessor 10. Conversely, store instructions may be used to transfer a value stored in a register into the memory operand storage location.
  • a memory operand may be of various sizes (i.e. numbers of bytes). In one embodiment, three sizes are available: byte, halfword, and word. A halfword comprises two bytes, and a word comprises four bytes. Other memory operand sizes are contemplated for other embodiments.
  • FIG. 8 a block diagram of exemplary hardware within instruction decompressor 12 for decompressing the immediate field of a load/store instruction is shown. It is noted that multiple copies of the exemplary hardware shown in Fig. 8 may be employed to concurrently decompress multiple load/store instructions.
  • the exemplary hardware shown in Fig. 8 is described in terms of microprocessor 10B. However, similar hardware may be employed within mi ⁇ oprocessor 10 A.
  • the exemplary hardware includes a immediate field decompressor 170 and a register decoder 172.
  • the compressed immediate field comprises function field 28 (shown in Fig. 3A).
  • the base register field for the compressed load/store instruction is conveyed upon a base repster bus 176.
  • the base register field comprises second register field 26.
  • Repster decoder 172 decodes the repster identified upon base repster bus 176. If the base register is the global pointer register, repster decoder 172 asserts a GP signal upon GP line 178 to immediate field decompressor 170. Otherwise, register decoder 172 deasserts the GP signal. Immediate field decompressor 170 decompresses the compressed immediate field in one of two ways, dependent upon the GP signal. If the GP signal is deasserted, then immediate field decompressor 170 clears the most significant bit of the decompressed immediate field.
  • immediate field decompressor 170 sets the most significant bit of the immediate field if the GP signal is asserted Therefore, a positive offset is ⁇ eated when a register other than the global pointer repster is used as the base repster A negative offset is created when the global pointer repster is used as the base repster
  • Immediate field decompressor 170 conveys the decompressed immediate field upon a decompressed immediate bus 180
  • Fig 9 illustrates the decompressed immediate field generated for load/store instructions according to one embodiment of the exemplary compressed instruction set
  • the compressed immediate field of load/store instructions which do not employ the global pointer repster as the base repster are decompressed as indicated by reference number 182
  • the decompression for bytes, halfwords, and words are shown separately, with each bit position of the decompressed immediate field (or offset) represented by a numencal dipt or an "L" Bits from the compressed immediate field are shown in the respective bit locations of the decompressed field via the numencal dipts
  • Decompressed immediate fields corresponding to bytes, halfwords, and words for load/store instructions which use the global pointer repster as a base repster are indicated by reference number 184 Similar to the decompressed fields indicated by reference number 182, the decompressed fields indicated by reference number 184 depict numerals in bit positions which are filled with a bit from the compressed immediate field and the letter "L" is used to indicate a bit position which is set to a binary zero Additionally, the most significant bit of each decompressed offset is set to a binary one (indicated by the letter "H") Turning next to Fig 10, a flow chart is shown depicting activities performed by instruction decompressor 12 in order to decompress instructions in accordance with the embodiment shown in Fig 8 Although the steps shown in Fig 10 are illustrated as se ⁇ al in nature, it is understood that va ⁇ ous steps may be performed in parallel
  • Instruction decompressor 12 dete ⁇ mnes if a received instruction is a load/store instruction (decision block 190) If the instruction is not a load/store instruction, the instruction is expanded in accordance with a mapping between the compressed instructions (as illustrated in Figs 3A-6F) and the co ⁇ esponding decompressed instructions (step 192) If the instruction is a load/store instruction, then the base repster specified by the instruction is examined (de ⁇ sion block 196) If the base repster is the global pointer register, the immediate field is decompressed as indicated by reference number 184 in Fig 9 (step 194) Alternatively, if the base repster is not the global pointer repster, the immediate field is decompressed as indicated by reference number 182 in Fig 9 (step 192)
  • mi ⁇ oprocessor 10 In addition to decompressmg load/store offsets m a different manner for the global pointer repster, mi ⁇ oprocessor 10 also supports a compression mode for indicating which type of instructions are bemg executed by mi ⁇ oprocessor 10 (I e compressed or non-compressed)
  • Fig 11 is a block diagram illustrating a portion of one embodiment of instruction decompressor 12 The illustrated portion determines the compression mode for each routine executed by mi ⁇ oprocessor 10 The portion shown may be suitable for mi ⁇ oprocessor 10B, and a similar portion may be employed by mi ⁇ oprocessor 10A Fig 11 depicts a mode detector 200
  • Mode detector 200 detects when the jump and link (JAL) instruction is fetched, and further examines the exchange bit 94 If exchange bit 94 is set, the routine at the target address of the JAL instruction compnses compressed instructions Therefore, the compression mode of the target routine is compressed Alternatively, exchange bit 94 may be clear In this case, the compression mode of the target routine is uncompressed
  • the JAL instruction causes the address of the instruction following the JAL instruction to be stored into register $31 of the MIPS RISC architecture This register may subsequently be used with the JR instruction to return from the target routine Because the compression mode is stored as part of the address in this embodiment, the compression mode of the source routine is restored upon execution of the JR instruction
  • routines encoded in compressed instructions may be intermixed with routines encoded in non-compressed instructions
  • the new compression mode is conveyed to processor core 16 upon a compression mode line 206
  • mode detector 200 may be included as a part of processor core 16 instead of instruction decompressor 12, m alternative embodiments
  • mode detector 200 shown in Fig 11 includes a storage 204 for a compression enable bit If compression is enabled, the compression enable bit is set When instructions are fetched m compressed mode and compression is enabled, instruction decompressor 12 decompresses the instructions If the enable bit is clear, instruction compression is disabled for mi ⁇ oprocessor 10 Instruction decompressor 12 is bypassed when instruction decompression is disabled Furthermore, mode detector 200 indicates that the compression mode is non-compressed when instruction compression is disabled
  • a routine is an ordered set of instructions coded for execution by mi ⁇ oprocessor 10
  • the routine may be coded in either compressed or non-compressed instructions, and is delimited by a subroutine call instruction and a return instruction
  • the delimiting subroutine call instruction is not included within the routine Instead, the subroutine call instruction indicates the beginning of the routine via a target address included with the subroutine call instruction
  • the first instruction of the routine is stored at the target address
  • the address of an instruction within the routine including the subroutine call instruction is saved so that a return instruction may be executed to return to the calling routine
  • the jal instruction may serve as a subroutine call instruction
  • the jalr instruction may serve as a subroutine call instruction
  • a routine ends with a return instruction, which causes subsequent instruction execution to return to the address saved when the corresponding subroutine call instruction is executed
  • the target address of the return instruction is the saved address
  • the jr instruction may serve as a return instruction
  • a target address is an address at which instruction fetching is to bepn upon execution of the instruction co ⁇ esponding to the target address
  • a block diagram of one embodiment of repster field decompression is shown Other embodiments of repster field decompression are contemplated
  • the compressed repster field co ⁇ esponding to an instruction is conveyed upon compressed register field bus 210
  • a register decompressor block 212 receives the compressed repster field Additionally, at least a portion of the compressed repster field is incorporated into the decompressed repster field which is then conveyed upon decompressed repster field bus 214
  • the decompressed repster field is thereby formed by concatenating at least a portion of the compressed repster field to the value generated by repster decompressor block 212
  • the entire compressed repster field is concatenated into the decompressed repster field Additionally, the remaining portion of the decompressed repster field depends upon which repster set the instruction accesses (e g xs vs rs and xt vs rt)
  • a set selector signal is received upon set selector bus 216 for each repster, indicating whether the xs (xt) or the rs (rt) repster set should be used If the set selector signal is asserted, then xs (xt) is selected. Otherwise, rs (rt) is sele ⁇ ed.
  • the set selector signal is asserted or deasserted based upon the opcode of the instruction being decompressed, in accordance with the exemplary compressed instruction set shown in Figs. 5A-6F.
  • the register mapping between compressed and decompressed registers shown in Table 1 may be employed.
  • register decompressor 212 may employ the following logic, wherein DR represents the decompressed register field, CR represents the compressed register field, and RH represents the co ⁇ esponding set selector signal value:
  • va ⁇ ous repsters are assigned to va ⁇ ous functions by software convention
  • the MIPS assembler assigns the following meamngs to repsters
  • ⁇ u ⁇ oprocessor 10 is incorporated onto a semiconductor substrate 224 along with multiple I/O interfaces 222 A- 222N
  • the I/O interfaces interface to I/O devices external to substrate 224
  • An exemplary I/O interface 222A may be a universal asynchronous receiver/transmitter (UART)
  • Microprocessor 10 may be coupled to I/O interfaces 222 for communication therewith Additionally, mi ⁇ oprocessor 10 may be coupled to external interface lope 226, which further interfaces to one or more dynamic random access memory (DRAM) modules 228 DRAM modules 228 may store compressed and/or non-compressed instruction code, as well as data for used by the propam represented by the compressed and/or non-compressed instruction code
  • DRAM dynamic random access memory
  • va ⁇ ous signals As used herein, a signal is “asserted” if it conveys a value indicative of a particular condition Conversely, a sipial is “deasserted” if it conveys a value indicative of a lack of a particular condition
  • a signal may be defined to be asserted when it conveys a lopcal zero value or, conversely, when it conveys a logical one value
  • Verilog listing describes exemplary logic for instruction decompressor 12. Many different embodiments of the logic are contemplated, although the Verilog listing shown is one suitable example:
  • wire spany -ext Jal & ci[15] & ⁇ ci[14] & ⁇ ci[l 1]
  • wire splor2 spany & ⁇ ci[13]
  • wire special splor2 & ⁇ ci[12]
  • wire br brjal & ⁇ i[ll]
  • wire word ci[15] & ( ⁇ ext
  • wire half ci[15]&( ⁇ ext
  • assign xo[31] -dojal & c ⁇ [15] & ( ext
  • -ext & ⁇ c ⁇ [l 5] & ⁇ c ⁇ [ 14] br) assign xo[27] dojal
  • ⁇ ( spany j c ⁇ [15]&c ⁇ [14]& ⁇ c ⁇ [l l] ) ), assign xo[26] dojal
  • a microprocessor has been descnbed which executes instructions from both a compressed instruction set and a non-compressed instruction set
  • the nu ⁇ oprocessor expands the compressed instructions into decompressed instructions or directly decodes the compressed instructions
  • routines coded using the compressed instruction set occupy a smaller amount of memory than the co ⁇ esponding routines coded m non-compressed instructions
  • Memory formerly occupied by such routines may be freed for use by other routines or data operated upon by such routines

Abstract

Microprocesseur configuré pour aller chercher un jeu d'instructions comprimées qui comporte un sous-ensemble d'un jeu d'instructions non comprimées correspondantes. Le jeu d'instructions comprimées est un jeu d'instructions de longueur variable comportant des instructions à 16 bits et des instructions à 32 bits. Les instructions à 32 bits sont codées à l'aide d'un code d'opération d'extension qui indique que l'instruction recherchée est une instruction étendue (par ex. 32 bits). Le jeu d'instructions comprimées comporte en outre des jeux multiples de cartographies de registres des champs de registre comprimés aux champs de registre décomprimés. Certaines instructions de sélection se voient attribuer deux codages par code d'opération, un pour chacune des deux cartographies des champs de registres correspondants. Le champ de registre comprimé est directement copié dans une partie du champ de registre décomprimé tandis que la partie restante du champ de registre décomprimé est créée à l'aide d'un petit nombre de portes logiques. L'instruction d'appel de sous-programme au sein du jeu d'instructions comprimées comporte un mode de compression qui indique si oui ou non le sous-programme cible est codé en instructions comprimées. Le mode de compression est stocké dans le registre de compteur d'instructions. La décompression du champ immédiat utilisée pour les instructions de charge/stockage ayant le registre de pointeur global en tant que registre de base est optimisée en vue de l'exécution mixte d'instructions comprimées/non comprimées. Le champ immédiat est décomprimé en un champ immédiat décomprimé pour lequel le bit le plus significatif est fixé.
PCT/US1997/009984 1996-06-10 1997-06-10 Appareil et procede permettant de detecter et de decomprimer des instructions a partir d'un jeu d'instructions comprimees de longueur variable WO1997048041A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP10501756A JP2000512409A (ja) 1996-06-10 1997-06-10 可変長圧縮命令セットから命令を検出し及び伸張する装置ならびに方法
GB9825726A GB2329495B (en) 1996-06-10 1997-06-10 An apparatus and method for detecting and decompressing instructions from a variable-length compressed instruction set
AU34808/97A AU3480897A (en) 1996-06-10 1997-06-10 An apparatus and method for detecting and decompressing instructions from a variable-length compressed instruction set

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US66102796A 1996-06-10 1996-06-10
US08/659,709 US5794010A (en) 1996-06-10 1996-06-10 Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
US08/659,708 1996-06-10
US08/661,003 1996-06-10
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US08/659,708 US5905893A (en) 1996-06-10 1996-06-10 Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999014669A1 (fr) * 1997-09-17 1999-03-25 Sony Electronics Inc. Unite de traitement de signaux numeriques avec instructions de largeur variable
WO1999028818A2 (fr) * 1997-12-02 1999-06-10 Telefonaktiebolaget Lm Ericsson (Publ) Decodage d'instructions ameliore
EP0942357A2 (fr) * 1998-03-11 1999-09-15 Matsushita Electric Industrial Co., Ltd. Microprocesseur compatible avec une pluralité de formats d'instructions
WO2000008554A1 (fr) * 1998-08-07 2000-02-17 Koninklijke Philips Electronics N.V. Appareil comportant une memoire de programme et un processeur
WO2008138781A1 (fr) * 2007-05-09 2008-11-20 Xmos Ltd Codage d'ensemble d'instructions compact
EP2863302A1 (fr) * 2013-10-18 2015-04-22 VIA Technologies, Inc. Processeur avec instructions comprimées et non comprimées et procédé d'exécution d'instructions
US9372696B2 (en) 2013-10-18 2016-06-21 Via Technologies, Inc. Microprocessor with compressed and uncompressed microcode memories
GB2586258A (en) 2019-08-15 2021-02-17 1Inspiries Tech Ltd Efficient processor machine instruction handling
US11204768B2 (en) 2019-11-06 2021-12-21 Onnivation Llc Instruction length based parallel instruction demarcator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9710277B2 (en) * 2010-09-24 2017-07-18 Intel Corporation Processor power management based on class and content of instructions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437149A (en) * 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
JPH07121352A (ja) * 1993-10-21 1995-05-12 Canon Inc 演算処理装置
GB2284492A (en) * 1993-12-06 1995-06-07 Graeme Roy Smith Data processor with instruction decompression unit
GB2289353A (en) * 1994-05-03 1995-11-15 Advanced Risc Mach Ltd Data processing with multiple instruction sets.

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437149A (en) * 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
JPH07121352A (ja) * 1993-10-21 1995-05-12 Canon Inc 演算処理装置
GB2284492A (en) * 1993-12-06 1995-06-07 Graeme Roy Smith Data processor with instruction decompression unit
GB2289353A (en) * 1994-05-03 1995-11-15 Advanced Risc Mach Ltd Data processing with multiple instruction sets.

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DITZEL D R ET AL: "The hardware architecture of the CRISP microprocessor", 14TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE. CONFERENCE PROCEEDINGS (CAT. NO.87CH2420-8), PITTSBURGH, PA, USA, 2-5 JUNE 1987, ISBN 0-8186-0776-9, 1987, WASHINGTON, DC, USA, IEEE COMPUT. SOC. PRESS, USA, pages 309 - 319, XP000212078 *
PATENT ABSTRACTS OF JAPAN vol. 095, no. 008 29 September 1995 (1995-09-29) *

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6189090B1 (en) 1997-09-17 2001-02-13 Sony Corporation Digital signal processor with variable width instructions
WO1999014669A1 (fr) * 1997-09-17 1999-03-25 Sony Electronics Inc. Unite de traitement de signaux numeriques avec instructions de largeur variable
WO1999028818A2 (fr) * 1997-12-02 1999-06-10 Telefonaktiebolaget Lm Ericsson (Publ) Decodage d'instructions ameliore
WO1999028818A3 (fr) * 1997-12-02 1999-09-16 Ericsson Telefon Ab L M Decodage d'instructions ameliore
US6499100B1 (en) 1997-12-02 2002-12-24 Telefonaktiebolaget Lm Ericsson (Publ) Enhanced instruction decoding
US7194602B2 (en) 1998-03-11 2007-03-20 Matsushita Electric Industrial Co., Ltd. Data processor
US7979676B2 (en) 1998-03-11 2011-07-12 Panasonic Corporation Method for instructing a data processor to process data
US6199155B1 (en) 1998-03-11 2001-03-06 Matsushita Electric Industrial Co., Ltd. Data processor
US8650386B2 (en) 1998-03-11 2014-02-11 Panasonic Corporation Data processor including an operation unit to execute operations in parallel
US6549999B2 (en) 1998-03-11 2003-04-15 Matsushita Electric Industrial Co., Ltd. Data processor
EP0942357A2 (fr) * 1998-03-11 1999-09-15 Matsushita Electric Industrial Co., Ltd. Microprocesseur compatible avec une pluralité de formats d'instructions
US8443173B2 (en) 1998-03-11 2013-05-14 Panasonic Corporation Method for instructing a data processor to process data
US7664934B2 (en) 1998-03-11 2010-02-16 Panasonic Corporation Data processor decoding instruction formats using operand data
EP0942357A3 (fr) * 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Microprocesseur compatible avec une pluralité de formats d'instructions
WO2000008554A1 (fr) * 1998-08-07 2000-02-17 Koninklijke Philips Electronics N.V. Appareil comportant une memoire de programme et un processeur
US7676653B2 (en) 2007-05-09 2010-03-09 Xmos Limited Compact instruction set encoding
WO2008138781A1 (fr) * 2007-05-09 2008-11-20 Xmos Ltd Codage d'ensemble d'instructions compact
EP2863302A1 (fr) * 2013-10-18 2015-04-22 VIA Technologies, Inc. Processeur avec instructions comprimées et non comprimées et procédé d'exécution d'instructions
US9361097B2 (en) 2013-10-18 2016-06-07 Via Technologies, Inc. Selectively compressed microcode
US9372696B2 (en) 2013-10-18 2016-06-21 Via Technologies, Inc. Microprocessor with compressed and uncompressed microcode memories
US9830155B2 (en) 2013-10-18 2017-11-28 Via Technologies, Inc. Microprocessor using compressed and uncompressed microcode storage
GB2586258A (en) 2019-08-15 2021-02-17 1Inspiries Tech Ltd Efficient processor machine instruction handling
US11204768B2 (en) 2019-11-06 2021-12-21 Onnivation Llc Instruction length based parallel instruction demarcator

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AU3480897A (en) 1998-01-07
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GB2329495B (en) 2000-09-20

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