GB2349252A - An apparatus and method for detecting and decompressing instructions from a variable length compressed instruction set - Google Patents

Abstract

A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set, for example including 16-bit and 32-bit instructions. Extended (e.g. 32-bit) instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. Extended instructions have a second opcode field, which is decompressed into a decompressed opcode field within a decompressed instruction. For non-extended instructions, the first opcode field is decompressed into the decompressed opcode field. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates. The subroutine call instruction within the compressed instruction set includes a compression mode which indicates whether or not the target routine is coded in compressed instructions. The compression mode is stored in the program counter register. The decompression of the immediate field used for load/store instructions having the global pointer register as a base register is optimized for mixed compressed/non-compressed instruction execution. The immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.

Description

2349252 TrrLE: AN APPARATUS AND METHOD FOR DETECTING AND DECOMPRESSING

INSTRUCTIONS FROM A VARLABLE- LENGTH COMPRESSED INSTRUCTION SET

BACKGROUND OF THE LWENTTON

L Field of the Invention

This invention relates to the field of microprocessors and, more particularly, to optimization of the instruction set of a microprocessor.

2. Desgipti on of the Relevant Art Microprocessor architectures may generally be classified as either complex instruction set computing (CISC) architectures or reduced instruction set computing (RISC) architecrur-es. CISC architectures specify an instruction set comprising high level, relatively complex instructions. Oft= microprocessors implementing CISC architecttires decompose the complex instructions into multiple simpler operations which may be more readily implemented in hardware. Microcoded routines stored in an on-chip read-only memory (ROM have been successfially employed for providing the decomposed operations corresponding to an instruction. More recently, hardware decoders which separate the complex instucrions into simpler operations have beeti adopted by certain CISC microprocessor designers. The x86 microprocessor architecture is an example of a CISC architectu:re.

Conversely, RISC architectures specify an instruction set comprising low level, relatively simple instnictions. TypicaUy, each instruction within the instruction set is dft=dy implemented in hardware.

Complexities associated with the CISC approach are removed, allowing for more advanced implementations to be demigned Additionally, high frequency designs may be achieved more easily sinc-- the hardware employed to execute the instructions is simpler. An exemplary RISC architecture is the MIPS RISC architecture.

Although not necessarily a defining feature, variable-length instruction sets have often been associated with CISC architectures while fixed-length instruction sets have been associated with PJSC architectures.

Variable-lerurth instruction sets use dissimilar numbers of bits to encode the various instructions within the set as well as to specify addressing modes for the instructions, etc. GeneraUy speaking, variable-length instruction sets attempt to pack inmruction information as efficiently as possible into the byte or bytes representing each instruction. Conversely, fixed-length instruction sets employ the same number of bits for each instruction (the number of bits is typically a multiple of eight such that each instruction fWly occqies a fixed number of bylm).

Typically, a small number of instruction formats comprising fixed fields of information are defined. Decoding each instruction is thereby simplified to routing bits corresponding to each fixed field to logic designed to decode that field.

Bemuse each instruction in a fixed-length instruction set comprises a fixed number of bytes, locating instructions is simplified as well. The location of numerous instructions subsequent to a particular instruction is implied by the location of the particular instruction (Le. as fixed offsets from the location of the particular instruction). Converselv, locating a second variable-length instruction requires locating the end of the first variable-length instruction; locating a third variable-length instruction requires locating the end of the second variable-Icngth instruction, etc. Still further, variable-length instructions lack the fixed field strurure of fixed length instructions. Decoding is further complicated by the lack of fixed fields.

I Unfortunately, PLISC architectures emplaying fixed-length insmiction sets suffer from problems not generally applicable to CISC architectures employing variable-length instruction sets. Because each instructon is fixed length. certain of the simplest inmuctions may effectively waste memory by occupying bytes which do not convey information concerning the instruction. For exampIc, fields which are specified as "don't care" fields for a particular instruction or instructions in many fixed-length instruction sets waste memory. In contrast, variable-length instuction sets pack the instruction information into a minimal number of bytes.

Still further, since RISC architectures do not include the more complex instructions employed by CISC architectures, the number of instructions employed in a pro grarri coded with RISC instructions may be larger than the number of ins=ctibns -employed in the same program coded in with CISC Uwructions. Each of the more complex instructions coded in the CISC version of the program is replaced by multiple instructions in the RISC version of the program- Therefbre, the CISC version of a program often occupies sigicantly less memory than the RISC version of the pmgramContspondingly, more bandwidth between devices storing the program. memory, and the mi=processor is needed for the RISC version of the program than for the CISC is version of the program.

SIMOLARY OF TEM VVENMON The problems outlined above are in large part solved by a microprocessor in accordanc: with the present invenuon. The microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The non- compressed instruction set may be a RISC instruction set, such that the microprocessor may enjoy the high frequency operation and simpler execution resources typically associated with RISC architectures. Fetching the compressed instructions fi-om memory and decompressing them within the microprocessor advantageously decreases the memory bandwidth required to achieve a given level of performance (e.g. instructions executed per second). Still further, the amount of memory occupied by the compressed instructions may be comparatively less tl= the corresponding non compressed mstructions may occupy.

The exemplary compressed insamcdon set described herein is a variable length insmiccion set.

According to one embodiment, two distinct instruction lengths are included: 16-bit and 32-bit insauctions, The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction- Instructions may be fetched as 16- bit quantities. When a 16-bit instrucrion having the extend opcode is fetched, the succeeding 16-bit insamcrion is concatenated with the instruction having the extend opcode to form a 32-bit extended instruction- Extended instructions have enhanced capabilities with respect to non-cxnded instructions, further enhancing the flexibility and power of the compressed instruction set. Routines which employ the capabilities included in the extended ins=-dons may thereby be coded using compressed instructions.

The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Each value coded in the compressed register fields decompresses to a different register within the microprocessor. In onee embodiment, the compressed register fields comprise three bits each. Therefore. eight registers are acc-cessible to a particular instruction- In order to offer access to additional registers for certain select insuumons. the select instructions are assigned two opcode encodings. One of the opcode encodings indicates a firr, mapping of register fields, while the

2 second opcode encoding indicates a second mapping of register fields. Advantageously, the compressed register fields may include rclatively few bits while select instructions for which access to additional registers is desired mav be granted such acc=. Additionally, the register mappings are selected to minimize the logic employed to decompress register fields. In one embodiment. the compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

The microprocessor supports programs having routines coded in compressed instructions and other roltaines coded in non-compressed instructions. The subroutine call instruction within the compressed instruction set includes a compression mode which indicates whether or not the target routine is coded in cbmpressed inmcrions. The compression mode specified by the subroutine call Utstruction is captured by the microprocessor as the compression mode for the routine. In one embodiment, the compression mode is stored as one of the fetch address bits (stored in a program counter register within the rru-=processor). Since the conTression mode is part of the fetch address and the subroutine call instruction includes storing a icuu addres for the subroutine. the compression mode of the calling routine is automatically stored upon execution of a subroutine call insrru=orL When a subroutine return instruction is executed. the compression mode of the calling routine is theretn- automatically restored.

An additional feature of one embodiment of the microprocessor is the decompression of the immediate field used for load/stom insauctions having the global pointer register as a base register. The immediate field is decompressed iiito a decompressed immediate field for which the most significant bit is set. A subrange of addresses at the lower boundary of the global variable address space is therebry allocated for global variables of compressed instructions. Non-compressed instructions may store global variables in the remainder of the global variable address space. Advantageously, global variable allocation between the compressed and non compressed routines of a particular program may be relatively simple since the subranges are separate.

Broadly spealang, the present invention contemplates an apparatus for exectning inmcdons from a variable-length compressed instruction set, comprising an instruction decompressor. The instruction decompressor is coupled to receive instructions which are members of the variable-length compressed instruction set, wherein the instruction decompressor is configured to examine an opcode field of a particular instruction. The instruction decompressor is configured to determine that the particular insmiction is an c=ded instruction having a fim fixed length if the opcode field is coded as an extend opcode. Additionally, the instruction decompressor is configured to determine that the particular instruction is a non-extended instruction if the opcode field is coded as a second opcode different than the emend opcode,

The present invention further contemplates a method for expanding compressed instructons into decompressed instructions. A compressed instruction is determined to be an extended instruction having a first fixed length if an opcode field of the compressed instruction is an extend opcode. If the opcode field of the compressed instrumion is a second opcode different than the extend opcode. the compressed instruction is a non-extended instruction having a second fixed length. The compressed instruction is decompressed into a decompressed instruction. A number of bytes included in the compressed instrtiction is defined by the first fixed length if the compressed instruction is an extended instruction. Alternatively the number of bytes is defined by the second fixed length if the compressed instruction is a non- mended instruction.

The present invention still flirther contemplates an apparatus for expanding compressed instructions into de.-OMDressed instructions. comprising a first determining means, a second determining means, and a decompressing means. The first deterniining means determines that a compressed instruction is an extended 3 instruction having a f= fixed length if an opcode field of the compressed instruction is an extend opcode.

The second determining mearts detennines that the compressed instruction is a non-extended instruction having a second fixed length if the opcode field of the compressed instruction is a second opcode different than the extend opcode. The decompressing means decompresses the compressed instruction into a decompressed instruction. A number of bytes included in the compressed instruction is defined by the fim fixed length if the compressed insttucuon is the extended instruction. Alternatively, the number of bytes is defined by the second fixed length if the compressed instruction is the non-extended instruction.

The present invention yet further contemplates a method for executing a pmgram including a E= mutine and a second routine in a microprocessor. A subroutine caU instruction is executed within the fim toutme, whemn the subroutine call, instruction indicates that the second routine is to be executed via a target - address of the subroutine call instruction. An indication within the subroutme =11 instruction is examined. if the indication is in a fim state. the second routine is determined to be coded using compressed instructions.

The second routine is determined to be coded using non-compressed instructions if the indication is in a second state diffe=t than the first state.

Fuvlermore, the present invention contemplates an apparatus for executing a program including a first routine and a second routine in a nuc:roprocessor, comprising am executing means and an I. 9 rneam. Ile executing means executes a subroutine call instruction within the first routine. The subroutine caU instruction indicates that the second routine is to be executed via a target address of the subroutine caU in==on. The examining means examines an indication within the subroutine call instruct:ion. The exandning: means determines that the second routine is coded using compressed instructions if the indication is in a first state. If the indication is in a second state, the examining means determines that the second routine is coded using non-compressed instructions.

The present invention still funher contemplates an apparatus for fetching compressed and non compressed instructions in a microprocessor, comprising a storage device and a mode detector. The storage device stores a compression enable indicator. Coupled to the storage device, the mode detector is configured to detect a compression mode of a target routine upon fetch of a subroutine call instruction specifying the target routine. The mode detector is configured to convey the compression mode to a processor core. 'Me processor core is configured to fetch compressed insttuctions if the compression mode indicates compressed.

Additional.ly, the processor core is configured to fetch non-compressed instructions if the corrmmssion mode indicates non-compTessed The present invention yet fur-ther contemplates a microprocessor comprising an inswicdon decompressor and a processor core. The instruction decompressor is coupled to receive compmssed instructions which are members of a variable-length compressed instruction set. The instruction decompressor is configured to decompress each received compressed instruction into a corresponding decompressed instruction- Coupled to receive decompressed insauctions, the processor core is configured to execute the decompressed instrucTions.

The present invention additionally contemplates a method for executing instruction code.

Compressed instructions are fetched. wherein the compressed instructions are members of a variable-length compressed instruction set. The compressed instructions are decompressed in an instruction decompressor, thereby forming corresponding decompressed instructions. The decompressed instruccuions ar-- -executed in a processor core.

The present invention still further contemplates an apparatus for executing instruction code, 4 compnsing a fetching means. a decomPressmg means. and an executing m&Ins. The fetching mean fetches compressed ins=crions which are members of a variable-lezigth compressed instruction set. The decompressing means decompresses the compressed instructions, therrbv forming con-esponding decompressed instructions. The executing means executes the decompressed instructions.

Furthertriore, the present invention contemplates an instruction decompressor configured to decompress compressed instttictions. A first one of the compressed instructions is codable to access a first subset of registers defined for a corresponding non-compressed instruction set. Additionally, a second one of the compressed instructions is codable to access the first subset of registers and is ftirther codable to access a second subset of registers.

1 The pn=nt invention ftrflmr contemplates a method for decompressing compressed insmictions. A particular compressed instruction having a first register field is decompressed using a first register map ping from compressed register indicators to decompressed register indicators if the particular compressed instruction is encoded using a f= opcode. Alteriiatively, the particular compressed instruction having the first. register field is decompremed using a second register mapping from compressed regisw indicators to is decompressed register indicators if the particular compressed instruction is encoded using a second opcode.

T'he prewnt invention still further contemplates an apparatus for deconipressing compressed instructions comprising a decompressing means. The decompressing mean is configured to decompress a particular compmssed instruction having a first register field using a first register mapping from compressed register indicators to decompressed register indicators if the particular comprrss.-d instruction is encoded using a first opcode. Additionally, the decompressing means is configured to decompress the particular compressed instruction. using a second register mapping from compressed register indicators to de-compressed register indicators if the particular compressed instruction is encoded using a Second opcode.

Ile present invention yet fin'ther contemplates an instruction decompressor configured to decompress a compressed register field of a compressed instruction into a decompressed register field. of a decompressed instruction. A decompression of the compressed register field is dependent upon a first value coded into the corripressed register field and a second value coded into an opcode field of the compressed instru:ction.

The present invention additionally contemplates a method for decompressing a compressed register field of a compressed instruction into a decompressed register field of a decompressed instruction. At least a portion of the compressed register field is directly copied into a portion of the decompressed register field. The remaining portion of the decompressed register field is produced by logically operating upon the compressed register field.

Moreover, the present invention contemplates an apparanis for decompressing a compressed register field of a compressed instruction into a decompressed register field of a decompressed instruction, comprising a first means and a second means. The first means is for directly copying at least a portion of the compressed register field into a portion of the decompressed register field. The first means is coupled to receive the compressed register field. Similarly coupled to receive the compressed register field. the second means is for logically operating upon the compressed register field to produce a remaining portion of the decompressed register field.

Furthermore, the present invention contemplates an instruction decompressor configured to decompress a compressed register field of a compressed instruction into a decompressed register field of a decompressed instruction. The instruction decompressor forms a first portion of the decompressed register field by coping at least a portion of the compressed register field thereto. Additionally, the instruction compressed er field to decompressor includes a logic block which, is configured to operate upon the regist produce a remaining portion of the decompress register field.

BREEF DESCREMON OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which.

Fig. 1 is a block diagram of am embodiment of a microprocessor.

Fig. 2 is a block diagram of a second embodiment of a microprocemr.

Fig. 3A is a fim instruction format supported by one embodiment of the microprocemn shown in Figs. 1 and 2.

Fig. 3B is a second instruction format mpported by one embodimem of the microprocessors shown in Figs. I and 2.

Fig. 3C is a third instruction format supported by one embodiment of the microprocessors shown in Figs. 1 and 2.

Fig. 3D is a fourth instruction format supported by one embodiment of the microprocessors shown in Figs. 1 and 2.

Fig. 4A is a fifth insuuction format supported bry one embodiment of the microprocessors shown in Figs. 1 and 2.

Fig. 4B is a sixth inmcdon, format supported by one embodiment of the microprocess rs shown in Figs. 1 and 2.

Fig. 4C is a seventh instruction format supported by one embodiment of the microprocessors shown in Figs. I and 2.

Fig. 4D is an eight instruction format, supported by one embodiment of the MiCICPL ors shown in Figs. I and 2.

Figs. 5A, 5B, SC, 5D, and 5E are tables of exemplary instructions using the formats shown in Figs 3A, 3B, 3C, and 3D.

4 0 Figs. 6A, 6B, 6C, 6D, 6E, and 6F are tables of exemplary instructions usingthe formats shown in Figs. 4A, 4B, 4C, and 4D.

6 Fig. 7 is a diagram depicting offsets from an arbitrary registex and a global pointer register. according to one embodiment of the microprocessors shown in Figs. I and 2.

Fig. 8 is a block diagram of exemplary hardware for expanding an immediate field from a compressed instruction to a decompressed instrtwtion.

Fig. 9 is a diagram depicting decompressed offsets in accordance with one embodiment of the microprocessors shown in Figs. I and 2.

1 Fig. 10 is a flow chart, ddpicting operation of a decompr-.ssor for immediate fields according to one - embodiment of the microprocessors shown in Figs. I and 2.

Fig. I I is a block diagram of exemplary hardware for generating fetch addresses according to one embodiment of the microprocessors shown in Figs. I and 2.

Fig. 12 is a block diagram showing register decompression logic emploved in one embodiment of the microprocessors shown in Figs. I and 2.

Fig. 13 is a block diagram of an exemplary computer system inchiding the microprocessor for which embodimmu are shown in Figs. I and 2.

While the mve=on is susceptible to various modifications and alternative forms, specific embochments thereof are shown by way of example in the dravnngs and wM herein be described in detail. It should be understood, however, that the drawings and detailed description thercto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defted by the appended claims.

DETAILED DESCREMON OF THE MMNTTON Turning now to Fig. 1. a block diagram of a first embodiment of a microprocessor I OA is shown.

Nficroprocessor I OA includes an instruction decompressor 12A. an hs=ction cache 14A, and a processor core 16. Insauction decompressor 12A is coupled to receive instruction bytes from a main memory subsystem (not shown). Instruction decompressor 12A is further coupled to instruction cache 14A. Instruction cache 14A is coupled to processor core 16.

Generally speaking, microprocessor I OA is configured to fetch compressed instructions from the main memory subsystem. The compressed instructions are passed through instruction decompressor 12A, which expands the compressed instructions into decompressed instructions for storap within instruction cache 14A Many of the compressed instructions occupy fewer memory storage locations than the corresponding decompressed instructions, advantageously reducing the amount of memory required to store a particular program. Additionally, since instructions are decompressed within microprocessor IOA, the bandwidth required to transport the compressed instructions from the main memory subsystem to microprocessor I OA is 7 reduced. Nficroprocessor 10A may be employed within a computer system having a relatively small main memory. Relatively large programs may be stored in the main memory due to the compression of insauctions; stored thervin.

In one embodiment. microprocessor 10A is configured to execute both compressed and non compressed instructions on a routine-by-routine basis. In other words, a routine may be coded using either compressed ins;tructions or non-compressed instructions. Advantageously, rounnes which may not be efficiently coded in the compressed instruction set may be coded using non-compressed instructions, while routines which are efficiendy coded in the compressed instruction set are so coded. Nficroprocessor I OA may support a Darticular decompression of the immediate field for load/store instructions using the global pointer register as a base regisTer. in order to mpport mixing of compressed and non-compressed instructions. The - particular decompression is detailed ftuther below. Addi-tionally. a compression mode is detected b!v instruction decompressor 12A. The compression mode identifies the instruction set in which a roudne is coded: compressed or non-compressed.

Instruction compression is achieved in microprocessor 10A by imposing certain limitations upon the available instruction encodings. By limiting the instruction encodings, instruction field sizes may be reduced (i.e. the number of bits within an instruction field may be decreased). For example, the nurtiber of available registers may be reduced to form the compressed instruction set. Bemuse fewer registers are available, a smaller field may be used to encode the registers used as source and destination operands for the instruction

Instructioa decompressor 12A expands the encoded register field into a decompressed register field- The decompressed register field is included in the decompressed instruction. The compressed instructions use the reduced iiistruction fields. thereby occupying less memory (i.e. fewer bits) than the original instruction encodings defined by the microprocessor architec=e employed by processor core 16.

Insmwdon decompressor 12A is configured to accept compressed instructions and to decourpress the instructions into the orizinal instruction encodings. Each instruction field within a partictilar cempressed instruction is expanded from the compressed field to a corresponding decompressed field within the corresponding decompressed instruction. 'Me decompressed instruction is coded in the original instruction format supported by processor core 16.

Processor core 16 includes circuitry for fetching instructions from instruction cache 14.k decoding the instructions, and ex m-ting the instructions. The instructions supported by processor core 16 art specified by the microprocessor architecture employed therein- In one particular embodiment, processor core 16 employs the MIPS RISC architecture. However, it is understood that processor care 16 may employ any microprocessor architecture. Since instriction decompressor 12A decompresses instructions into the original instruction format, processor core 16 may comprise a previously designed processing core. In other words, the processing care may not require substantial modification to be included within microprocessor 10A The MIPS RISC architecture specifies an instruction set comprising 32 bit fixed-length inst:ructions.

A compressed instruction set is defined for microprocessor 10A which comprises variable-length instructions.

Many of the compressed insmictions comprise 16-bit instructions. Other compressed instructions comprised 32 bit instructions in conjunction with the extend instruction described below. Several 16-bit and 32-bit instruction fon-nats are defined. It is understood that, although 16-bit and 32-bit compressed instrucdons are used in this embodiment. other embodiments may employ different instruction lengths. The compressedinstructions encode a subset of the non-compressed instructions. Instruction encodings supponed,%ithin the compressed instruction set comprise many of the most commonly coded instructions as well as the most often 8 used registers, such that many Programs. or routines within the programs, may be coded using the Compressed instructions.

In one embodiment. microprocessor IOA employs a compressioff mode. If the compmssion made is active, then compressed instructions are being fetched and executed. Instruction decompressor 12A decompresses the instructions when they are transferred from main memory to instruction cache 14.

Alternatively, the compressed mode may be inactive. VZ= the compression mode is inactive. non-compressed instructions are being fetched and executed, Instruction decompressor 12A is bypassed when the compressed mode is inactive, In one particular embodiment. the compression mode is indicated by a bit within the fetch address (e.g. bit 0). The current fetch address may be stored in a PC register 18 wiLhin processor core 16. Bit 0 f PC register 18 indicates the c-dinpression mode (CW of microprocessor IOA.

Instruction cache 14A is a high speed cache memory configured to store decompressed and.non compressed instructions. Although any =he organization may be employed by instruction cache 14A, a set associative or direct mapped configuration may be suitable for the embodiment shown in Fig. 1.

Turning nen to Fig. 2, a second embodiment of a microproc=or IOB is sh Nficroprocessor IOB includes an instruction cache 14B coupled to receive instruction bytes from the main memory subsystem, an instruction decompressor 12B, and processor core 16. Instruction cache 14B is coupled to instruction decompremor 12B, which is ftirther coupled to processor core 16.

Microprocessor IOB is configured with instruction decompressor 12B between instruction cache 14B and processor core 16. Instruction cache 14B stores the compressed instrmcrions transferred from the main memory subsystem. In this manner, instruction cache 14B may store a relatively larger number of instructions than a sim:ELarly sized instruction cache employed as instruction cache 14A in microprocessor 10A_ Instrtiction decompressor 12B r=ives fetch addresses corresponding to instiuction fetch requests from processor core 16, and accesses insmaction cache 14B in response to the fetch request. The corresponding compressed instructions are decompressed into decompressed instructions by instruction decompressor 12B. The decompressed in=uctions; are transmitted to processor core 16.

Similar to microprocessor IOA, microprocessor IOB includes a compression mode in one embodiment. Instruction decompre-zor 12B is bypassed when non-compressed instrtictions are being fetched and executed. For this embodiment, instruction cache 14B stores both compressed and non-comprmed instructions. It is noted that instruction cache 14D typically stores instruction byte.- in fixed-size storage locations refmTed to as cache lines. Therefore, a particular cache line may be storing compressed or non compressed instructions. In either case, a plurality of instruction bytes are stored. Therefore, instriwdon caches 14A and 14B may be of similar construction. The compression made at the time a cache line is accessed determines whether the instruction bytes are interpreted as compressed or rion-compressed insauctions.

An alternative configuration for microprocessor I OB is to include instruction decompressor 12B within the instruction decode logic of pmcessor core 16. The compressed instructions may not actually be decompressed in such an embodimenL Instead, the compressed instructions may be decoded dimctly by the decode lo c. The decoded instructions may be similar to the decoded instructions generated for the non gi compressed instructions which correspond to the compressed instructions.

It is noted that microprocessors I OA and 1013 are merey exemplary embodiments of a microprocessor which operates upon compressed instructions. For the remainder of this diszmssion. microprocessor 10, instruction cache 14, and instruction decompressor 12 will be used to refer to the corresponding elements of 9 both Figs. I and 2 as well as other embodiments of the elements included in other implementations of microprocessor 10.

The terms decompression, compressed instrucrion. decompressed instruction. and non-compressed instruction are used in the above discussion and may further be used below. As used herein. the term "compressed instruction" refers to an instruction which is stored in a compressed form in memory. The compressed instruction is generally stored using fewer bits than the number of bits used to store the instruction whert represented as defined in the rrucroprocessor architecture employed by processor core 16. The term "decompressed instruction" refers to the result of expanding a compressed instruction into the original encoding as defirted in the microprocessor architecture employed by processor core 16. The term "non cmpressed insr:ruction" refers to in instruction represented in the encoding defined by the mi=processor - architecture employed by processor core 16. Non-comprtssed instructions are also stored in memory in the sam format (Le. non-compressed instructions were never compresseA). Finally, the term "decompression" - refers to the process of expanding a compressed instruction into the corresponding decompressed instruction.

It is noted that instruction decompressors 12A and 12B may be configured to simultaneously decompress multiple compressed instructions. Such embodiments of instruction decompressors 12 maybe employed with embodiments of processor core 16 which execute multiple iristructions per clock cycle.

Figs. 3A-3D and 4,k-4D depict exemplary iustruction formats for 16-bit and 32-bit compressed instructions, respectively, according to one specific embodiment of microprocessor 10 employing the MIPS RISC architecture. Other instructions formats may be -employed by other =bodiments. The instruction formats shown in Figs. 3A-3D each comprise 16 bits in this particular implementation. Conversely, the instruction formats shown in Figs. 4A-4D each comprise 32 bits in this particular implementarion. The compressed instructions encoded using the instruction formats are decompressed into instruction formats as defined by the MIPS RISC architecture for each instruction.

Fig. 3A depicts a first instruction format 20- Instruction format 20 includes an opcod-- field -12, a fim register field 24, a second register field 26, and a function field 28. Opcode field 22 is used to identify the instruction. Additionally, function field 28 is used in conjunction with certain particular encodings of opcode field 22 to identity the instruction. Effectively, fimcrion field 28 and opcode field 22 together form the opcode field for these instructions. When opcode field 22 employs certain other cricodings; than the particular encodings, function field 28 is used as an immediate ficid.

First register field 24 and second register field 26 identify destination and source regisT---s for the instruction. The destination register is also typically used as a source register for the instruction. In this manner, two source operands and one destination operand are specified via fim register field 24 and second register field 26. The notations "RT" and "RS" in first register field 24 and second register field 26 indicate the use of the fields in the instruction tables below. Either RT or RS may be a destination register, depending upon the encoding of the instrtiction.

In one embodiment, opcode field 22 comprises 5 bits, first register field 24 and second register field

26 comprise 3 bits each, and function field 28 comprises 5 bits. First register field 24 is divided into two subfields (labeled RTI and RTO). RTI comprises two bits in the present embodiment, while RTO comprises one bit. RTI is concatenated with RTO to form first register field 24. Subfield RTI and second regisw field

26 are used in certain instructions encoded via instruction format 20 to indicate one of the 32 registers defined by the MIPS RISC architecture.

Fig. 3B depicts a second instruction format 30. Instruction format 30 includes opcode field 22, first register field 24, and second register field 26. Additionally, a third register field 32 and a function field 34 are shown. Third register field 3 2 is generally used to identify the destination register for instruct:ions using instruction format 30. Therefore. first register field 24 and secbnd register field 26 comprise source registers for instruction format 30. Function field 34 is used similar to function field 28. In the embodiment shown.

third register field 32 comprises three bits and function field 34 comprises two bits.

A third immcdon format 40 is shown in Fig. 3 C. Instruction format 40 includes opcode field 2-7 and sewnd register field 26, as well as an immediate field 42. Immediate field 42 is used to provide immediate data for the instruction specified by instruction format 40. Immediate data is an operand of the instrtioa, similar to the value stored in a register specified by first register field 24 or s=nd register field 26. For i 0 eample, an add instruction which uses immediate dam adds the immediate data to the value stored in the - destination register, and stores the resulting sum into that destination register. In one embodiment,.immediate field 42 comprises eight bits. Immediate field 42 is divided into two subfields MvUl and RvWO) in the instruction format shown in Fig. 3 C. The subfields allow second register field 26 to be placed in the same bit positions within instruction format 40 as it is placed in ins=ction formats 20 and 30. Advantageously, second is register field 26 is always found in the same position of 16-bit instructions in which it is used. Therefore, subfield NMI comprises 2 bits and subfield 54MO comprises 6 bits. DAM1 is concatenated with RvJMO to form the immed ate value.

Fig. 3D depicts a fourth instruction format 50. Instruction format 50 includes opcode field 2-1 and an immediate field 52 Immediate field 52, similar to immediate field 42, is used as an operand of the instruction.

However, immediate field 52 comprises I I bits.

Fig. 4A depicts a fifth instruction format 60. Instruction format 60 includes opcode field 2-1, which is coded as the emend instruction. Instruction decompressor 12 re-cognizes the extend instruction opcode within opcode field 22 and trcats the current instrucdon as a 32-bit instruction (i.e. the 16 bits included in the instruction containing the emend opcode and the 16 bits which would otherwise comprise the next instructiorn in program order are concatenated to form a 32 bit instruction). Therefore, the compressed instruction can be seen to be a variable-length instruction set comprising 16-bit instructions and 321 -bit instructions. Instruction format 60 fimher includes a =o field 62 comprising six bits (coded to all binary zeros), an immediate field

64, and a BR field 66. Instruction format 60 is used to code an extended form of the BR instruction (an unconditional branch instruction), and hence BR field 66 is an opcode field indicadng the BR instruction. In one embodiment, the BR opcode is hexadecimal 02.

The emended BR instruction has a Luger immediate field than the nonextended BR instruction, and therefore may be coded with larger offsets Um the non-extended BR instruction. When a branch to an instruction distant ftom the branch instruction is desired, the extended BR instruction may be usecL Alternatively, branches to close instructions may use the non-extended BR instruction. Immediate field 64 comprises 16 bits which are used as an offset to be added to the address of the instruction following the BR instruction to create the target address of the branch instruction. The non-emended BR insauction, by contrast. includes an eleven bit offiset (i.e. it is coded using instruction format 50).

Fig. 4B depicts an instruction format 70 which is an extended version of instruction format 40.

Instruction format 70 includes opcod.- field 22 coded as the extend opcode, as well as an immediate field 72, a first register field 74, a second register field 76, and a second opcode field 78. First register field 74 and second register field 76 comprise five bits each in the embodiment shown. Therefore, any register defined by the MPS PJSC architecture may be accessed using instruction format 70. Second opcode field 78 defines the

I I instruction being executed. and comprises 5 bits (similar to opcode field 22). Finally, irnmediate field 72 comprises 12 bits divided into a one bit NM'21 subfield. a five bit WM I subfield. and a six bit DAMO subfield.

Lmmediate field 72 is formed by concatenatirig MA2 with 2^f I and fiirther with WAO in the embodiment shown.

An extended instruction format corresponding to instruction format 30 is shown in Fig. 4C as an instruction format 80. Instruction format 80 includes opcode field 22, first register field 74, second register field 76. and second opcode field 78, similar to instruction format 70. Additionally, instruction format 80 includes a third register field 82 and a function field 84. Third register field 82 is similar to third register field

32, except that third register field 82 comprises five bits. Therefore, any MIPS RISC architecture register may b specified by third register field'82. Function field 84 is similar to function fields 28 and 34, except that - function field 84 comprises six bits.

Second opcode field 78 is coded to a particular value to identify instruction format 80 from instruction format 70. When second opcode field 78 is coded to the particular value, instruction format 80 is asuined by instruction decompressor 12. Conversely, when second opcode field 78 is coded to a value other than the is particular value, instruction format'70 is assumed by instruction decompressor 12. In one embodiment, the particular value comprises hexadecimal 00.

Instruction format 80 ftirther includes a CON bit 86. COPO bit 86, when set, indicates that certain coprocessor zero instructions (as defined in the MrPS RISC architecture) are being execmed. The tables of instructions below ftuther define the insmwdons encoded by setting CON bit 86, The ins;tructions defined for instruction formats 20. 30, 40, and 50 are capable of performing many of the operations commonly performed in typical programs. However, routines may need to perform operations of which these instructions are incapable. While most of the instructions in the routine may be coded using instruction form= 20-50, several instructions may require additional encodings. For example, access to a regi= not included within the subset of available registers in formats 20- 50 may be needed. Additional instructions not included in the instructions encoded using forinats 20- 50 may be needed. For these and other masons.. the extend opcode and extended instruction formats 60-80 are defined.

Instruction decompressor 12 examines opcode field 22 in order to detect the extend opcodc. The extend opcode is one of the opcodes defined to use instruction format 50 in the present embodiment, although the bits included in imm-.diate ficid 52 are assigned differing interpretations depending upon the extended instruction format coded for the particular extended instruction- The extended instruction formats include a second opcode field (e.g. fields 66 and 78) which identify the particular extended instruction.

Addition of the ext-end opcode and extended instruction formats allows for many instructions to be encoded using the narrower instruction formats 20-50, but still have the flexibility of the wider extended instruction formats when desired. Programs which occasionally make use of the functionality included in the extended insmxdon formats may still achieve a reduced memory footprint, since these programs may be encoded using compressed instructions and many of the compressed instructions may comprise 16-bit compmssed instructions.

An embodiment of inicroprocessor 10 may handle the extended instructions by fetching 16-bit instruction portions and detecting the extend opcode. When the extend opcode is detected, a NOP may be transmitted to processor core 16 and the remaining 16-bit portion of the extended instruction may be fetched.

The extended instruction is decompressed and provided as the next instruction after the NOR Additionally, instruction decompressor 12 handles cases wherein a portion of the extended instruc-tion 12 is available while a second portion is unavailable. For example. two portions of the extended instruction mav lie within two distinct cache lines within instruction cache 14. Therefore. one portion of the instruction may be fetched from instruction cache 14 while the other portion may not rei ide'within instruction cache 14. The portion may then need to be stored within instruction clecompressor 12 until the remaining portion is available.

Finally, Fig. 4D is an instruction format 90 used to explicitly expand the JAL instruction of the MIPS RISC instruction SeL Tn-. JAL instruction is often used as a subroutine call instruction. Subroutines mav be stored in memory at a great distance (address-wise) from the calling routine. Therefore, having the largest possible range of relative offsets (via an intmediate field 92 comprising 26 bits) is importara. for the JAL instruction- Additionally, an "change bit 94 is included in the instruction mcoding. The exchange bit is used io indicate the compressedinon-co'mpressed nature of the instructions at the target. address. If the bit is set, the target instructions are compressed instructions. If the bit is clear, the target mmuctions are non-compressed in:structions. The value of exchange bit 94 is copied into bit 0 of the program counter within processor core 16.

- Bit 0 of the program counter may always be assumed to be zero, since the sixteen bit and thirty-two bit instructions occupy, at least two bytes each and instructions are stored at aligned addresses. Therefore, bit is a useful location for storing the compression mode of the current routine. Processor core 16 increments fetch addresses by 2 (instead of 4) when bit 0 is seL thereby fetching 16 bit compressed instructions through instruction decompressor 12.

Each instruction within the compressed instruction set employed by microprocessor 10 uses at least one of the instruction formats shown in Figs. 3A-3D and Figs. 4A-4D. it is noted that opcode field 2-1 is included in each instruction format, and is located in the same place within each i:nstruction format The coding of opcode field 22 determines which instruction format is used to interpret the remainder of the instruction. A first portion of the opcode field encodings is assigned to instruction format 20; a second portion of the opcode field encodings is assigned to instruction format 30; etc.

As used herein. the term "irtscrtiction field" refers to one or more bits within an instruction which are grouped and assigned an interpretation as a group. For example, opcode field 22 is comprises a group of bits which are interpreted as the opcode of the instruction- Additionally, &st and second register fields 24 and 26 comprise register identifiers which identif a storage location within processor core 16 which store operands of the instruction. Additionally, the term immediate field refers to an instruction field in which immediate data is coded. Immediate data may provide an operand for an instruction. Alternatively, immediate data may be used as an offset to be added to a register value, thereby producing an address. Still further. immediate data may be used as an offset for a branch instruction.

Figs. 5A-6F are tables listin an exemplary compressed instruction set for use tn- one particular 9 implementation of microprocessor 10. The particular implementation employs the MIPS RISC architecture within processor core 16. Therefore. the instruction mnemonics listed in an instruction column 100 of the tables correspond to instruction mnemonics defined in the MIPS RISC architecture (or defined for the instruction assembler, as described in -MIPS RISC Architemim, by Kane and Heinrich. Appendix D, Prentice Hall PTPL Upper Saddle River, New Jersey, 1992, incorporated herein by refe=ce) with the following exceptions: CMPI, MOVEI, MOVE NEG, NOT. and extend. These instructions =late to the following MIPS instructions (RS and RT refer to the 16-bit RS and RT):

CNIPI XORI S24, RS. imm8 MOVI ADDIU RS, $0, simm8 13 MOV ADD RS, SO, RT NEG SUB RS, SO, RT NOT NOR RS, $0, RT extend (described above) Additionally, the instruction tables use several symbols. In an operands column 102, the symbols rs, rt, xs, xt, and rd are used. Rs and xs refer to second register field 26 (or second register field 76), while rt and xt refer to first register field 24 (or first register field 74). Similarly, rd refers to third instruction field 32 (or third instracdon field 82). As mentioned for one embodiment above, first. register field 24, second register field 26, and third register field 3 comprise three bits each. 'Table I below lists the mapping of the field - encodings Gisted in binary) to registers in the MIPS RISC architecture for then symbols. Other mappings are also contemplated, as shown f=hcr below. Names assigned according to MEPS assembler convention are also listed in Table 1.

Table 1: RegLuer Mappings Field Encoding R.S. RT. RD XS,

000 S8 (to) S24 (t8) 001 S I (at) S17(sl) S2 (VO) SIS(s2) Oil S3 (vl) S19(s3) S4 (aO) S28 (gp) 101 S5 (al) S29 (sp) S6 (a2) S30(sg) 111 $7 (0) S31 (m) As shown in table 1, up to 16 registers are available for use in compressed instructions having registers fields

24, 26, or 32. Because each register field is three bits, only eight registers are available for a given opcode.

Instructons; which may access all six= registers are assigned rwo opcodes in the instruction tables below.

Register selection is thereby a f4riction of both a register field and opcode field 22. Advantageously, register fields may be c=ded using fewer bits while still providing select instructions which may access a large group of registers.

Also listed in operands column 102 are symbols for the immediate fields 32, 42, 64, and 72. The symbol "imm" indicates an immediate field is included. If imm" is preceded by an "s", the immediate field is signed and the decompression of the immediate field into the decompressed instruction is performed by sign extending the iinmediate field. If "imm" is not preceded by an S", the immediate field is unsigned and immediate field decompression involves zero extending the immediate field. In one embodiment, immediate field decompression for load/store instructions comprises right rotation of the immediate bits by one bit for halfwords and two bits for words, followed by shifting of the immediate bits left by one bit for halfwords and two bits for words. Effectively, a seven bit immediate field is provided for words and a six bit immediate field for halfwords (in the 16-bit instruction formats). The MIPS RISC architecn= defines that data addresses corresponding to load/store instructions are aligned for each instruction included in the exemplary compressed instruction set. Therefore, the least significant bit (for halfwords) and the second least significant bit (for words) may be set to zero. Bits in the compressed immediate field need not be used to specify these bits.

14 finally, nimnin is post-fixed with a munber indicating the number of bits included in the imnuxiiate field.

Opcode field 22 and function field 29 are decompressed as well. More particularty, opcode field 22 and function field 28 identify the instruction within the MIPS R1SC architecMrr, in accordance with the tables shown in Figs. SA-6F. The opcode and Rinction fields of the decompressed instructions are coded in accordance with the MIPS RISC architecture definitiorL Figs. 5A and 5B depict a table 110 and a table 112, respectively. Tables 110 and 112 list instructions from the exemplary compressed instucticn. set which use instruction format 20 shown in Fig. 3 A. Instruction column 100 and operands coll-n 102 are included, as well as an opcode column 106 and a firricrion column 104. Opcode column 104 and &nction column 106 inctude hexadedmal munbers, and correspond to opcode fi;Id 22 and function field 28, rcs-pba-

Table 110 includes several instructions which have an wimm " coding in Rinction coluinn 104. The wimm5 " coding appears for the load/storc instructions within table I 10, and indicates that function field 28 is used as an immediate field for these instruction& For other instructions, function field 28 is used in conjunction with opcode field 22 to identify a particular instruction within the compressed instruction set.

Additionally, opcode I d is labeled as special in table 110. ne special instructions have a specific intapretation of hinction field 28. In particular, if the most significant bit of the function fidd is clear, then the instruction is defined to be:

ADDrU rt, rs, simin4 wherein the "simm4" operand is fornied from the remaining bits of function field 28. If the most significant bit of function field 28 is set, the instruction is defined to be:

ADDrU xt. xs, simm4 except for rwo special cases. If second register field 26 is coded to a zero, then the instruction is:

MOVEIxt, imm4 wherein again the imm4 operand is formed from the remainder of ftinction field 28. Lastly, if second register &M 26 is coded to 5 (hexadecimal), then the instruction is defined to be:

ADDIU sp, simm9 wherein the simm9 operand is formed from the remaining bits of function field 28 and first register field 24.

The low order two bits of the simm9 operand are set to zero.

It is noted that the destination of the SLT and SLTU instructions shown in table I 10 is the t8 register (register S24) according to one embodiment.

Table 112 shows an "imnO " and "inun6" operand for several insauctions. The irnm3 operand is coded into second register field 26, and the "imrW operand is coded into both second register field 26 and first register field 24.

Additionally, table 112 includes the jump register (JR) insauction, having second register field 26 as an operand. However. it is noted that in one embodiment subfield RT1 of first register field 24 is used in conjunction with second register field 26 to specify any of the MIPS RISC architeaure re-gisters for the JR instruction.

Turning now to Fig. 5C, a table 114 including instruction column 100. operands column 102, opcode column 106, and function column 104. Table 114 lists instructions from the exemplary instruction set which use instruction format 30 shown in Fig. 3B. Certain itstructions within table 114 have hardcoded destination registers (Le. the destination registers cannot be selected by the programmer, other than by using a different opcode). For these iristructions. third register field 32 is combined with function field 34 to store the function field encoding shown in function column 104, Addirionally, an insaniction is down which has an immediate operand in function coilann 104 and operands column 102. This instruction uses second register field 26 in - conjunction with function field 34 to code the corresponding immediate field used by the instruction.

Fip 5D and 5E are tables 116 and I IS showing the instructions from the exemplary compressed - instruction set which employ ftmtruction formats 40 and 50, respectively. It is noted that the extend instruction is shown in table 118. However, the extend instrtiction actuailly indicates that the instruction is a 32-bit compressed insmwtion which uses one of instruction formats 60, 70, or 80.

Turning now to Figs. 6A and 6B, a table 120 and a table 122 are shown. Tables 120 and 122 depict those insauctions; from the exemplary compressed instruction set which are encoded using instruction format 70, shown in Fig. 4B.

Table 120 includes instruction column 100 and operands column 102, and further includes an opcode column 108. Opcode colurrui 108 is similar toopcode column 106, except that the opcode encodings shown in opcDde column 108 correspond to opcode field 79.

Table 122 includes an RT column 109 which corresponds to first. register field 74. The coding of the

RT field in the instructions shown in table 122 indicates which instruction is selected. The instructions shown in t3ble 122 share a specific encoding in opcode field 79. In one embodiment- the specific ancoding is 00 (hexadecimal).

Figs. 6C, 6D. 6E. and 6F are tables 124, 126, 128, and 130 which depict insauctions from the exemplary compressed instruction,et which are encoded according to instruction format 80. Tables 124, 126, and 130 include a function column 107 which corresponds to encodings; of function field 94. Table 128 includes an RS, RT coluirm 105 which will be explained in more detail below.

Operands column 102 for table 124 includes immediate operands for certain instructions. The Rimird. operand is coded into second register field 76. The "imml5" operand is coded into a combination of first. register field 74, second register field 76, and third register field 82.

The instructions listed in table 128 are identified via encodings of second register field 76, as shown in RS, RT collymn 105. Certain instructions are identified via second register field 76 in conjunction with first register field 74. Those instructions for which RS. RT colunui 105 includes an asterisk for the RT portion an identified via s=ond rezister field 76, while those instructions for which RS, RT column 105 does not include an asterisk are identified by second register field 76 in conjunction with first regi=r field 74. Instructions which are not identified via first register field 74 may use first register field 74 to encode an operand, The instructions listed in tables 128 and 130 are instructions for which COPO bit 86 is set, while inmctions listed in tables 124 and 126 are encoded with CON bit 86 clear.

Certain instruc-dons in table 128 include an "imm6" operand. Tle "imm6" operand is coded into function field 84. Addicionallv. function field 84 is used to indicate the instructions shown in table 130 when

16 second register field 76 is coded to Ix (hexadecimal). wherein 'Y' indicites that the low order bits are don't cared.

Turning now to Fig. 7, a first addressing window 150 and a second addressing window 152 are shown according to one embodiment of microprocessor 10. At the center of addressing window 150 is the value of a base register (represented as Reg. on the left side of addressing window 150). The value of tL- base register identifies an address within the main memory subsystm Addressing window 150 represents the range of addresses around the value of the base register which are accessible to a load/store instruction in the non compressed instruction set according to one embodiment of the non- compressed instructiOll SCL 'rhe non compressed instruction set specifies that load/store inst:ructions form the address of a memory operand via the slum of a value stored in a base register and a sixteen bit signed immediate field. In such an embodiment, the range of addresses has an upper boundary of 327677 greater than the base register and a lower boundary of 32768 less than the base registu. Other embodiments may include larger or smaller range& As used hem-in, the term "base register" refers to a re_=zr which is specified by a load/store instruction as storing a base addres, to which the signed immediate field is added to form the address of the memory operand operated upon by the ins;trtiction.

As shown in table i 10, for example, load/store insauctions within the 16bit portion of the exemplary compressed instruction set include a five bit inimediate field. This field is rotated right two bits and then shifted left two bits for word-siz memory operands. forming a seven bit immediate field (the largen of the immediate fields which may be formed using the five bits, according to one embodiment). 'Mee seven bit immediate field is then zero extended to fom a positive offset from the base register in the corresponding decompressed instruction. A subrange 154 of addresses am therefore available for access by compressed instructions. Within addressing window 150, subrangc 154 has an upper boundary of 127 greater than the base register and a lower boundary of the base register. However, subrange 154 may vary in size from embodiment to embodiment.

While subrange 154 may work well for many load/store instructions, a different subrange may be emplayed for use with the global pointer register. 71c global pointer register is a register assigned bN- software convention to locate an area of memory used for storing global variables. A global variable is a variable which is available for access from any routine within a program In contrast, a local variable is typically accessible only to a particular routine or group of routines. In the MIPS instruction set. for example, register S28 is often used as the global pointer register.

The area of memory around the global pointer register may therefore be viewed as a table of global variables. Each global variable is assigned an offset within the table. The offset corresponds to a particular immediate field value which may be added to the global pointer register in order to locate the global variable.

For the embodiment shown in Fig. 7, for exarnple, a 64 kilobyte table may be allocated for global variables as shown along the left side of addressing windows 150 and 152.

If compressed immediate fields are decompressed as described for addressing window 150, then the global variable table includes a sccton which is accessible to compressed instructions (corresponding to subrange 154) which is between two subranges 156 and 158 accessible to non-compressed instructions. As noted abave. microprocessor 10 may support programs in which some routines am coded with non-compressed instructions while other routines are coded with compressed ins=ctons. Allocating global,=bles in a particular program is complicated by the division of the non-compressed global variable subranets 156 and 158 of addressing window 150. Global variables may be allocated into subrange 158, for example, and then 17 global variable allocation must continue in subrange 156 (for noncompressed instrtictions). In other words, subrange 154 must be bypassed for global variables accessible to non- compressed instructions.

Microprocessor 10 may erriplay a decompression of the compressed immediate field for load/store instructions using the global pointer (GP) register which leads to addressing window 152. Addressing window 152 includes a subrange 160 accessible to compressed insumcdons and a subrange 162 ac le to aon compressed instructions. Advantageously, subrange 162 is a contiguous block of memory. Global variables for acces by non-compressed instructions may be allocated into subrange 162, while global variables for access by compressed instructions may be allocated into subrange 160. Essentially, submage 160 and subrange 162 form distinct tables of global variables for access by compressed and non- compressed instractions, respectively.

1 Addressing window 152"is achieved by decompressing the compressed immediate field as described above, except that the mos, significant bit of the decomprewed immediate field is set. If the compressed immediate field is coded with binary zeros, then the decompressed immediate field is 8000 (in hexadecimal).

Sir= the decompressed immediate field is interpreted as a signed field for load/sEore instructions. the 8000 value is the most negative number available in the decompressed immediate field- Other encodings of the compressed immediate field are decompressed into negative numbers which form subrange 160. Subrange 160 forms the lower boundary of the range of addresses represented by addressing window 152 as shown in the embodiment of Fig. 7.

As used herein, the terra memory operand refers to a value stored in a memory location within the main memory subsystem. Load instrixtions may be used to transfer the memory operand to a regLser within microprocessor 10. Conversely, store instructions may be used to transfer a value stored in a register into the memory operand storage location. A memory operand may be of various sizes (i..-. numbers of bytes). In one embodiment, d= sizes are available: byte, haffword, and word. A halfword comprises two bytes, and a word comprises four bytes. Other memory operand sizes are contemplated for other -embodiments.

Turning to Fig. 8, a block diagram of exemplary hardware within instruction decompressor 12 for decompressing the immediate field of a load/store instruction is shown. It is noted that multiple copies of the exemplary hardware shown in Fig. 8 may be employed to concurrently decompress multiple load/store histrimbons. The exemplary hardware shown in Fig. 8 is described in terms of microprv-essor I OB. However, similar hardware may be employed within microprocessor 10A. The exemplary hardware includes a iinmediate field decompressor 170 and a register decoder 172.

When an instriiction is conveyed to instruction decompressor 12B from inon cache 14B, a portion of the instruction comprising the compressed immediate field for load/store instructions is convcyed to immediate field decompressor 170 upon a compressed inirriediate bus 174. For the exemplary instruction set described in Figs. 3A-6F, the compressed immediate field comprises function field 28 (shown in Fig, 3A).

Additionally, the base register field for the compressed load/store instruction is conveyed upon a base register bus 176. For the exemplary instruction set shown in Figs. 3A-6F, the base register field comprises second register field 26.

Register decoder 172 decodes the register identified upon base register bus 17 6. If the base register is the global pointer register, register decoder 172 asserts a GP signal upon GP line 178 to immediaL- field decompressor 170. Otherwise. register decoder 172 deasserts the GP signal.

Immediate field decompressor 170 decompresses the compressed irnmediate field in one of rwo ways, dependent upon the GP signal. U the GP signal is deasserted. then immediate field de-compressor 170 clears the most significant bit of the decompressed immediate field. Conversely, immediate field decornpressor 170 is sets the most significant bit of the immediate field if the GP sigual is asserted. Therefore, a positive offm is created when a register other than the global pointer register is used as the base register. A negati'm off;et is created when the global pointer register is used as the base register. ln=ediate field decompressor 170 conveys the decompressed immediate field upon a decompremed immediate bus 180.

Fig. 9 illustrates the decompressed immediate field generated for load/store instructions according to one embodiment of the exemplary compressed instruction set. The compressed immediate field of load/store instructions which do not employ the global pointer register as the base register are decompressed as indicated by reference number 182. The decompression for bytes, balfwords, and words are shown separately, with each bit position of the decompressed immediate field (or offset) represented by a numerical digit or an "L". Bits i 0 fforn the compressed immediate fmld are shown in the respective bit locations of the decompressed field via the numerical digits, The least significant bit of the compressed immediate field is represented by the digit 0, and the most significant bit of the compressed immediate field is represented by a 4. The letter 'L" is used to indicate a bit position which is set to a binary zero.

Decompressed immedin, fields corresponding to bytes, halfwords, and words for load/store instructions which use the global pointer register as a base register are indicated by reference munber 184.

Similar to the decompressed fields indicated by reference number 182, the decompressed fields indicated by refe=ce number 184 depict numerals in bit positions which are filled with a bit from the compressed immediate field and the letter "L" is used to indicate a bit position which is set to a binary zero. Additionally, the most significant bit of each decompressed offset is set to; a binary one (indicated by the letter "M.

Turning next to Fig. 10, a flow ch= is shown depicting activities performed by instruction decompressor 12 in order to decompress instructions in accordance with the embodiment shown in Fig. 8.

Although the steps shown in Fig. 10 are illustrated as serial in narure, it is understood that v3zious steps may be performed in parallel.

Instruction decompressor 12 determines if a received instruction is a load/stcrt instruction (decision block 190). If the instruction is not a load/store instruction. the instruction is expanded in accordance with a mapping between the compressed instructions (as illustrated in Figs. 3A6"r7 and the corresponding decompressed instructions (step 192). If the instruction is a load/store instruction, then the base re-zMer specified by the instruction is examined (decision block 196). If the base register is the global pointer rtgismr, the immediate field is decompressed as indicated by reference number 184 in Fig. 9 (sEep 194). Alternativdy, if the base register is not the global pointer register, the immediate field is decompressed as indicated by reference number 1821 in fig. 9 (step 192).

In addition to decompressing load/store offsets in a difFerent manner for the global pointer register, microprocessor 10 also supports a compression mode for indicating which type of inscructions are being executed by microprocessor 10 (i.e. compressed or non-compressed). Fig. I I is a block diagram illustrating a portion of one embodiment of instruction decompressor 12. 'Me illustrated portion determines the compression mode for each routine executed by micropmcessor 10. The portion shown may be suitable for microprocessor I OB, and a similar portion rnay be employed by microprocmor IOA. Fig. I I depicts a mode detector 200.

When an instruction is fetched by processor core 16, the instruction is received upon an instruction bus 202bv mode detector 200. Mode detector 200 detects when the jump and link (JAL) instruction is fetched, and ftu-ther examines the exchange bit 94. If exchange bit 94 is set- the routine at the target address of the JAL instruction comprises compressed instructions. Therefore, the compression mode of the target routine is 19 compressed. Altemativelv, exchange bit 94 may be clear. In this case, the compression mode of the target routine is uncompressed.

In addition to specifying the compression mode for the target routine. the JAL instruction causes the address of the insauction following the JAL instruction to be stored into register S3 I of the 1\13PS RISC architecture. This register may subsequently be used with the IR instruction to return from the target routine.

Because the compression mode is stored as part of the address in this embodiment, the compression mode of the source routine is restored upon execution of the JR insmiction. Advantageously, routines encoded in compressed instructions may be intermixed with routines encoded in noncompressed instructions. The new compression mode is conveyed to processor core 16 upon a compression mode line 206. It is noted that mode dtoctor 200 may be included as a art of processor core 16 insmad of instruction decomDrtssor 12, in alternative embodiments.

The embodiment of mode detector 200 shown in Fig. 11 includes a storage 204 for a compression - enable bit. If compression is enabled, the compression enable bit is set. When instructions are fetched in compressed mode and compression is enabled, instruction decompressor 12 decompresses the instructions. If the enable bit is clear. instruction compression is disabled for microprocessor 10. Instruction decompressor 12 is bypassed when instruction decompression is disabled. Furthermore, mode detector 200 indicates that the compression mode is non-compressed when instruction compression is disabled.

As used herein, a routine is an ordered set of instructions coded for execution by microprocessor 10.

The routine mzy be coded in either compressed or non-compressed instructions. and is delimited by a subroutine call instruction and a return instruction. The delimiting subroutine call instruction is not included within. the routine. Instead, the subroutine call instruction mdicam the beginning of the routine via a target address included with the subroutine call instrtiction. The f= instruction of the routine is stored at the target address. Additionally, the addre of an inswiction within the routine including the subroutine call instruction is saved so that a retur instruction may be executed to M-turri to the calling routine. In the exemplary compressed instruction set depicted in Figs. 3A-6F, the jal instruction may serve as a subroutine call instruction. Alternatively, the jalr instruction may serve as a subroutine call instruction.

A routine ends with a return instruction, which causes subsequent insauction execution to return to the address saved when the corresponding subroutine call insrruction is executed. In other words, the target address of the return instruction is the saved address. For the exemplary compressexi iristruction set, the jr instruction may serve as a return instruction. Generally speaking, a target address is an address at which instruction fetching is to begin upon execution of the instruction corresponding to the target address.

Turning next to Fig. 12, a block diagram of one embodiment of register field decompression is shown.

Other embodiments of register field decompression at-. contemplated. The compressed register field corresponding to an instruction is corrveyed upon compressed register field bus 210. A register de-compressor block 212 receives the compressed register field. Additionally, at least a portion of the compressed register field is incorporated into the decompressed register field which is then conveyed upon decompressed register field bus 214. The decompressed register field is thereby formed by concatenating at least a portion of the compressed register field to the value generated by register decompressor block 2 12.

In one embodiment, the entire compressed register field is concatenated into the decompressed register field. Additionally, the remaining portion of the decompressed register field depends upon which register set the instruction accesses (e.g. xs vs. rs and xt vs. rt). A set selector signal is received upon set selector bus 216 for each register, indicating whether the xs (xt) or the rs (rt) register set should be used. If the set selector signal is asserted, then xs (xt) is selected. Otherwise, rs (rt) is selected. The set selector signal is asserted or deasserted based upon the opcode of the instruction being decompressed. in accordance with the exemplary, compressed instruction set shown in Figs. 5A-6F. For example, the register mapping between compressed and decompressed registers shown in Table I ma-y be employed. For such an example, register decompressor 212 may =ploy the following logic, wherein DR represents the decompressed register field, CR represents the compressed register field, and RH represents the corresponding set selector signal value:

DR[4:31 = OUL (RH & CR(211!CR[2:01)) 1C Several other register mappings are contemplated, examples of which are shown in tables 2-4 below, along with corresponding Verilog logic equations. It is noted that any register mapping may be =plTfcd by various erabodiments of microprocessor 10. Table 2: Second Exemplary Register Mappings Field Encoding RS. RT. RD XS,

000 $8 (to) S24 (t8) 001 $9 (ti) S25 09) S2 (VO) SI8(s2) Oil S3 (vl) S19(s3) S4 (0) S28 (gp) 101 $5 (al) S29 (Sp) S6 (a2) S30(sg) III S7 (0) $31 (ra) DR[4:31 - (RK (R14 & CR[21 I CR[2: 1])) 15 Table 3: Third Exemplary Register Mappings Field Enco-ding RS. RT. RD XS,

000 S16(sO) $24 (t8) 001 S I (at) S9 (ti) S2 (VO) sio (c) Oil S3 (vl) SII (0) S4 (0) $28 (gp) 101 S5 (al) S29 (sp) $6 (a2) S30(s8) ill S7 (0) S31 (ra) DR(4:3] = ((RH & CR(21 I!CR[2:01), RHI Table 4: Fourth Exemplary Register Mappings Eteld Encoding RS, RT. RD XS, XT 000 S16(sO) S24 (t8) 001 S17(sI) S25 (t9) S2 (vo) $I D (C) Oil S3 (vl) $11 (0) 21 $4 (aO) $28 (gp) 101 S5 (al) $29 (sp) S6 (a2) S-30(ss) III S7 (0) S3 1 (ra) DP44:31 = ((RH & CR(21 1! CR[2:1]), RH) As indicated by the assembler assigned names shown in tables 1-4, various registers are assigned to various fitrictions by software convention. For example, the MIPS assembler asmgm the following mmnings to registers:

table 5: Softwam Convention'for Register Names Regiz Software Name use so none Hardwired to S1 sat used by assembler S2.33 vo-VI Function results or static link $4.37 aO-a3 arguments for a subroutine ss-sis, TO49 Temporary registm not saved between subroutine calls S24 S25 S16 SZ3, S30 sO-s8 Saved between subrmnine calls S26.127 kO-kI Reserved for operating system S28 gp Global Pointer S29 sp Stack Pointer S31 M Rctarri address It is desirable to provide access to both temporary and saved registers to routines coded in compressed insmtcrions. Additionally, access to vO-v I, aO-a3, gp, sp, and m are needed to operate with existing software.

The register mappings shown balance these qualities with the desire for register decompressor 212 to o=rpy a &n1y small numbc- of gates. Advantageously, a useful set of registers is selected from the MIPS register set while still maintaining a low pte count within register decompressor 212.

Turning now to Fig. 13, an exemplary computer system 220 including microprocessor 10 is shown.

Many other computer systems employing microprocessor 10 are contemplated. Within computer system 220, microprocessor 10 is incorporated onto a semiconductor substrate 224 along with multiple 1/0 interfaces 222A 222N. The 1/0 interfa= interface to 1/0 devices external to substrate 224. An exemplary 1/0 interhice 222A may be a universal asynchronous (UART).

hficroprocessor 10 may be coupled to 1/0 interfaces 222 for communication therewith. Additionally, microprocessor 10 may be coupled to external interface logic 226, which further interfaces to one or more dynamic random access memory (DRW modules 228. DRAM modules 228 may store compressed and/or non-compressed instruction code, as well as data for used by the program represented by the compressed and/or non-compressed instruction code.

It is noted that the present discussion may refer to the assertion of various signals. As used herein, a signal is wasserted" if it conveys a value indicative of a particular condition. Corrversely, a signal is "deasserted" if it conveys a value indicative of a lack of a particular condition. A signal may be defined to be asserted when it conveys a logical zero value or, conversely, when it convn-s a logical one value.

22 Although a specific example of a compressed instru=on set is shown and described hatin, multiple variations. extensions. and modifications may be made to the exemplary compre insnction seL These variations. extensions. and modifications are contemplatedL The following Verilog lis;ring describes exemplary logic for instruction decompressar 11 Many different embodiments of the logic are contemplatezi, although the Verilog listing shown is one suitable example:

timescale I ns / I us module dayrisc_dp( xa, ci, dojal, ext, x Output[3 1:01 XO; H expanded inswaction out inpw(15:01 ci; H compressed insmuction in dojal; H do jal ext; H extend [10:0] extend bits wire =jal ext I dojal / ci(15:1 11 decodes xsp = ci[15:1 11 5'bOOOOO wire spany = -wdjal & ci(IS) & --ci[14] & -<i[l 11 wire splor2 = spany & --ci [ 131; wire special = splor2 & -ci[121; wire brjal = ci[15:121 - 4100001 wire br = bal & -.ci[ I I I; wire word = ci[15] & (-ext I --.ci(131) & ci[121 & ci[I 11 wire special3= --wajal & ci[I5:11] - 5'bl 1101; wire half = ci[15] & (-ext I --ci[13] I -d[121) & ci[l 11 & -specia13; wire opi = -ci(15] & ci[141 & -<121; wire opx = ci[15:12] - 4bOOOO I ci[151 & -ci[13] & ci(121 & ci[Il]; wire S11 = -Cajal & ci(IS: 111 - 51010110; wire rMO = -exl_jal & (--ci[151 & ci(141 & cill2l & -<ci[131 & ci[Ill)); wire snx = -ci[IS] & --ci[14] & (ci[13] I --ci[121) I ci[15:Ill 5'bOlOOI wire spccial2= splor2 & ci[12]; wire amm = --( xsp I br); wire exti = ext & ximm; wire x2z = spany & ci[12] wire x4z = spany I special3 wire - ci[ 15:11] - 5'bO 1111 wire ill = btal, I xn; wire rsza = -Cxtjal & ( i I I I slI I ci[ 15:11]5'bO 1000 / & decodes / wire J, r - special & ci[4:1] - 4WI00; wire jair = jr & ci[O]; wire negriot = sp=al & ci[41 & -<31 & ci[l] & ci[O]; wire rseqO = ci[8:61 == 313000; wire sp2x = special2 & --ci[Oj so wire slt = sp2x & cifl]; wire sp3x = spccW3 & ci(4] wire sp3sp - sp3x & ci[8:6] - 3 b Iv 1 / I decodes / wire i8 = --exl_jal & --ci[15] I sp3sp; wire i8s - i8 &-ill; wire rdrs = sp2x & -ci[ I I I special & ci(41 wire rdrt = sp=al &, -(ci[4] I ci[31) I jalr; wire rdrd - spccial2 & ci(O] I sll -! 23 -(ci[1511 wire shrs --d0jal & ( brJal I -= & xn I cif 14:111 - 4b,0000 & ci[4:21 3bOO & (ext 7 r.i[51 I x(JOI): ci[151)); wire rs5 - extjal I il I I jr & --<:i[O]; wire rsz W r= I sp2x & --ci[21 & -d[l] I negriot I sp3x & rseqO I shrs wire rtrs - -c=_jaj & opi I sp3 sp; wire rtrt - -< =_jai i rtrS I ir I --d[151 & --opi wire snsp3 - ci[31 & special3 & --(ci[41 & rseqO); wire snI - =sp3 & --sp3sp; wire snm = ci[IO) & --enjal & snx I snsp3 wire snh - snm I ci[101 & -cajal & br I x[101 & exti Wire Sall = exti & half ? ci[O]: snh; wire snl2 - exti &word? cif I]: sah wire xs - sp2x & cj[41 I sp3x I opx; WiTe xt - jair I sp2x & ci[3] I sp3r, is assign xopl] - -dojal & ci[151 & ( ext I -x4z) assign xo(301 = ex&xsp&x[101; assign xo(291 - -dojal & ci[141 & -< -ca & ci[151 & -.d[12] & -.cip 1] 20- assign xo[281 - -dojal&( ci[131&-(spanyl-ca&wordlspecL-d3)1-.ca&- d[151&--d[14]lbr); assign =(271 dojal I ci[121 & ext I --( spany I ci[151&ci(141&--d[I 1] assign xo[26] dojal I ci(l 11; wire(4:0] rs = rs.5 ? ci( 10:9] (xs,(ci[g) & xs I rseqO)), ci[8:61 assign xo[25:21] rs & (5(-rsz)); wirc[4:01 rt A (6110] ? xt: -<ci[9] I ci[51)), ci[10:91, ci[5] assign xo[20:16] rt & (S(rtrt)) rs & (5(rtrs)) 1 x(9:51 & (5(=jal)) I (rtxO, rLxO, 3bW); wire[4:0] rd IbO,!ai[4:21, ci[4:21 assign xo[15:11] rs & (5 (rdrs)) rt & (5 (rdrt)) rd & (5(rdrd)) I x(4:01 & 115(ext & -ximm I dojal)) I ( (2(slt I snh)), snh, snl2, snl I assign xo(10:6] rs & ((2(shrs)), (3 (shrsisn))) I ci[15:11] & (5(dojal)) x[4:0] & (5{cxd)) ( ci[II&-slL ci[OI&s1l. 11)0, ci[IOI&i8s. ci[91&igs I ci(l]&--xzjaI&ward) ( snm, mm, snm, sal, snl); assign xo(51 = ci[51 & (extjal I A) I ci[41 & special I ci[O] & -extjal & half I specia12 I ml assign xo[4] - ci[41 & -x4z I cifl] & sp3sp I sol 50 assign xo(31 = sp3sp ? ci[O]: ci[3]&-x2zlslt; assign xo(21 = ci[21 & - x2z7, assign xo[l] = ci[ 11 & -doial & word I sU I sp3sp assign xo[O] = ci[Ol & -dojal & half I sH I sp3sp specW2 & ci[2] 55 endmodule In accordance with the above disclosure, a microprocessor has been descnbed which mv:cutes instructions from both a compressed instruction set and a non-compressed instruction set. The microprocessor expands the compressed instructions into decompressed instructions or directly decodei the compressed instructions. Advantageously, routines coded using the compressed instruction set occupy a smaller amount of 24 mernory than the corresponding routines coded in non-compressed insmictions. M=ory formerly occupied bry such routines may be fited for use by other routines or data operated upon by such routines. Numerous variations and modifications will become apparent to those sialled in the art once the above disclosure is fully appreciated. It is intended that the following claim be interpreted to embrace an such v==ons and modifications.

Claims (1)

1. CLAIMS:

   1. An 3ppararus for ---tecuring instructions from a variable-length compressed insmutan SCL Comprisinr.

   an instruction de-compressor (12A, 12B) coupled to receive compressed hsmwdons ('20, 30, 40, 50, 60, 70. 30, 90) which are members of said variable-lerigth compressed instruction set, wherein said instruction decompressor is configured to demmprtss said compressed instru=ioas into decompressed instrucdons, and wherein said h=wdon decompressor is configured to examine a first opcode deld (221) of a particular m qr, -; ad insnction, and wherein said k=nxd= decompt r is coafigtomd to detemmine dw said partcular 10 compressed instracdon is an extended Instruction (60, 70, 90, 90) hving a lirst fted length if said f1m opcode ffeld is coded as am extend opcode, and whertin said izwractiam decompres= Is configured to detemme that said particular compressed instruction is a non-. extended instruction (20, 30, 40, 50) having a second fixed length if said first opcode field is coded as a second opcode different than said extend opcode, and wherein said extended 15 instruction includes a second opcode filed (66,78), and wherein said instruction decompressor is configured to decompress said second opcode field of said extended instruction into an decompressed opcode field within a decompressed instruction, and wherein said instruction decompressor is configured to decompress said first opcDde field of said non--extended instruction into said decompressed opcode field. 20 2. The apparatus as recited h daim. I wherein said am fi;-,ed length is a first number of bytes which is V=W than a second auMbe.- of bytes corresponding to said second ffixed length.

   3. The apparatus as r=ted in claim 2 wherein said first number is greater than said second number by an inteam, factor.

   4. The apparatus as recited in claim 3 where= said integger factor is Mo.

   examin s. The apparam as recited in clairn I wherein said bLmuctioa decampressor is =nfirzred to e said second opcodc field in order to determine how to decompress said wamded ins=ctiOn- 6. 'rhe apparam 3s recited in claim I funher compr-ising a proctssor cor.- (16) c-Oriagurttl to ext-Cute said decompressed insmtctions.

   7. ne 3pp=tLs as recited in claim 6 wherein each compressed instruczion corr=onds to one decompressed inmcdon.

   i ed ins cd -^ss S. The 3ppamw as recitcd in clairn 1. wherzina, first one of said comp s Ml ons is COdable to acc 26 a first subset of registers defined for a corresponding non-compressed - ifistrIctinn ser. and whercht a second one of said compressed instructions is codable to access said first subset of registers and is further codable to access a second subset of registers.

   9. The apparatus as recited in claim 8 wherein said second one of said compressed instructions is assigned a first opcode encoding and a second opcode encoding.

   10. The apparatus as recited in claim 9 wherein said fim opcode encoding indicates that said second one of said compressed immctions is coded to access one of said E= subset of registers.

   11. The apparatus as recited in claim 10 wherein said ins=ction decompressor is configured to decompress said second one of said compressed instructions using a first mapping of compressed register oodings to decompressed register codings, wherein said fim mapping maps each compressed register coding to a decompressed register coding within said first subset 12. The apparatus as recited in claim I I wherein said second opcode encoding indicates that said second one of said compressed instructions is coded to access one of said second subset of registers.

   13. The apparatus as recited in claim 12 wherein said in=ction decompressor is configured to decompress said second one of said compressed instructions using a second mapping of compressed register codings to decompressed register codings, wherein said second mapping maps each of said compressed register codings; to a decorrivressed re-enster coding within said second subset of registers.

   14. The apparatus as recited in claim 9 wherein said second one of said compressed instructions includes a am register field (26) and a second register field (3 M.

   15. The apparatus as recited in claim 14 wherein said insrtruction decompressor decompresses said first, register field according to said fim subset of registers if said E= opcode encoding is used.

   16. The apparatus as recited in cLaim, 15 wherein said iiistruction decompressor decompresses said first register field according to said second subset of registers if said second opcode encoding is used. 17. The apparams as recited in claim 16 wherein said second one of said compressed instructions is assigned a third opeode encoding, wherein said decompressor decompresses said second register field using said second 35 subse, of re- gisters if said third opcode encoding is used.

   13. The apparanis: as recited in claim 17 wherein said second one of said compressed hmllctions is assigned a fourth opcode encoding, wherein said decompressor decompresses said first register field and said second 27 register field using said second subset of registers if said fourth opr:odeencqding i t1sed.

   19. The apparatus as recited. in claim 9 wherein said first opcode encoding and said second opcode encoding differ in bits included in a function field (28, 34) of said second one of said compressed instructions.

   20. The appamms as recited in claim 1, wherein said instruction decompressor is configured to decompress a compressed register field (26, 32) of one of said corVressed instructions into a decompressed register field of a corresponding decompressed instruction responsive to a fim value coded into said compressed revver field and a second value coded into said fim opcode field of said compressed instriiction.

   to I I - 21. The appmratus as recited in claim 20 wherein said instruction decornpressor is configured to select one of multiple mappings from compressed register field mcodings to decompressed register field enoodings in response tn said second value 22. The apparatus as recited in. claim 21 wherein said instruction decompressor is configured. to select one of said decompressed register encodings from said one of said multiple mappings in response to said first value.

   23. The apparatus as recited in claim 22 wherein a particular instruction is assigned a first opcode encoding and a second opcode encoding, and wherein said instruction decompressor, upon receipt of said particular instruction having said first opcode cricoding selects said one of said multiple mappings for decompressing said compressed register field 24. The apparatus as recited in claim 23 wherein said instruction decompressor, upon-receipt of said particular instruction havinc, said second - opcode encoding, is configur:A to select another one of said multip!e mappings CP for decompressing said compressed register field.

   25. The apparatus as recited in claim I wherein said instruction decompressor is configured to decompress a compressed register field (26, 32) of a compressed instriiction into a decompressed register field of a decompressed instruction, wherein said b:istrucdon decompressor forms a fimt portion of said decompressed register rield by copyin at le= a portion of said compressed register field thereto, and wherein said 9 instruction decompressor includes a logic block (212) which is configured to operate upon said compressed register field to produce aremaining portion of said decompressed register field 26. The apparatus as recited in claim 25 wherein said portion of said compressed rtgister field comprises an entirety of said compressed register field- 2-7. The apparatus as recited in claim 25 wherein said logic block is configured to select a register mapping from compressed mVgcr field encodings to decompressed register fied'd encodings in response to a signal 28 received from said instruction decompressor.

   28. The apparatus as recited in claim 27 wherein said instruction decompressor is configured to assat said signal upon detection of a first opcode ancoding within said first opcode field, said f= opcode encoding assigned to a particular instruction, and wherein said instruction decompressor is configured to deassert said signal upon detection of a second opcode encoding within said fim opcode field. said second opcode encoding assigned to said particular instruction.

   29. A method for expanding compressed instructions into decompressed instructions, comprising:

   deterrnig that a compressed instruction (20, 30, 40, 50, 60, 70, 80, 90) is an extended instruction (60, 70, 80) having a first fixed length if an opcode field (22) of said compressed instruction is an extend opcode, wherein a number of bytes included in said compressed instruction is defined by said fim fixed length if said compressed instruction is said extended instmcdon, and wherein said extended instruction includes a second apcode field (66, 78); deterrnining that said compressed in=ction is a non-extended instruction (20, 30, 40, 50) bavtng a second fixed length if said opcode field of said compressed instiuction is a second opcode different dm said extend opcode, wherein said number of bytes is defined by said second fixed length if said compressed ias=ction is said non-extended instruction; and decompressing said compressed instructon. into a decompressed instruction, said decompressed instruction including a decompressed opcode field, wherein said decompressing includes decompressing said second opcode field into said decompressed opcode field responsive to said determining that said compressed ins;truction is said extended inmction, and wherein said decompressing includes decompressing said opcode field into said decompressed opcode field responsive to said determining that said compressed in=ction is said non extended irimcdon.

   30. The method as recited in claim 29 further comprising fetching compressed ins=ctions in quantities a.7 defined by said second fixed length.

   3 1. The method as recited in claim 30 further comprising forming said extended instruction, when detected, from a f= of said quantities in which said =end opcode is detected and a second of said quantities Which is immediately subsequent to said fim of said quantities.

   32. The method as recited in claim 29 further comprises identiMna a particular --Ktcnded instruction, ' 9 said second opcode field.

   29 33. The method as recited in claim 32 wherein said decompressing comprises ideriffying an extended instruction fonrut (60, 70, 80) corresponding to said particular extended instruction.

   34. The method as recited in claim 33 wherein said decompressing further corrTrises interpreting bits within said particular =ended instruction according to a plurality of instruction fields within said extended instruction format.

   35. The method as recited in cktim 29 wherein said decompressing comprises identffring a non-ex:tended instruction format (20, 30, 40, 50) c6rresponding to said non-=ended instruction from an encoding of said opcode field 36. 7he metod as recited in claim 35 wherein said decompressing further comprises interpreting bits from said rim-crtended hstruction according to a second plurality of instruction fields within said non-extended instruction format.

   37. The method as recited in claim 29, further comprising decompressing a partiadar compressed instruction having a first register field (26, 32) using a first register mapping from compressed register indicators to decompressed res:ister indicators for decompressing said first register field if said particular compressed instruction is encoded using a first opcode; and decompressing said particular compressed instruction having said first register field using a second register mapping from compressed register indicators to decompressed register indicators for decompressing said first register field if said particular compressed instruction is encoded using a second opoode.

   38. Tbe method as recited in claim 37 wherein said particular compressed instruction further includes a second register field (26, 32).

   39. The method as recited in claim 38 further comprising decompressing said second register field using said second register mapping if said particular compressed instruction is encoded using a third opcode.

   40. The method as recited in claim 39 further comprising decompressing said second register field and said first register field using said second register mapping if said particular compressed ins=ction is encoded using a fourth opcode.

   4 1. The method as recited in claim 37 further comprising decompressing a seconcl particdar c,)mPr=cd instruction using said first mapping.

   42. The method as recited in claim 29, 5arther corqrising:

   directly copying at least a portion of a compressed register field (26, 32) within one of said coapressed instructions into a portion of a decompressed register field of a con-Monding decompressed instruction; and logically operating upon siid compressed regis= field to produce a remaining portion of said decompressed register field.

   43. The method as recited in claim 42 wherein said portion of said compressed regis= field comprises an entirety of said compr=ed register field.

   44. The method as recited in claim 43 wherein said portion of said decompressed regL= field receiving said entirety of said compressed register field comprises a phn-ality of least signiflicant bits of said decompres;sed register field.

   45. The method as recited in claim 42 further comprising logically opm-. dmg upon an opcode field (22) of said compressed instrucdon to produce said remaining portion of said decompressed register field.

   46. The method as recited in claim 45 wherein said logically operating upon said opcode field comprises selecting a first register mapping in response to a first opoode encoding in said opcode field.

   47. The method as recited in claim 46 wherein said logically opm-aring upon said opcode field Rather comprises selecting a second register mapping in response to a second opcode encoding in said opcode field.

   a 48. The method as recited in claim 47 wherein said first opcode encoding and said second opcode encoding are assigned to a particular instruction31 49. An apparatus substantially as hereinbefore described as an embodiment and as shown in the corresponding accompanying drawings.

   50. A method substantially as hereinbefore described as an embodiment with reference to the corresponding accompanying drawings.

   I - I 32