CN111381877B

CN111381877B - Decompress instruction decoding method, data processing method, decoder and data processing device

Info

Publication number: CN111381877B
Application number: CN201811623548.6A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-12-28
Filing date: 2018-12-28
Publication date: 2022-12-02
Anticipated expiration: 2038-12-28
Also published as: CN111381877A

Abstract

The application relates to a DECOMPRESS instruction decoding method, which expands the hardware structures of an instruction set and a decoder by analyzing the DECOMPRESS instruction, improves the decoding function of the decoder and perfects the operation of the DECOMPRESS instruction.

Description

Decompress instruction decoding method, data processing method, decoder and data processing device

Technical Field

The present application relates to the field of information processing technologies, and in particular, to a DECOMPRESS instruction decoding method, a data processing method, a decoder, and a data processing apparatus.

Background

With the continuous development of data processing technology, people have higher and higher requirements on data processing compatibility, and more data are processed, so that more and more data processing methods and data processing devices are provided to solve the problem of data bit number.

The traditional data processing instruction can directly decompress data to obtain decompressed data, and an instruction method for decompressing compressed data with a specific format is lacked, and a method for analyzing the method is also lacked.

Disclosure of Invention

In view of the above, it is necessary to provide a DECOMPRESS command decoding method, a data processing method, a decoder, and a data processing apparatus capable of decompressing compressed data of a specific format.

A method of decoding a DECOMPRESS instruction, the method comprising:

acquiring the number of lines in a data block and the number of single lines in the data block in the DECOMPRESS instruction, and configuring a fourth operation of the DECOMPRESS instruction according to the number of lines in the data block and the number of single lines in the data block to obtain a fourth operand of the fourth operation, wherein the fourth operation is used for reading the data block of compressed data and sending out the read data block according to the fourth operand, the data block of the compressed data comprises a plurality of data headers and a plurality of data bodies, the data headers store the start addresses and the data lengths of the corresponding data bodies, the data bodies comprise compressed encoding values of the compressed data, and the fourth operand comprises an immediate number or a register number;

and acquiring destination data of decompressed data in the DECOMPRESS instruction, and configuring a fifth operation of the DECOMPRESS instruction according to the destination data of the decompressed data to obtain a fifth operand of the fifth operation, wherein the fifth operation is used for writing out the obtained decompressed data according to the fifth operand, and the fifth operand comprises an immediate number or a register number.

In one embodiment, the acquired instruction is analyzed, and the instruction is determined to be a DECOMPRESS instruction according to the instruction type and the instruction type in the instruction.

In one embodiment, if the fourth operand is an immediate, the fourth operation is used to read a data block of compressed data from a first storage device according to the fourth operand, where the first storage device is an off-chip storage device;

and if the fourth operand is a register number, the fourth operation is used for reading a data block of compressed data from a second storage device according to the fourth operand, wherein the second storage device is a chip memory storage device.

In one embodiment, the original address of the data header in the fourth operand is obtained according to the source address and the address offset of the data header in the DECOMPRESS instruction;

and configuring a fourth operation of the DECOMPRESS instruction according to the original address to obtain a fourth operand of the fourth operation, wherein the fourth operation is used for reading the data block according to a source address and an address offset of a data header in the fourth operand.

In one embodiment, a fourth operation of the demoframe instruction is configured according to the number of rows of a data header in the demoframe instruction, the line feed distance, and the number of single-row data headers, so as to obtain a fourth operand of the fourth operation, where the fourth operation is used to read the data block according to the number of rows of the data header in the fourth operand, the line feed distance, and the number of single-row data headers.

In one embodiment, the original address and the data length of the data body in the fourth operand are obtained according to the starting address and the data length in the data header in the fourth operand;

and configuring the fourth operation of the DECOMPRESS instruction by using the original address and the data length of the data body.

In one embodiment, the destination address of the decompressed data in the fifth operand is obtained according to the destination address of the decompressed data in the DECOMPRESS instruction;

and configuring a fifth operation of the DECOMPRESS instruction according to the target address of the decompressed data to obtain a fifth operand of the fifth operation.

A method of data processing, the method comprising:

acquiring a DECOMPRESS instruction, and analyzing the DECOMPRESS instruction to obtain a fourth operand and a fifth operand of the DECOMPRESS instruction;

reading a block of compressed data from a storage device to which the fourth operand is directed, and sending the read block of data, the fourth operand comprising an immediate or register number;

decompressing the read data block of the compressed data to obtain decompressed data;

and writing the decompressed data into a storage device pointed to by the fifth operation data, wherein the fifth operand comprises an immediate number or a register number.

In one embodiment, if the fourth operand is an immediate, reading a data block of the compressed data from a first storage device according to the fourth operand, and sending the read data block, wherein the first storage device is an off-chip storage device;

and if the fourth operand is a register number, reading a data block of the compressed data from a second storage device according to the fourth operand, and sending the read data block out, wherein the second storage device is a chip memory device.

In one embodiment, a data block of compressed data is read according to a source address and an address offset of a data header in the fourth operand, wherein the data block of the compressed data comprises a plurality of data headers and a plurality of data bodies.

In one embodiment, the data block of the compressed data is read according to the number of rows of data heads, the line feed distance and the number of data heads in a single row in the fourth operand.

In one embodiment, according to the destination address of the decompressed data in the fifth operand, the obtained decompressed data is written into the storage device pointed to by the fifth operand.

A decoder, the decoder comprising: the device comprises a first configuration unit and a second configuration unit, wherein the first configuration unit is connected with the second configuration unit;

the first configuration unit is configured to acquire the number of rows in a block and the number of single lines in the block of a data block in the demo press instruction, and configure a fourth operation of the demo press instruction according to the number of rows in the block and the number of single lines in the block of the data block to obtain a fourth operand of the fourth operation, where the fourth operation is configured to read a data block of compressed data according to the fourth operand and send the read data block, the data block of the compressed data includes a plurality of data headers and a plurality of data bodies, the data headers store start addresses and data lengths of the corresponding data bodies, the data bodies include compressed encoded values of the compressed data, and the fourth operand includes an immediate number or a register number;

the second configuration unit is configured to acquire destination data of decompressed data in the demo press instruction, and configure a fifth operation of the demo press instruction according to the destination data of the decompressed data, to obtain a fifth operand of the fifth operation, where the fifth operation is configured to write out the obtained decompressed data according to the fifth operand, and the fifth operand includes an immediate number or a register number.

A data processing device comprises a configuration unit, a data reading and writing unit and a compression and decompression unit, wherein the configuration unit is connected with the compression and decompression unit, the configuration unit is connected with the data reading and writing unit, and the compression and decompression unit is connected with the data reading and writing unit, wherein the configuration unit comprises a first configuration unit and a second configuration unit;

the data reading and writing unit receives a fourth operand and a fifth operand sent by the configuration unit, reads a data block of compressed data from a storage device pointed by the fourth operand according to the fourth operand, and sends the data block of the compressed data to the compression and decompression unit;

the compression and decompression unit receives the data blocks of the compressed data and decompresses the data blocks of the compressed data to obtain decompressed data;

the data reading and writing unit is further used for writing the decompressed data into a storage device pointed by the fifth operand according to the fifth operand.

According to the DECOMPRESS instruction decoding method, the data processing method, the decoder and the data processing device, the DECOMPRESS instruction is analyzed, the fourth operation of the DECOMPRESS instruction is configured to obtain the fourth operand of the fourth operation, the fifth operation of the DECOMPRESS instruction is configured to obtain the fifth operand of the fifth operation, the fourth operation and the fifth operation are completed according to the fourth operand and the fifth operand, the DECOMPRESS instruction is analyzed, compressed data in a specific format can be decompressed, and the method for processing the compressed data in the specific format is realized.

Drawings

FIG. 1 is a block diagram of the structure of a decoder in one embodiment;

FIG. 2 is a block diagram of a processor in one embodiment;

FIG. 3 is a block diagram of a data processing apparatus according to an embodiment;

FIG. 4 is a flowchart illustrating a method for decoding a COMPRESS instruction according to an embodiment;

FIG. 5 is a flowchart illustrating a first operation performed under different conditions in one embodiment;

FIG. 6 is a flow diagram illustrating the configuration of a first operation in one embodiment;

FIG. 7 is a flowchart illustrating a configuration of a second operation in one embodiment;

FIG. 8 is a flowchart illustrating a configuration of a third operation in one embodiment;

FIG. 9 is a flow diagram that illustrates a data processing method in one embodiment;

fig. 10 is a flowchart illustrating step S800;

FIG. 11 is a flow diagram illustrating a DECOMPRESS instruction decode method according to an embodiment;

FIG. 12 is a flowchart illustrating a fourth operation performed in various instances under an embodiment;

FIG. 13 is a flowchart illustrating a configuration of a fourth operation in one embodiment;

FIG. 14 is a flowchart illustrating a configuration of a fifth operation in one embodiment;

FIG. 15 is a flowchart showing a data processing method in another embodiment;

fig. 16 is a flowchart illustrating the step S1700.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The terms "first," "second," "third," "fourth," and "fifth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements recited, but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The instruction decoding method provided by the present application can be applied to the decoder 1000 shown in fig. 1. The first configuration unit 101 is connected to the second configuration unit 102, and the first configuration unit 101 is connected to the third configuration unit 103 through the second configuration unit 102.

Alternatively, the instruction may be a COMPRESS instruction or a DECOMPRESS instruction. The compact instruction may COMPRESS original data, divide the original data into data blocks, and COMPRESS the original data in the obtained data blocks to obtain compressed data, where the compressed data may be divided into multiple data blocks and may include multiple data headers and data volumes, the data header may include multiple data volumes, the data header stores a start address and a data length of a corresponding data volume, and the data volume may include corresponding compressed encoded data. The democompress command may DECOMPRESS the compressed data, which may be divided into a plurality of data blocks, may include a plurality of data headers and a plurality of data bodies, the data headers may include a plurality of data bodies, the data headers may store the start addresses and the data lengths of the corresponding data bodies, and the data bodies may include corresponding compressed encoded data.

Specifically, the first configuration unit 101 is configured to configure a first operation of the compare instruction, and obtain a first operand of the first operation. A fourth operation, also for the demolist instruction, is configured to obtain a fourth operand for the fourth operation.

The second configuration unit 102 is configured to configure a second operation of the complete instruction, so as to obtain a second operand of the second operation. And also for configuring a fifth operation of the DECOMPRESS instruction to obtain a fifth operand for the fifth operation.

A third configuration unit 103, configured to configure a third operation of the compare instruction, so as to obtain a third operand of the third operation.

The first operand may be a storage address of original data when the original data is read, and may be an immediate or a register number. The second operand may represent an identification of the original data to be compressed. The third operand may be represented as a destination storage address of a header when the header in the compressed data is written back, and may alternatively be an immediate or a register number. The fourth operand may represent the original storage address of the block of compressed data when the block is read, and may alternatively be an immediate or register number. The fifth operand may represent a destination storage address of the decompressed data when the decompressed data is written back, and may alternatively be an immediate or register number.

Alternatively, referring to fig. 2, the controller unit 11 in the processor 2000 may be used as the decoder 1000, wherein the controller unit 11 is connected to the operation unit 12, and the operation unit 12 includes: a master processing circuit and a plurality of slave processing circuits;

a controller unit 11 for acquiring input data and a calculation instruction; in an alternative, the input data obtaining and instruction calculating manner may be obtained through a data input/output unit, and the data input/output unit may be one or more data I/O interfaces or I/O pins.

The above calculation instructions include, but are not limited to: a forward operation instruction or a backward training instruction, or other neural network operation instructions, etc., such as a convolution operation instruction.

The controller unit 11 is further configured to analyze the calculation instruction to obtain a plurality of operation instructions, and send the plurality of operation instructions and the input data to the main processing circuit;

a master processing circuit 121 configured to perform a preamble process on the input data and transmit data and an operation instruction with the plurality of slave processing circuits;

a plurality of slave processing circuits 122, configured to perform an intermediate operation in parallel according to the data and the operation instruction transmitted from the master processing circuit to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master processing circuit;

and the main processing circuit 121 is configured to perform subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction.

Alternatively, the controller unit 11 may include: instruction cache unit 110, instruction processing unit 111, and store queue unit 113.

The instruction cache unit 110 is configured to store a calculation instruction associated with an artificial neural network operation.

The instruction processing unit 111 is configured to parse the computation instruction to obtain a plurality of operation instructions.

A store queue unit 113 for storing an instruction queue, the instruction queue comprising: and a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue.

Alternatively, the first configuration unit 101 and the second configuration unit 102 may be disposed in the instruction processing unit 111, and the instruction processing unit 111 obtains an instruction from the instruction cache unit 110, parses the obtained instruction, and configures the first operation and the second operation through the first configuration unit 101 and the second configuration unit 102.

Optionally, the controller unit 11 may further include:

the dependency processing unit 112 is configured to determine whether a first operation instruction is associated with a zeroth operation instruction before the first operation instruction when there are multiple operation instructions, if so, cache the first operation instruction in the instruction storage unit, and after the zeroth operation instruction is executed, extract the first operation instruction from the instruction storage unit and transmit the first operation instruction to the operation unit;

the determining whether the first operation instruction and a zeroth operation instruction before the first operation instruction have an association relation or not comprises the following steps:

extracting a first storage address interval of required data (such as a matrix) in the first operation instruction according to the first operation instruction, extracting a zeroth storage address interval of the required matrix in the zeroth operation instruction according to the zeroth operation instruction, if the first storage address interval and the zeroth storage address interval have an overlapped area, determining that the first operation instruction and the zeroth operation instruction have an association relation, and if the first storage address interval and the zeroth storage address interval do not have an overlapped area, determining that the first operation instruction and the zeroth operation instruction do not have an association relation.

For example, in an alternative embodiment, the main operation processing circuit may also include a controller unit, and the controller unit may include a main instruction processing unit, specifically configured to decode instructions into microinstructions. Of course, in another alternative, the slave arithmetic processing circuit may also include another controller unit that includes a slave instruction processing unit, specifically for receiving and processing microinstructions. The micro instruction may be a next-stage instruction of the instruction, and the micro instruction may be obtained by splitting or decoding the instruction, and may be further decoded into control signals of each component, each unit, or each processing circuit.

In an alternative, the instruction may be a COMPRESS instruction, and the instruction format of the instruction may be as shown in Table 1 below:

TABLE 1

The instruction category Name is used for determining a category of the instruction (the category of the instruction may include a COMP type instruction and other instructions, where the COMP type is 16), that is, the instruction category is used for determining whether the operation instruction is a COMP type instruction. The instruction Type is used for determining the Type of the COMP Type instruction, and the Type of the COMP Type instruction is used for indicating what function is implemented by the instruction, for example, when the instruction Type is 1, the instruction is a COMP instructions. The Head address Head addr, the Head address offset Head offset, the Head row number Head seg num, the Head row feed distance Head stride, and the single-row Head number Head num are used to indicate the target address of the Head to be written back. The instruction fields of the original Data source address Data addr and the original Data wrapping distance Data stride are used to indicate the original address of the original Data to be read.

Further, the instruction format of the complete instruction may further include: the configuration table address configaddr is used for storing the encoded value of the data in the compressed format.

Further, the instruction format of the complete instruction may further include flag bits of each instruction field, for example: a flag Packing en for indicating a Packing pattern parameter, specifically, when the Packing en is 1, a Packing pattern of compressed data is indicated. There is a flag bit Compress en for indicating the compression mode, and specifically, when the Compress en is 1, it indicates that the compression operation is turned on. There is also a flag bit for indicating Run-length encoding, specifically, when Run length en is 1, indicating that Run-length encoding is turned on. There is also a flag bit Shuffle en for indicating shuffling, specifically, when Shuffle en is 1, it indicates that shuffling is turned on.

And a flag bit Head addr regen for identifying whether the address Head addr of the data header entry is an immediate number or a register number, specifically, when the Head addr regen is 1, the address Head addr representing the data header destination is the register number, that is, the address Head addr representing the data header destination comes from the register, and when the Head addr regen is 0, the address Head addr representing the data header entry is the immediate number.

Specifically, when the Head offset reg is 1, this indicates that the Head offset Head is a register number, that is, the Head offset Head is from the register, and when the Head offset reg is 0, this indicates that the Head offset Head is an immediate number.

And a flag bit Data addr regen for identifying whether the original Data source address Data addr is an immediate number or a register number, specifically, when the Data addr regen is 1, the flag bit indicates that the original Data source address Data addr is the register number, namely, the original Data source address Data addr comes from the register, and when the Data addr regen is 0, the flag bit indicates that the original Data source address Data addr is the immediate number.

Further, a flag bit Block seg num reg en for identifying whether a Block line number Block seg num of the data Block is an immediate number or a register number is provided, and specifically, when the Block seg num reg en is 1, the Block line number Block seg num indicating the data Block is a register number, that is, when the Block line number Block seg num of the data Block is from a register, and when the Block seg num reg en is 0, the Block line number Block seg num indicating the data Block is an immediate number.

And a flag bit Block size reg en for identifying whether the Block single line number Block size of the data Block is an immediate number or a register number, and specifically, when the Block size reg en is 1, the Block single line number Block size indicating the data Block is a register number, that is, when the Block single line number Block size of the data Block comes from a register, and when the Block size reg en is 0, the Block single line number Block size indicating the data Block is an immediate number.

Similarly, there are a flag bit Head stride regen for identifying whether the header line feed distance Head stride is an immediate number or a register number, a flag bit Data stride regen for identifying whether the original Data line feed distance Data stride is an immediate number or a register number, a flag bit Head seg num regen for identifying whether the header line number Head seg num is an immediate number or a register number, and a flag bit Head num regen for identifying whether the single-line header number Head num is an immediate number or a register number. Specifically, when the flag bits are 1, the register number indicates that each instruction field is a register number, and when the flag bits are 0, the immediate number indicates that each instruction field is an immediate number.

In one alternative, the instruction may be a DECOMPRESS instruction, which may be in the instruction format shown in Table 2 below:

TABLE 2

The instruction type Name is used to determine the type of the instruction (the type of the instruction may include a COMP type instruction and other instructions, where the COMP type is 16), that is, the instruction type is used to determine whether the operation instruction is a COMP type instruction. The instruction Type is used for determining the Type of the COMP Type instruction, and the Type of the COMP Type instruction is used for indicating what function is implemented by the instruction, for example, when the instruction Type is 2, the instruction is a DECOMPRESS instruction. The destination address Data addr of the decompressed Data is used to indicate the destination address of the decompressed Data to be written back. The command fields are used for indicating the original address of a target data Head to be read.

Further, the instruction format of the demolist instruction may further include: and the configuration table address Config addr is used for storing the coding value of the data in the compression format.

Further, the instruction format of the demo press instruction may also include flag bits for each instruction field, such as: specifically, when the Data addr reg en is 1, the destination address Data addr representing the decompressed Data is a register number, that is, the destination address Data addr representing the decompressed Data comes from a register, and when the Data addr reg en is 0, the destination address Data addr representing the decompressed Data is an immediate number.

And a flag bit Headdr regen for identifying whether the Head source address Headdr is an immediate number or a register number, specifically, when the Headdr regen is 1, the flag bit Headdr regen indicates that the Head source address Headdr is the register number, that is, the Head source address Headdr comes from the register, and when the Headdr regen is 0, the flag bit Headdr addr regen indicates that the Head source address Headdr addr is an immediate number.

Specifically, when the Head offset regen is 1, the flag bit indicates that the Head address offset Head offset is the register number, that is, the Head address offset Head offset comes from the register, and when the Head offset regen is 0, the flag bit indicates that the Head address offset Head offset regen is the immediate number.

Referring to fig. 3, the present application also provides an apparatus for instruction application, i.e. a data processing apparatus 3000, which may include a configuration unit 100, a data reading/writing unit 200, and a compression/decompression unit 300. The configuration unit 100 is connected to the data reading/writing unit 200, the configuration unit 100 is connected to the direct memory access unit 300, and the compression/decompression unit 300 is connected to the data reading/writing unit 200.

Alternatively, the first configuration unit 101, the second configuration unit 102, and the third configuration unit 103 may be packaged as one configuration unit 100.

The configuration unit 100 obtains a first operand by configuring a first operation, a second operand by configuring a second operation, a third operand by configuring a third operation, a fourth operand by configuring a fourth operation, and a fifth operand by configuring a fifth operation, and sends the first operand, the third operand, the fourth operand, and the fifth operand to the data read/write unit 200.

After receiving the operand sent by the configuration unit 100, the data reading and writing unit 200 reads the original data from the storage device pointed by the first operand according to the first operand, and divides the original data into a pair of data blocks. And writing a data head in the compressed data into a storage device pointed by the third operand according to the third operand, and then writing out a data body according to the corresponding relation between the data head and the data body. According to the fourth operand, the data block of the compressed data is read from the storage device pointed to by the fourth operand and is sent to the compression and decompression unit 300. And writing the decompressed data into the storage device pointed by the fifth operand according to the fifth operand.

The compression and decompression unit 300 receives the second operand sent by the configuration unit 100, and performs data compression on the data block according to the second operand to obtain compressed data. Furthermore, the codec unit 300 may also decompress the data block of the compressed data to obtain decompressed data after receiving the data block of the compressed data.

Optionally, the storage device may include the first storage device 13, and may also include the second storage device 201. The first memory means 13 may be a memory means arranged outside the processor. The second storage means 201 may be a buffer and/or a register arranged inside the processor 1000. The first storage device 13 and the second storage device 201 may also be a non-volatile memory or a volatile memory, and are not limited herein. The data read/write unit 200 may be an I/O circuit.

Alternatively, the compression-decompression unit 300 may be provided in the operation unit 12.

In one embodiment, as shown in fig. 4, a decoding method of a complete instruction is provided, which is described by taking the decoder in fig. 1 as an example, and includes the following steps:

s200, acquiring source data of original data in the COMPRESS instruction, and configuring a first operation of the COMPRESS instruction according to the source data of the original data to obtain a first operand of the first operation.

Wherein the source data of the original data represents an original address of the original data. The first operation is to read the original data according to the first operand, dividing the original data into a plurality of data blocks. The first operand may be an immediate or a register number.

Specifically, the first configuration unit 101 acquires source data of original data in the comp ress, and configures a first operation of the comp ress according to the acquired source data of the original data in the comp ress, to obtain a first operand of the first operation, that is, to acquire an original address of the original data.

S300, obtaining source data of a compression operation in the COMPRESS instruction, and configuring a second operation of the COMPRESS instruction according to the source data of the compression operation to obtain a second operand of the second operation.

Wherein, the source data of the compression operation is represented by the flag bit of the compression mode, that is, when the flag bit of the compression mode is 1, it represents that the compression is started. The second operation is to compress the block of data based on a second operand.

Specifically, the second configuration unit 102 obtains source data of a compression operation in the COMPRESS instruction, and configures a second operation of the COMPRESS instruction according to the obtained source data of the compression operation, so as to obtain a second operand of the second operation.

S400, acquiring destination data of a data head in the COMPRESS instruction, and configuring a third operation of the COMPRESS instruction according to the destination data of the data head to obtain a third operand of the third operation.

The destination data of the data header represents the target address of the data header, i.e. the obtained data header is written to the position corresponding to the target address. And the third operation is used for writing out a data head in the compressed data according to the third operand and then writing out a data body according to the corresponding relation between the data head and the data body. The third operand includes an immediate or register number. The compressed data obtained by the compression operation comprises a plurality of data heads and a plurality of data bodies, wherein the data heads store the initial addresses and the data lengths of the corresponding data bodies, and the data bodies contain the compression coding values of the compressed data.

Specifically, the third configuration unit 103 obtains destination data of a data header in the compare instruction, and configures a third operation of the compare instruction according to the obtained destination data of the data header, so as to obtain a third operand of the third operation.

In the decoding method of the comp ress, a first operand of the first operation is obtained by configuring the first operation, the first operation represents a read operation for reading original data according to the first operand, a second operand of the second operand is obtained by configuring the second operation, the second operation represents a compression operation for compressing the original data according to the second operand, and a third operand of the third operand is obtained by configuring the third operation, and the third operation represents a write-back operation for compressing a data header in the data according to the third operand. The COMPRESS instruction is analyzed to obtain corresponding operation, the analysis of the COMPRESS instruction is achieved, and meanwhile the instruction can obtain compressed data in a specific format.

In one embodiment, with continued reference to fig. 4, the method may further include the steps of:

s100, analyzing the obtained instruction, and determining the instruction to be a COMPRESS instruction according to the instruction type and the instruction type in the instruction.

As shown in table 1 above, the instruction class Name is used to determine a class of the instruction (the class of the instruction may include a COMP-type instruction and other instructions, where the COMP-type is 16), that is, the instruction class is used to determine whether the operation instruction is a COMP-type instruction. The instruction Type is used for determining the Type of the COMP Type instruction, and the Type of the COMP Type instruction is used for indicating what function is implemented by the instruction, for example, when the instruction Type is 1, the instruction is a COMP instructions.

Specifically, the instruction processing unit 111 analyzes the acquired instruction, distinguishes the instruction according to the instruction Type Name and the instruction Type, and when the instruction Type is 1, indicates that the instruction is a complete instruction.

Alternatively, the instruction processing unit 111 may obtain the instruction through the instruction cache unit 110, and then the first configuration unit 101, the second configuration unit 102, and the third configuration unit 103 in the instruction processing unit 111 perform configuration.

In one embodiment, referring to fig. 5, the first operand may include an immediate or a register number, whether the first operand is an immediate is determined, and when the first operand is determined to be an immediate, step S500 is executed, where the first operand is used to read original data from the first storage device.

Wherein the first storage means 13 may be an off-chip storage means.

In particular, when the first operand is an immediate, the first operation is used to read the original data from the corresponding location in the first storage means 13 to which the first operand points.

When the first operand is determined to be the register number, step S600 is executed, and the first operation is used to read the original data from the second storage device according to the first operand.

Wherein the second storage 201 may be an on-chip storage.

In particular, when the first operand is a register number, the first operation is used to read the original data from the corresponding location in the second storage means 201 to which the first operand points.

The method of the embodiment adapts to the requirements on the instruction in different application scenes by reading the original data of the off-chip address and the on-chip address, and enhances the completeness of the instruction application.

In one embodiment, referring to fig. 6, the process of configuring the first operation may include the following steps:

s210, obtaining the original address of the original data in the first operand according to the source address and the line feed distance of the original data in the COMPRESS instruction.

Specifically, the first configuration unit 101 obtains a source address and a line-feed distance of original data in the complete command, and then obtains the original address of the original data in the first operand according to the source address and the line-feed distance of the original data. And obtaining an original address of the original data by obtaining the source address and the line feed distance of the original data, wherein the original address is used for storing the original data.

S220, configuring the first operation of the COMPRESS instruction according to the original address to obtain a first operand of the first operation.

Specifically, after obtaining the original address of the original data, the first configuration unit 101 configures a first operation of the compare instruction according to the original address, and obtains a first operand of the first operation. And configuring the original address for storing the original data according to the storage address of the original data to obtain a first operand, and reading the original data according to the first operand.

S230, configuring the first operation of the COMPRESS instruction according to the number of the lines in the data block and the number of the single lines in the data block in the COMPRESS instruction, and obtaining a first operand of the first operation.

Specifically, after acquiring the number of lines in a block and the number of single lines in the block of a data block in the complete command, the first configuration unit 101 configures according to the number of lines in the block and the number of single lines in the block of the data block, so as to obtain a first operand. The first operand is used to determine the number of rows within a block and the number of single rows within the block of data, and the first operation is used to divide the original data into a plurality of blocks of data according to the number of rows within the block and the number of single rows within the block of data in the first operand.

In this embodiment, the original data in the first operation is configured, so that the position of the original data header that is read is more accurate.

In one embodiment, the first configuration unit 101 may configure the first operation of the complete instruction according to a window parameter in the complete instruction, to obtain a first operand of the first operation. The window parameters may include direction parameters in four directions, for example, the parameters in each direction are set as follows in table 1: the non-integral block Top value Top (upper), the non-integral block Bottom value Bottom (lower), the non-integral block Left value Left (Left), and the non-integral block Right value Right (Right). The original data can be window read according to the direction parameters of the four directions. The first operation is for performing a non-whole block read of the original data according to a first operand.

In one embodiment, referring to fig. 7, the process of configuring the second operation may include the following steps:

s310, configuring a second operation of the COMPRESS instruction according to the source data of the run-length codes in the COMPRESS instruction to obtain a second operand of the second operation.

Specifically, the second configuration unit 102 obtains the run-length encoded source data in the complete instruction, and then obtains a second operand of the second operation according to the run-length encoded source data. The second operation is to select whether to use run-length encoding for compression based on run-length encoded source data in the second operand.

S320, configuring a second operation of the COMPRESS instruction according to the shuffled source data in the COMPRESS instruction to obtain a second operand of the second operation.

Specifically, the second configuration unit 102 acquires shuffle source data in the combine instruction, configures a second operation of the move instruction according to the shuffle source data, and obtains a second operand of the second operation, where the second operand is used to indicate whether to perform data shuffle before a compression operation. The second operation is used to select whether to shuffle the data prior to the compress operation based on the shuffle source data in the second operand.

The method of the embodiment enables the compression of the data block to be more diversified by configuring the compression operation.

In one embodiment, referring to fig. 8, the process of configuring the third operation may include the steps of:

and S410, obtaining a target address of the data head in the third operand according to the target address and the address offset of the data head in the COMPRESS instruction.

Specifically, the third configuration unit 103 obtains a destination address and an address offset of the data header in the complete command, and then obtains a target address of the data header according to the destination address and the address offset of the data header. The target address of the data header is used for indicating the target address to which the data header is to be written back, i.e. the target address of the data header is used for storing the written-back data header.

And S420, configuring a third operation of the COMPRESS instruction according to the target address of the data head to obtain a third operand of the third operation.

Specifically, after obtaining the target address of the data header, the third configuration unit 103 configures the third operation of the compare instruction according to the target address of the data header, to obtain a third operand of the third operation, where the third operand is used to indicate the target address of the data header, that is, the third operand is used to indicate the target address to which the data header is to be written back, that is, the target address of the data header is used to store the written-back data header.

S430, configuring a third operation of the COMPRESS instruction according to the line number, the line feed distance and the number of the single-line data heads in the COMPRESS instruction, and obtaining a third operand of the third operation.

Specifically, after the line number, the line feed distance, and the number of single-line data heads of the data head in the complete command are obtained, the third configuration unit 103 configures according to the line number, the line feed distance, and the number of single-line data heads of the data head, and obtains a third operand. The third operand is used to determine the destination address, the number of rows, and the number of single lines of the header to be written back.

S440, configuring a third operation of the COMPRESS instruction by using the placement mode parameter in the COMPRESS instruction to obtain a third operand of the third operation.

Specifically, the third configuration unit 103 configures the third operation of the complete command according to the placement mode parameter in the complete command, and obtains a third operand of the third operation. The third operand is used to determine the placement mode of the data header to be written back.

S450, according to the initial address and the data length in the data head of the third operand, the target address and the data length of the data body of the third operand are obtained.

Specifically, the third operand includes a target address of a data header and a number of the data header, and the data header and the data body have a certain correspondence, the data header stores a start address and a data length of the corresponding data body, and the third configuration unit 103 obtains the target address and the number of the data body according to the target address and the number of the data header.

And S460, configuring a third operation of the COMPRESS instruction by using the target address and the data length of the data body.

Specifically, the third configuration unit 103 obtains the target addresses and the number of the data volumes, and then configures a third operation of the compare instruction according to the target addresses and the number of the data volumes, where the third operation is used to perform a write-out operation on the data volumes according to the target addresses and the number of the data volumes.

In this embodiment, the number and the number of rows of the data header in the third operation are configured, so that the position of the written data header is more accurate.

Referring to fig. 9, the present application further provides a data processing method, for example, the method applied to the data processing apparatus of fig. 3, which includes the following steps:

s700, a COMPRESS instruction is obtained and analyzed, and a first operand, a second operand and a third operand of the COMPRESS instruction are obtained.

Wherein the first operand may include an immediate or register number and the third operand may include an immediate or register number

Specifically, the configuration unit 100 obtains the complete command, and parses the complete command to obtain a first operand, a second operand, and a third operand of the complete command.

And S800, reading original data from the storage device pointed by the first operand, and dividing the original data into a plurality of data blocks.

The storage device may be the first storage device 13 or the second storage device 201.

Specifically, after the configuration unit 100 obtains the first operand, the first operand is sent to the data reading and writing unit 200, and after the data reading and writing unit 200 receives the first operand, the original data is read from the storage device pointed by the first operand according to the first operand, and the original data is divided into a plurality of data blocks.

And S900, compressing the data block according to the second operand to obtain compressed data.

Specifically, after obtaining the second operand, the configuration unit 100 sends the second operand to the compression and decompression unit 300, and after receiving the second operand, the compression and decompression unit 300 compresses the obtained data block according to the second operand, so as to obtain compressed data.

S1000, writing a data head in the compressed data into a storage device pointed by the third operation data, and writing out a data body according to the corresponding relation between the data head and the data body.

Specifically, after obtaining the third operand, the configuration unit 100 sends the third operand to the data reading and writing unit 200, and after receiving the third operand, the data reading and writing unit 200 writes the data header in the compressed data into the storage device to which the third operation data points according to the third operand, and then writes out the data volume according to the corresponding relationship between the data header and the data volume.

According to the method, the original data are compressed according to the first operand, the second operand and the third operand which are obtained through analysis, the compressed data are obtained, the data head in the compressed data is written out, and then the data body is written out according to the corresponding relation between the data head and the data body, so that the compressed data in a specific format can be obtained, the instruction function is improved, and the functionality of equipment is improved.

In one embodiment, referring to fig. 10, the step S800 may include the following steps:

judging whether the first operand is an immediate number, and executing step S810 when the first operand is an immediate number, and reading original data from the first storage device according to the first operand.

Wherein the first storage device 13 is an off-chip storage device.

Specifically, when the first operand is an immediate, the data reading and writing unit 200 reads the original data from the first storage device 13 according to the first operand and the position pointed to by the first operand.

When the first operand is determined to be the register number, step S820 is executed to read the original data from the second storage device according to the first operand.

The second storage device 201 is an on-chip storage device.

Specifically, when the first operand is a register number, the data reading and writing unit 200 reads the original data from the second storage device 201 according to the first operand and the position pointed by the first operand.

The method of the embodiment adapts to the requirements of the instructions under different application scenes by reading the original data of the off-chip address and the on-chip address, and enhances the completeness of the instruction application.

In one embodiment, the data read/write unit 200 may read the original data from the location pointed by the first operand according to the source address and the line feed distance of the original data in the first operand.

In one embodiment, the data read/write unit 200 divides the read original data into a plurality of data blocks according to the number of rows in a data block and the number of single rows in the data block in the first operand.

In one embodiment, the codec unit 300 sends the data block to the storage device to which the second operand data points according to the run-length encoded source data in the second operand, and then selects whether to use run-length encoding for compression.

In one embodiment, the data reading and writing unit 200 writes the data header in the compressed data into the storage device pointed by the third operand according to the destination address and the address offset of the data header in the third operand, and then correspondingly writes the data body into the storage device pointed by the third operand according to the placement mode parameters of the data header and the data body in the third operand.

The data body and the writing position of the data head are more accurate by configuring the placing mode parameters of the data head and the data body.

Referring to fig. 11, in one embodiment, a method for decoding a decode command is provided, which is illustrated by applying the method to the decoder in fig. 1, and includes the following steps:

s1200, obtaining the number of rows in the data block and the number of single lines in the data block in the demoprep instruction, and configuring a fourth operation of the demoprep instruction according to the number of rows in the data block and the number of single lines in the data block, to obtain a fourth operand of the fourth operation.

And the fourth operation is used for reading the data block of the compressed data according to the fourth operand and sending out the read data block. The data block of the compressed data comprises a plurality of data heads and a plurality of data bodies, the data heads and the data bodies have a certain corresponding relation, the data heads store the initial addresses and the data lengths of the corresponding data bodies, and the data bodies contain compressed coding values of the compressed data. The fourth operand may be an immediate or a register number.

Specifically, the first configuration unit 101 obtains the number of rows in a block and the number of single lines in the block of a data block in the demopress instruction, and configures the fourth operation of the demopress instruction according to the obtained number of rows in the block and the number of single lines in the block of the data block, so as to obtain a fourth operand of the fourth operation.

S1300, acquiring the destination data of the decompressed data in the DECOMPRESS instruction, and configuring the fifth operation of the DECOMPRESS instruction according to the destination data of the decompressed data to obtain the fifth operand of the fifth operation.

The target data of the decompressed data represents the target address of the decompressed data, namely the decompressed data is written back to the position corresponding to the target address. The fifth operation is for writing out the retrieved decompressed data. The fifth operand includes an immediate or register number.

Specifically, the second configuration unit 102 obtains destination data of the decompressed data in the demoprep instruction, and configures a fifth operation of the demoprep instruction according to the destination data of the decompressed data, to obtain a fifth operand of the fifth operation, that is, to obtain a target address of the decompressed data.

In the method for decoding the demoprep instruction, the fourth operand of the fourth operation is obtained by configuring the fourth operation, the fourth operation represents a read operation for compressing a data block of data according to the fourth operand, and the fifth operand of the fifth operation is obtained by configuring the fifth operation, and the fifth operation represents a write-back operation for decompressing data according to the fifth operand. Corresponding operation is obtained by analyzing the DECOMPRESS instruction, so that the DECOMPRESS instruction is analyzed, and decompression of compressed data in a specific format is supported.

In one embodiment, referring to fig. 11, the method may further include the steps of:

s1100, analyzing the obtained command, and determining the command to be a DECOMPRESS command according to the command type and the command type in the command.

As shown in table 2 above, the instruction class Name is used to determine the class of the instruction (the class of the instruction may include a COMP type instruction and other instructions, where the COMP type is 16), that is, the instruction class is used to determine whether the operation instruction is a COMP type instruction. The instruction Type is used for determining the Type of the COMP Type instruction, and the Type of the COMP Type instruction is used for indicating what function is realized by the instruction, for example, when the instruction Type is 2, the instruction is a DECOMPRESS instruction.

Specifically, the instruction processing unit 111 analyzes the acquired instruction, distinguishes the instruction according to the instruction Type Name and the instruction Type, and indicates that the instruction is a demompress instruction when the instruction Type is 2.

Alternatively, the instruction processing unit 111 may obtain the instruction through the instruction cache unit 110, and then the first configuration unit 101 and the second configuration unit 102 in the instruction processing unit 111 perform configuration.

In one embodiment, referring to fig. 12, the fourth operand may include an immediate or a register number, and whether the fourth operand is an immediate is determined, and when the fourth operand is determined to be an immediate, step S1400 is executed, where the fourth operation is used to read a data block of compressed data from the first storage device according to the fourth operand.

Wherein the first storage means 13 may be an off-chip storage means.

In particular, when the fourth operand is an immediate, the fourth operation is to read a block of compressed data from the corresponding location in the first storage means 13 to which the fourth operand points.

When the fourth operand is determined to be the register number, step S1500 is executed, and the fourth operation is used to read the data block of the compressed data from the second storage device according to the fourth operand.

Wherein the second storage 201 may be an on-chip storage.

In particular, when the fourth operand is a register number, the fourth operation is to read a block of compressed data from the corresponding location in the second storage means 201 to which the fourth operand points.

The method of the embodiment adapts to the requirements for the instruction in different application scenes by reading the data blocks of the compressed data from the off-chip address and the on-chip address, and enhances the completeness of the instruction application.

In one embodiment, referring to fig. 13, the process of configuring the fourth operation may include the steps of:

s1210, according to the source address and the address offset of the data head in the DECOMPRESS instruction, the original address of the data head in the fourth operand is obtained.

Specifically, the first configuration unit 101 obtains a source address and an address offset of a data header in the demompress instruction, and then obtains an original address of the data header in the fourth operand according to the source address and the address offset of the data header. And obtaining an original address of the data head by obtaining the source address and the address offset of the data head, wherein the original address is used for storing the data head.

S1220, configure the fourth operation of the decode instruction according to the original address, to obtain a fourth operand of the fourth operation.

Specifically, after obtaining the original address of the data header, the first configuration unit 101 configures a fourth operation of the complete instruction according to the original address, so as to obtain a fourth operand of the fourth operation. And if the original address is used for storing the data head, configuring according to the storage address of the data head to obtain a fourth operand, and reading the data head according to the fourth operand.

And S1230, configuring the fourth operation of the DECOMPRESS instruction according to the line number of the data head in the DECOMPRESS instruction, the line feed distance and the number of the single-line data heads, and obtaining a fourth operand of the fourth operation.

Specifically, after acquiring the number of rows, the row change distance, and the number of single-row data heads of the data head in the demo press instruction, the first configuration unit 101 configures according to the number of rows, the row change distance, and the number of single-row data heads of the data head, and obtains a fourth operand. The fourth operand is used to determine the original address, the number of rows, and the number of single rows of the header to be read.

S1240, according to the start address and the data length in the data head of the fourth operand, the original address and the data length of the data body in the fourth operand are obtained.

Specifically, the fourth operand includes an original address and a data length of a data header, and the data header and the data body have a certain correspondence, the data header stores a start address and a data length of the corresponding data body, and the first configuration unit 101 obtains the original address and the data length of the data body according to the original address and the data length of the data header.

S1250, the fourth operation of the demolist instruction is configured using the original address and the data length of the data body.

Specifically, the first configuration unit 101 obtains an original address and a data length of a data body, and then configures a fourth operation of the demoprep instruction according to the original address and the data length of the data body, where the fourth operation is used to read the data body according to the original address and the data length of the data body.

In this embodiment, the number and the number of rows of the data heads in the fourth operation are configured, so that the position of the read data head is more accurate.

In one embodiment, referring to fig. 14, the process of configuring the fifth operation may include the steps of:

s1310 obtains a destination address of the decompressed data in the fifth operand according to the destination address of the decompressed data in the demoframe instruction.

Specifically, the second configuration unit 102 obtains a destination address of the decompressed data in the demoframe instruction, and then obtains a destination address of the decompressed data according to the destination address of the decompressed data. The target address of the decompressed data is used to indicate the target address to which the decompressed data is to be written back, i.e. the target address of the decompressed data is used to store the decompressed data that is written back.

S1320, according to the target address of the decompressed data, the fifth operation of the DECOMPRESS instruction is configured, and a fifth operand of the fifth operation is obtained.

Specifically, after obtaining the destination address of the decompressed data, the second configuration unit 102 configures according to a fifth operation of the destination address of the decompressed data DECOMPRESS instruction, and obtains a fifth operand of the fifth operation, where the fifth operand is used to indicate the destination address of the decompressed data, that is, the fifth operand is used to indicate the destination address to which the decompressed data is to be written back, that is, the destination address of the decompressed data is used to store the decompressed data that is written back.

The method of the implementation configures the target address of the decompressed data, so that the address of the written-back decompressed data is more accurate.

Referring to fig. 15, the present application further provides a data processing method, for example, the method applied to the data processing apparatus of fig. 3, which includes the following steps:

and S1600, acquiring a DECOMPRESS instruction, and analyzing the DECOMPRESS instruction to obtain a fourth operand and a fifth operand of the DECOMPRESS instruction.

Wherein the fourth operand may include an immediate or register number and the fifth operand may include an immediate or register number

Specifically, the configuration unit 100 obtains the demoprep instruction, and parses the demoprep instruction to obtain a fourth operand and a fifth operand of the demoprep instruction.

S1700, reading the data block of the compressed data from the storage device pointed by the fourth operand, and sending the read data block.

The storage device may be the first storage device 13 or the second storage device 201. The data block of the compressed data comprises a plurality of data heads and a plurality of data bodies, wherein the data heads store the initial addresses and the data lengths of the corresponding data bodies, and the data bodies contain compression coding values of the compressed data.

Specifically, after obtaining the fourth operand, the configuration unit 100 sends the fourth operand to the data reading and writing unit 200, and after receiving the fourth operand, the data reading and writing unit 200 reads the data block of the compressed data from the storage device to which the fourth operand points according to the fourth operand.

S1800, decompressing the read data block of the compressed data to obtain decompressed data.

Specifically, after receiving the read data block of the compressed data, the compression and decompression unit 300 decompresses the read data block of the compressed data to obtain decompressed data.

And S1900, writing the decompressed data into the storage device pointed by the fifth operation data.

Specifically, after obtaining the fifth operand, the configuration unit 100 sends the fifth operand to the data reading and writing unit 200, and after receiving the fifth operand, the data reading and writing unit 200 writes the decompressed data into the storage device to which the fifth operand points according to the fifth operand.

According to the method, the data block of the compressed data is decompressed according to the fourth operand and the fifth operand which are obtained through analysis, the decompression processing of the data in a specific compression format is supported, the instruction function is improved, and the device functionality is improved.

In one embodiment, referring to fig. 16, the step S1700 may include the following steps:

judging whether the fourth operand is an immediate number, and when the fourth operand is an immediate number, executing step S1710, reading a data block of the compressed data from the first storage device according to the fourth operand, and sending the read data block.

The first storage device 13 is an off-chip storage device.

Specifically, when the fourth operand is an immediate, the data reading and writing unit 200 reads the data block of the compressed data according to the position pointed by the fourth operand and sends the read data block in the first storage device 13 according to the fourth operand.

When the fourth operand is determined to be the register number, step S1720 is executed to read the data block of the compressed data from the second storage device according to the fourth operand, and send the read data block.

The second storage device 201 is an on-chip storage device.

Specifically, when the fourth operand is a register number, the data reading and writing unit 200 reads a data block of compressed data according to a position pointed by the fourth operand and sends the read data block in the second storage device 201 according to the fourth operand.

In one embodiment, the data read/write unit 200 may read the data block of the compressed data according to the source address and the address offset of the data header in the fourth operand. The data block of the compressed data comprises a plurality of data heads and a plurality of data bodies.

In one embodiment, the data read/write unit 200 reads the data block of the compressed data according to the number of rows of data heads in the fourth operand, the row feed distance, and the number of data heads in a single row.

The number and position of the data head to be read can be accurately determined according to the source address, address offset, number of lines, number of single lines and the like of the data head.

In one embodiment, the data reading and writing unit 200 writes the obtained decompressed data into the storage device pointed by the fifth operand according to the destination address of the decompressed data in the fifth operand.

The position to be written back by the decompressed data can be accurately determined according to the destination address of the decompressed data.

It should be understood that although the various steps in the flowcharts of fig. 4-16 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. 4-16 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of performance of which is not necessarily sequential, but may be performed in turn or alternating with other steps or at least portions of sub-steps or stages of other steps.

In one embodiment, a computer device is provided that includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program to run on the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a move instruction decoding method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on a shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, performs the steps of:

the method comprises the steps of obtaining source data of original data in a COMPRESS instruction, and configuring a first operation of the COMPRESS instruction according to the source data of the original data to obtain a first operand of the first operation. Specifically, the first configuration unit 101 acquires source data of original data in the complete command, and configures a first operation of the complete command according to the acquired source data of the original data in the complete command, to obtain a first operand of the first operation, that is, to acquire an original address of the original data.

And acquiring source data of a compression operation in the COMPRESS instruction, and configuring a second operation of the COMPRESS instruction according to the source data of the compression operation to obtain a second operand of the second operation. Specifically, the second configuration unit 102 obtains source data of a compression operation in the COMPRESS instruction, and configures a second operation of the COMPRESS instruction according to the obtained source data of the compression operation, so as to obtain a second operand of the second operation.

And acquiring target data of a data head in the COMPRESS instruction, and configuring a third operation of the COMPRESS instruction according to the target data of the data head to obtain a third operand of the third operation. Specifically, the third configuration unit 103 obtains destination data of a data header in the compare instruction, and configures a third operation of the compare instruction according to the obtained destination data of the data header, so as to obtain a third operand of the third operation.

It should be clear that, steps implemented when the computer program in the embodiment of the present application is executed by the processor are consistent with the execution process of each step of the method in the foregoing embodiment, and may specifically refer to the foregoing description, and are not described herein again.

and configuring a fourth operation of the DECOMPRESS instruction according to the number of the line numbers in the data block and the number of the single lines in the data block to obtain a fourth operand of the fourth operation. Specifically, the first configuration unit 101 obtains the number of lines in a data block and the number of single lines in the data block in the demo press instruction, and configures the fourth operation of the demo press instruction according to the obtained number of lines in the data block and the number of single lines in the data block, so as to obtain a fourth operand of the fourth operation.

And acquiring the destination data of the decompressed data in the DECOMPRESS instruction, and configuring the fifth operation of the DECOMPRESS instruction according to the destination data of the decompressed data to obtain a fifth operand of the fifth operation. Specifically, the second configuration unit 102 obtains destination data of the decompressed data in the demoprep instruction, and configures a fifth operation of the demoprep instruction according to the destination data of the decompressed data, to obtain a fifth operand of the fifth operation, that is, to obtain a target address of the decompressed data.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method for decoding a DECOMPRESS command, the method comprising:

acquiring a source address and an address offset of a data head in the DECOMPRESS instruction to obtain an original address of the data head in a fourth operand; configuring a fourth operation of the DECOMPRESS instruction according to the original address to obtain a fourth operand of the fourth operation, where the fourth operation is used to read a data block of compressed data according to a source address and an address offset of a data header in the fourth operand, and send the read data block out, the data block of the compressed data includes multiple data headers and multiple data bodies, the data header stores a start address and a data length of the corresponding data body, the data body includes a compressed encoded value of the compressed data, and the fourth operand includes an immediate number or a register number;

and acquiring a destination address of the decompressed data in the DECOMPRESS instruction, acquiring a destination address of the decompressed data in a fifth operand, and configuring a fifth operation of the DECOMPRESS instruction according to the destination address of the decompressed data to acquire the fifth operand of the fifth operation, wherein the fifth operation is used for writing out the acquired decompressed data according to the fifth operand, and the fifth operand comprises an immediate number or a register number.

2. The method of claim 1, wherein the source address and address offset of the header in the DECOMPRESS instruction are obtained to obtain the original address of the header in the fourth operand; a step of configuring a fourth operation of the demo press instruction according to the original address to obtain a fourth operand of the fourth operation, where the method further includes:

analyzing the obtained instruction, and determining the instruction to be a DECOMPRESS instruction according to the instruction type and the instruction type in the instruction.

3. The method of claim 1, further comprising:

if the fourth operand is an immediate, the fourth operation is used for reading a data block of compressed data from a first storage device according to the fourth operand, wherein the first storage device is an off-chip storage device;

4. The method of claim 1, further comprising:

and configuring a fourth operation of the DECOMPRESS instruction according to the line number, the line feed distance and the number of the single-line data heads of the data head in the DECOMPRESS instruction to obtain a fourth operand of the fourth operation, wherein the fourth operation is used for reading the data block according to the line number, the line feed distance and the number of the single-line data heads of the data head in the fourth operand.

5. The method of claim 1, further comprising:

obtaining an original address and a data length of a data body in the fourth operand according to a start address and a data length in a data head in the fourth operand;

6. A data processing method, comprising:

reading a data block of compressed data from a storage device pointed by the fourth operand, and sending out the read data block, wherein the data block of the compressed data comprises a plurality of data headers and a plurality of data bodies, the data headers store the start addresses and the data lengths of the corresponding data bodies, the data bodies contain compressed encoding values of the compressed data, and the fourth operand comprises an immediate number or a register number; the fourth operand represents an original storage address of a data block when the data block of the compressed data is read;

writing the decompressed data to a storage device to which the fifth operation data points, wherein the fifth operand comprises an immediate or register number,

the obtaining a DECOMPRESS instruction and analyzing the DECOMPRESS instruction to obtain a fourth operand and a fifth operand of the DECOMPRESS instruction includes:

acquiring a source address and an address offset of a data head in the DECOMPRESS instruction to obtain an original address of the data head in the fourth operand; configuring a fourth operation of the DECOMPRESS instruction according to the original address to obtain a fourth operand of the fourth operation;

and acquiring a destination address of the decompressed data in the DECOMPRESS instruction, acquiring a destination address of the decompressed data in the fifth operand, and configuring a fifth operation of the DECOMPRESS instruction according to the destination address of the decompressed data to acquire a fifth operand of the fifth operation.

7. The method of claim 6, further comprising:

if the fourth operand is an immediate, reading a data block of the compressed data from a first storage device according to the fourth operand, and sending the read data block out, wherein the first storage device is an off-chip storage device;

8. The method of claim 6, wherein the steps of reading a block of compressed data from a storage device pointed to by the fourth operand and sending the read block of data further comprises:

and reading the data block of the compressed data according to the line number, the line feed distance and the number of the data heads in a single line in the fourth operand.

9. A decoder, characterized in that the decoder comprises: the device comprises a first configuration unit and a second configuration unit, wherein the first configuration unit is connected with the second configuration unit;

the first configuration unit is used for acquiring a source address and an address offset of a data head in a DECOMPRESS instruction to obtain an original address of the data head in a fourth operand; configuring a fourth operation of the DECOMPRESS instruction according to the original address to obtain a fourth operand of the fourth operation, where the fourth operation is used to read a data block of compressed data according to a source address and an address offset of a data header in the fourth operand, and send the read data block, the data block of the compressed data includes multiple data headers and multiple data bodies, the data header stores a start address and a data length of the corresponding data body, the data body includes a compressed encoded value of the compressed data, and the fourth operand includes an immediate number or a register number;

the second configuration unit is configured to obtain a destination address of decompressed data in the DECOMPRESS instruction, obtain a destination address of the decompressed data in a fifth operand, and configure a fifth operation of the DECOMPRESS instruction according to the destination address of the decompressed data, so as to obtain the fifth operand of the fifth operation, where the fifth operation is used to write out the obtained decompressed data according to the fifth operand, and the fifth operand includes an immediate number or a register number.

10. The data processing device is characterized by comprising a configuration unit, a data reading and writing unit and a compression and decompression unit, wherein the configuration unit is connected with the compression and decompression unit, the configuration unit is connected with the data reading and writing unit, and the compression and decompression unit is connected with the data reading and writing unit, wherein the configuration unit comprises a first configuration unit and a second configuration unit; the configuration unit obtains a fourth operand and a fifth operand by configuring a fourth operation, and sends the fourth operand and the fifth operand to the data read-write unit,

the first configuration unit is configured to obtain a source address and an address offset of a data header in a demoprep instruction, and obtain an original address of the data header in the fourth operand; configuring a fourth operation of the DECOMPRESS instruction according to the original address to obtain a fourth operand of the fourth operation;

the second configuration unit is configured to obtain a destination address of decompressed data in the demo instruction, obtain a destination address of the decompressed data in the fifth operand, and configure a fifth operation of the demo instruction according to the destination address of the decompressed data, so as to obtain a fifth operand of the fifth operation;

the data reading and writing unit receives a fourth operand and a fifth operand sent by the configuration unit, reads a data block of compressed data from a storage device pointed by the fourth operand according to the fourth operand, and sends the data block of the compressed data to the compression and decompression unit; the data block of the compressed data comprises a plurality of data heads and a plurality of data bodies, the data heads store the start addresses and the data lengths of the corresponding data bodies, the data bodies contain compressed encoding values of the compressed data, and the fourth operand comprises an immediate number or a register number; the fourth operand represents the original storage address of the data block when the data block of the compressed data is read;