GB2284492A - Data processor with instruction decompression unit - Google Patents

Data processor with instruction decompression unit Download PDF

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Publication number
GB2284492A
GB2284492A GB9325002A GB9325002A GB2284492A GB 2284492 A GB2284492 A GB 2284492A GB 9325002 A GB9325002 A GB 9325002A GB 9325002 A GB9325002 A GB 9325002A GB 2284492 A GB2284492 A GB 2284492A
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United Kingdom
Prior art keywords
instruction
unit
compressed
decompression
computer control
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Granted
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GB9325002A
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GB2284492B (en
GB9325002D0 (en
Inventor
Graeme Roy Smith
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Graeme Roy Smith
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Application filed by Graeme Roy Smith filed Critical Graeme Roy Smith
Priority to GB9325002A priority Critical patent/GB2284492B/en
Publication of GB9325002D0 publication Critical patent/GB9325002D0/en
Publication of GB2284492A publication Critical patent/GB2284492A/en
Application granted granted Critical
Publication of GB2284492B publication Critical patent/GB2284492B/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • G06F9/30178Runtime instruction translation, e.g. macros of compressed or encrypted instructions

Abstract

A computer control unit used for instruction sequencing in microprocessors, microcontrollers and digital signal processors has or is used with an instruction decompression unit 5. The unit 5 decompresses a previously compressed instruction block and provides sequential instructions to an instruction decode unit 7 at the correct time. Decoded instructions are passed in turn to instruction execution unit 8. A multiplexer 6 allows the use of non-compressed instructions, by bypassing unit 5. Method and apparatus are provided for source code compilation, de-bug, code simulation and code compression for use with a hardware instruction decompression unit 5. A compressed program is loaded in to the system main memory. Required and potentially required instruction blocks are loaded in to an instruction cache 3 by the computer control unit at run time. Program compression allows for reduced memory requirements and greater data and instruction through-put, by reducing main memory accesses. <IMAGE>

Description

IMPROVEMENTS TO COMPUTER CONTROL UNITS This invention relates to a computer control unit and source code compiler.

There are several forms of VLSI (Very Large Scale Integration) silicon computer devices available today, namely CISC (Complex Instruction Set Computers) and RISC (Reduced Instruction Set Computers) microprocessors, microcontrollers, and digital signal processors or DSP's. These integrated circuit devices are used to execute various instructions which manipulate binary data, arithmetically and logically in an arithmetic logic unit (ALU).

Each manufacturers computing device has its own dedicated instruction set. To perform any useful function, individual instructions are concatenated in a structured and coherent way to form a program. This program is stored in main memory. To execute a program, the computer loads these instructions one at a time into its instruction register, either directly or via an instruction cache. The instructions are then decoded and executed accordingly. The instruction cache allows groups of sequential instructions to be stored locally so the instruction execution unit can access individual instructions quickly without having to perform time consuming external memory read operations. This mechanism therefore increases system performance by reducing main memory accesses and allows instructions to be executed at a faster rate.

Many programs are thousands of instructions long and require large memory arrays to store them. These requirements can range from several kilo-bytes to many mega-bytes of memory. The instruction caching requirements also become more complex and involve sophisticated cache hit, cache miss and cache/main memory consistency control mechanisms. This includes cache write-through, write-back and snoop mechanisms. The instruction cache stores groups or lines of instructions that are regularly used or have a high chance of being required by the instruction execution unit. By making more of the program software directly available to the computer control unit and reducing main memory accesses, through the use of software compression algorithms and hardware decompression techniques, program execution rates can be increased and the size of the memory required to store the programs can be reduced.

With today's high gate densities, it is possible to fabricate three to four million transistors on a single silicon die. These densities allow for increased device functionality, system performance, data and instruction through-put and can be used to integrate hardware instruction decompression units either on the same silicon die or as a separate co-processor.

According to the present invention there is a computer control unit comprising a bus controller, an instruction fetch control unit, an instruction cache to store likely required groups of instructions, an instruction decompression unit which decompresses a block of compressed data from the instruction cache, an instruction decode unit together with a multiplexer to select the instruction source, an instruction execution unit, an interrupt control unit and an compressed interrupt routine memory which stores compressed interrupt service routines.

Apparatus and method for optimizing the source program into compressed target code are also provided. A compiler will first be used to check the source code (program) for correctness. Error free code will then be compressed by the compiler before being loaded into main memory for execution by the host processor. The compression algorithm can be a lossless compression technique or compression algorithm that allows some loss. In the latter case, the instruction decompression unit can regenerate the instruction codes from the 'lossy' compression block due to code redundancy, in a similar fashion to that performed by error correcting codes.

Due to program compression the program memory requirements are reduced because the program can be stored in a significantly smaller memory. As blocks of the program are compressed, more sections of the program can be loaded in to the computer control unit's cache memory. This increases the chance of a cache hit and hence processor performance. At the correct time, appropriate compressed instruction blocks are loaded in to the instruction decompression unit. The instruction decompression unit implements a decompression algorithm which decompresses the compressed instruction block. Sequential instructions are then generated at the output of the instruction decompression unit which are passed to the instruction decoder.

Compressed interrupt routines are stored in the local compressed interrupt routine memory. When an interrupt occurs instruction execution is halted at an appropriate time and the corresponding compressed interrupt routine loaded in to the instruction decompression unit for execution. Upon completion of the interrupt routine the computer control unit returns to normal program execution, unless there is another interrupt of less priority waiting to be serviced. Program flow integrity and decompression parameter maintenance is achieved via a stack associated with the instruction decompression unit which stores and retrieves parameters used by the instruction decompression unit as necessary.

A specific embodiment of the invention will now be described by the way of example with reference to the accompanying drawings in which: Drawing 1/2 figure 1 shows a block diagram of the computer control unit implementing an instruction decompression unit; Drawing 2/2 figure 1 illustrates the program compilation process and target program compression by use of a flow diagram.

Referring to drawing figure 1 the computer control unit comprises a bus controller 1 which is used to gain access of the local bus, a memory address register to hold the address of the memory location to be accessed and a bi-directional data bus on which data is read from or written to main memory or external cache memory. The appropriate control signals are also provided to access peripheral functions.

As a program is executed the instruction fetch control unit 2 loads blocks of program data into the instruction cache 3. This program data can be compressed data or uncompressed data. The mode of operation is dictated by a mode bit in a control register 10, an VO pin 11 of the device or the output of the instruction decode unit 7.

This allows the computer control unit to run either uncompressed programs in the conventional sense, a compressed programs 23 which have been previously compressed by an appropriate compression algorithm 21, 22, or a program which is a mixture of both compressed and non-compressed code. If the program data is not compressed then the instruction decompression unit 5 is bypassed and instructions from the instruction cache memory 3 are input to the instruction decode unit 7 via the instruction source multiplexer 6. The instructions are decoded and transferred to the instruction execution unit 8 where appropriate actions are taken.

In program compression mode, the source program must first have been compiled, checked and edited for correctness and then compressed as outlined in the flow diagram shown in figure 2. Target program code generated by the code generation function 20 of the compiler is passed to the code partitioning function 21 which divides the program into manageable sections of code. This partitioning phase is dependent on the compression algorithm implemented by the code compression 22 section of the compiler 14, 15, 16, 17, 18, 19, 20, the code size and the occurrence of Branch/Call/Goto or Jump type instructions. The decision to perform a branch in the instruction flow is taken by the instruction execution unit 8. If the instruction flow of the program dictates that a branch occurs to an area of code not contained by the current instruction block in the instruction decompression unit 5, then the appropriate instruction block will have to be fetched from the instruction cache 3 or main memory and loaded in to the instruction decompression unit 5. A successful branch to an area of code within the current compressed instruction block, contained in the instruction decompression unit 5, will cause the instruction decompression unit 5 to be initialised with parameters that will allow the instruction decompression unit 5 to generate instructions and permit a continuation in the program flow. The location of code pointed to by a branch type instruction is identified and marked by the code partitioning function 21. Code implemented at these potential branch destinations is coded in such a way by the code compression function 22 that the instruction decompression unit 5 is able to initialise the instruction decompression unit 5 and allow the continuation of program flow.

Compressed instruction blocks 23 are fetched from main memory by the instruction fetch control unit 2 via the bus controller 1 and stored in the instruction cache 3. If the required instruction block is stored in the instruction cache 3 then this block of data is pre-loaded in to instruction decompression unit 5. The instruction block can be prefetched and initialised in the instruction decompression unit 5 before the instructions are required to be decoded. This is due to the multi-stage pipelining provided in the instruction execution unit 8. If the required instruction block is not available in the instruction cache 3, that is, there is a cache miss, then the instruction block is fetched directly from main memory by the instruction fetch unit 2 and loaded into both the instruction cache 3 and the instruction decompression unit 5.

When activated by the decompression mode control bit 10, the I/O pin 11 or the output from the instruction decode unit 7, the instruction decompression unit 5 will decompress the loaded instruction data block and generate sequential instruction opcodes. These op-codes are passed to the instruction decode unit 7 via the instruction source multiplexer 6. By being able to select between the output of the instruction decompression unit 5 and the instruction cache 3, the computer control unit can execute instructions that are compressed or non-compressed. This scope allows for mixed mode programs 23 where a program 23 is constructed from both compressed instruction blocks and non-compressed instruction blocks. The output from the instruction decode unit 7 is transferred to the instruction execution unit 8 at the appropriate time. Output control fields from the instruction execution unit 8 are used to control peripheral logic which performs the desired function.

Compressed interrupt routines are stored in the local compressed interrupt routine memory 4. When an interrupt occurs instruction execution is halted at an appropriate time and the corresponding compressed interrupt routine loaded in to the instruction decompression unit 5 for execution. Upon completion of the interrupt routine the computer control unit returns to normal program execution, unless there is another interrupt of less priority waiting to be serviced. Program flow integrity and decompression parameter maintenance is achieved via a decompression stack 12 associated with the instruction decompression unit S which stores and retrieves parameters used by the instruction decompression unit S as necessary.

Claims (3)

1 A computer control unit comprising an instruction decompression unit for decompressing program instructions previously compressed on a compiler suitable for compressing the program source code in to compressed instruction blocks, the instruction decompression unit implements a decompression algorithm, this algorithm performs the inverse function of either a lossless compression algorithm or a compression algorithm that allows limited code loss, the original code being regenerated by the instruction decompression unit due to redundancy in the instruction codes used by the computer control unit, means for fetching the required compressed instruction blocks from main memory or cache memory to an instruction cache by the computer control unit, a means for transferring the compressed instruction blocks from the instruction cache to the instruction decompression unit, so a sequence of individual instructions can be generated from the compressed code for input in to the instruction decode unit via an instruction source multiplexer which can select between decompressed instructions from the instruction decompression unit or non-compressed instructions from the instruction cache, thus allowing the computer control unit to run either compressed programs, non-compressed programs or a program that contains both compressed and non-compressed instructions, the control of the instruction source multiplexer being determined by an input pin to the computer control unit, a code pattern written to a mode register or the output from the instruction execution unit, the decompressed instructions being transferred to the instruction decode unit at the correct time, before being passed to the instruction execution unit which performs the intended function, associated with the instruction decompression unit is the decompression stack for storing intermediate decompression parameters if interrupts occur and ensuring instruction decompression unit parameter maintenance and integrity, these parameters being restored into the instruction decompression unit in reverse order to enable continuation of program flow after an interrupt has been serviced, unless another lower priority interrupt is pending.
2 An instruction decompression unit which is separate to the main computer control unit and is employed as a computer control unit co-processor for the sole purpose of performing instruction decompression and transferring the individual decompressed instructions to the instruction decode unit in the computer control unit.
3 A computer control unit substantially as described herein with reference to Figures 1-2 of the accompanying drawing.
GB9325002A 1993-12-06 1993-12-06 Improvements to computer control units Expired - Fee Related GB2284492B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9325002A GB2284492B (en) 1993-12-06 1993-12-06 Improvements to computer control units

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Application Number Priority Date Filing Date Title
GB9325002A GB2284492B (en) 1993-12-06 1993-12-06 Improvements to computer control units

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GB9325002D0 GB9325002D0 (en) 1994-01-26
GB2284492A true GB2284492A (en) 1995-06-07
GB2284492B GB2284492B (en) 1998-05-13

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0811915A1 (en) * 1996-06-05 1997-12-10 Sun Microsystems, Inc. Computer system and method for executing threads of execution with reduced run-time memory space requirements
EP0811910A2 (en) * 1996-06-05 1997-12-10 Sun Microsystems, Inc. Computer system and method for executing architecture specific code with reduced run-time memory space requirements
EP0813144A2 (en) * 1994-05-03 1997-12-17 Advanced Risc Machines Limited Data processing system and method utilising multiple instruction sets
WO1997048041A1 (en) * 1996-06-10 1997-12-18 Lsi Logic Corporation An apparatus and method for detecting and decompressing instructions from a variable-length compressed instruction set
GB2319366A (en) * 1996-10-21 1998-05-20 Ibm Microcode compression
GB2319865A (en) * 1996-10-28 1998-06-03 Ibm Managing partially compressed ROM image code
WO1998053408A1 (en) * 1997-05-23 1998-11-26 Aspex Microsystems Ltd. Processor controller for accelerating instruction issuing rate
EP0811911A3 (en) * 1996-06-05 1999-03-10 Sun Microsystems, Inc. Computer system and method for executing network mobile code with reduced run-time memory space requirements
US5905893A (en) * 1996-06-10 1999-05-18 Lsi Logic Corporation Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set
GB2349252A (en) * 1996-06-10 2000-10-25 Lsi Logic Corp An apparatus and method for detecting and decompressing instructions from a variable length compressed instruction set
GB2354354A (en) * 1996-06-10 2001-03-21 Lsi Logic Corp Detecting and decompressing instructions from a variable-length compressed instruction set
GB2362733A (en) * 2000-05-25 2001-11-28 Siroyan Ltd A processor for executing compressed instructions and method of compressing instructions
US7707389B2 (en) 2003-10-31 2010-04-27 Mips Technologies, Inc. Multi-ISA instruction fetch unit for a processor, and applications thereof
USRE43248E1 (en) 1994-06-10 2012-03-13 Arm Limited Interoperability with multiple instruction sets

Citations (2)

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Publication number Priority date Publication date Assignee Title
GB1529538A (en) * 1976-06-30 1978-10-25 Ibm Data expansion apparatus
US5179680A (en) * 1987-04-20 1993-01-12 Digital Equipment Corporation Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
GB1529538A (en) * 1976-06-30 1978-10-25 Ibm Data expansion apparatus
US5179680A (en) * 1987-04-20 1993-01-12 Digital Equipment Corporation Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0813144A2 (en) * 1994-05-03 1997-12-17 Advanced Risc Machines Limited Data processing system and method utilising multiple instruction sets
EP0813144A3 (en) * 1994-05-03 1998-01-14 Advanced Risc Machines Limited Data processing system and method utilising multiple instruction sets
USRE43248E1 (en) 1994-06-10 2012-03-13 Arm Limited Interoperability with multiple instruction sets
EP0811910A3 (en) * 1996-06-05 1999-03-10 Sun Microsystems, Inc. Computer system and method for executing architecture specific code with reduced run-time memory space requirements
EP0811910A2 (en) * 1996-06-05 1997-12-10 Sun Microsystems, Inc. Computer system and method for executing architecture specific code with reduced run-time memory space requirements
CN1096636C (en) * 1996-06-05 2002-12-18 太阳微系统有限公司 Computer system and method for executing threads of execution with reduced run-time memory space reqirements
EP0811911A3 (en) * 1996-06-05 1999-03-10 Sun Microsystems, Inc. Computer system and method for executing network mobile code with reduced run-time memory space requirements
EP0811915A1 (en) * 1996-06-05 1997-12-10 Sun Microsystems, Inc. Computer system and method for executing threads of execution with reduced run-time memory space requirements
GB2354354A (en) * 1996-06-10 2001-03-21 Lsi Logic Corp Detecting and decompressing instructions from a variable-length compressed instruction set
WO1997048041A1 (en) * 1996-06-10 1997-12-18 Lsi Logic Corporation An apparatus and method for detecting and decompressing instructions from a variable-length compressed instruction set
GB2329495A (en) * 1996-06-10 1999-03-24 Lsi Logic Corp An apparatus and method for detecting and decompressing instructions from a variable-length compressed instruction set
US5905893A (en) * 1996-06-10 1999-05-18 Lsi Logic Corporation Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set
GB2329495B (en) * 1996-06-10 2000-09-20 Lsi Logic Corp An apparatus and method for detecting and decompressing instructions from a variable-length compressed instruction set
GB2354354B (en) * 1996-06-10 2001-05-02 Lsi Logic Corp An apparatus and method for detecting and decompressing instructions form a variable-length compressed instruction set
GB2349252B (en) * 1996-06-10 2001-02-14 Lsi Logic Corp An apparatus and method for detecting and decompressing instructions from a variable-length compressed instruction set
GB2349252A (en) * 1996-06-10 2000-10-25 Lsi Logic Corp An apparatus and method for detecting and decompressing instructions from a variable length compressed instruction set
GB2319366B (en) * 1996-10-21 2001-04-11 Ibm Microcode compression
GB2319366A (en) * 1996-10-21 1998-05-20 Ibm Microcode compression
GB2319865B (en) * 1996-10-28 2001-06-06 Ibm Managing compressed ROM image code
GB2319865A (en) * 1996-10-28 1998-06-03 Ibm Managing partially compressed ROM image code
WO1998053408A1 (en) * 1997-05-23 1998-11-26 Aspex Microsystems Ltd. Processor controller for accelerating instruction issuing rate
US6625722B1 (en) 1997-05-23 2003-09-23 Aspex Technology Limited Processor controller for accelerating instruction issuing rate
GB2362733A (en) * 2000-05-25 2001-11-28 Siroyan Ltd A processor for executing compressed instructions and method of compressing instructions
US7124279B2 (en) 2000-05-25 2006-10-17 Pts Corporation Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions
US7343471B2 (en) 2000-05-25 2008-03-11 Pts Corporation Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions
GB2362733B (en) * 2000-05-25 2002-02-27 Siroyan Ltd Processors having compressed instructions.
US7707389B2 (en) 2003-10-31 2010-04-27 Mips Technologies, Inc. Multi-ISA instruction fetch unit for a processor, and applications thereof

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GB2284492B (en) 1998-05-13
GB9325002D0 (en) 1994-01-26

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 19981206