WO1997045957A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- WO1997045957A1 WO1997045957A1 PCT/JP1996/001425 JP9601425W WO9745957A1 WO 1997045957 A1 WO1997045957 A1 WO 1997045957A1 JP 9601425 W JP9601425 W JP 9601425W WO 9745957 A1 WO9745957 A1 WO 9745957A1
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- WIPO (PCT)
- Prior art keywords
- mosfet
- gate
- vertical
- voltage
- semiconductor device
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/12—Modifications for increasing the maximum permissible switched current
- H03K17/122—Modifications for increasing the maximum permissible switched current in field-effect transistor switches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Definitions
- the present invention relates to a semiconductor device and, more particularly, to a technique effective for use in a vertical power MOS FET. Background art
- An object of the present invention is to provide a semiconductor device including a power MOSFET having a new function capable of switching a current supply capability according to the output current.
- the present invention provides a plurality of output M ⁇ SFETs having a common drain and source on one semiconductor substrate or one mounting substrate, and a gate inserted between the gate of the output MOSFET and the input terminal.
- a control circuit including an M 0 SFET for disconnection is formed, and the MOSFET for gate disconnection is turned on in response to an increase in output current by the above control circuit, so that an input signal supplied from an input terminal is provided. Increases the number of output MOSFETs transmitted.
- FIG. 1 is a block diagram showing an embodiment of the power MOSFET according to the present invention
- FIG. 2 is an equivalent circuit diagram of the power MOSFET shown in FIG. 1
- FIG. FIG. 4 is a schematic cross-sectional view of the element structure of the power MOSFET shown in FIG. 1
- FIG. 4 is a configuration diagram for explaining the parasitic capacitance of the power MOSFET
- FIG. 6 is an equivalent circuit diagram for explaining the parasitic capacitance of the SFET.
- FIG. 6 is a configuration diagram showing another embodiment of the power M ⁇ SFET according to the present invention.
- FIG. FIG. 8 is an essential circuit equivalent circuit diagram showing another embodiment of the power MOSFET according to the present invention.
- FIG. 8 is an essential circuit equivalent circuit diagram showing another embodiment of the power MOSFET according to the present invention.
- FIG. 8 is an essential circuit equivalent circuit diagram showing another embodiment of the power MOSFET according to the present invention.
- FIG. 10 is an equivalent circuit diagram for explaining another embodiment of the unit power M ⁇ SFET according to the present invention.
- FIG. 9 is a block diagram showing an embodiment of a power MOSFET configured using the power MOSFET of FIG. 9;
- FIG. 11 is an equivalent circuit showing still another embodiment of the power MOSFET according to the present invention;
- FIG. 12 shows a power MOSFET according to the present invention.
- FIG. 2 is a block diagram showing an embodiment of a switching power supply. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram of one embodiment of a power MOSFET according to the present invention.
- Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique.
- Each of the circuit blocks is drawn substantially in accordance with the actual geometric arrangement on the semiconductor substrate.
- the power MOSFET of this embodiment is roughly composed of three vertical power MOSFETs 1 and a control circuit 7 therefor.
- the control circuit 7 includes a gate disconnection circuit 2, a current detection circuit 3, and a wiring 8 connecting these.
- the source of the vertical power MOSFET 1 is commonly connected to the source pad 5, and the drain is shared by the drain electrode 6 on the back surface.
- the gate pad 4 as an input terminal is connected to the gate of the vertical power MOSFET 1 of 3 above via the gate cutting circuit 2.
- the current detection circuit 3 uses a vertical MOSFET in the form of a current mirror of the vertical power MOSFET, as described later, so that the gate is connected to the gate pad 4 and the drain is the semiconductor substrate itself. It is common and is connected to the back surface drain electrode.
- FIG. 2 shows an equivalent circuit diagram of the power MOSFET shown in FIG.
- the drains of the three vertical power MOSFETs 1 and the drains of the vertical MOSFETs 14 constituting the current detection circuit 3 are commonly connected to a drain electrode 6.
- the sources of the three vertical power MOSFETs 1 are shared by the source pad 5.
- the current detection circuit 3 includes a vertical MOSFET 14 and a resistance circuit provided between a source of the MOSFET 14 and the source pad 5.
- the resistance circuit is composed of three voltage-dividing resistance circuits corresponding to the above-mentioned three vertical type MOSFETs. Although there is no particular limitation on each of the resistor circuits, each of the combined resistors has the same resistance value, and the source and drain currents of the vertical MOSFET 14 are divided into three equal parts.
- the current flowing through the vertical MOSFET 14 is divided into the respective voltage-dividing resistor circuits and flows equally, and a predetermined first current is obtained by a resistance ratio of the resistors 12 and 13 as shown in the example. Is formed.
- the other divided resistor circuits also have different resistance ratios and form different second and third divided voltages.
- the gate cutting circuit 2 is composed of a lateral P-channel MOSFET 10 and a lateral N-channel MOSFET 11 as shown as an example.
- the P-channel MOSFET 10 is provided between the gate pad 4 as an input terminal and the gate of the vertical power MOSFET.
- the N-channel MOSFET 11 is provided between the gate of the P-channel MOSFET 10 and the source pad 5.
- the first divided voltage divided by the resistors 12 and 13 is supplied to the gate of the N-channel MOSFET 11.
- Gate disconnection circuits 2 'and 2 "corresponding to other vertical power MOSFETs are also composed of a combination of horizontal P-channel MOSFETs and horizontal N-channel MOSFETs as described above.
- the gate of the MOSFET is supplied with the second and third divided voltages formed by the above-mentioned voltage dividing resistor circuit.
- FIG. 3 is a cross-sectional view of a main element structure of a semiconductor device according to the present invention.
- the above-mentioned one vertical power MOSFET 1, two horizontal MOSFETs composing the gate disconnection circuit 2 and the current detection circuit The vertical MOSFET and the resistor 21 constituting 3 are shown.
- an epitaxial layer 25 made of N— is formed on a semiconductor substrate 26 made of N +, and each semiconductor layer for constituting each of the following elements is formed on the epitaxial layer 24. It is formed.
- the epitaxy layer 25 constitutes a drain region together with the substrate layer 26, as shown by way of example, a part of the source, the drain and the gate as a representative.
- the thin film electrode 27 is used as the drain terminal 6.
- the P + diffusion layer formed on the surface of the epitaxial layer 25 is a channel region, and the N + diffusion layer formed on the P + diffusion layer is a source region.
- the P + diffusion layer as the channel and the N + diffusion layer as the source are commonly connected by an electrode of aluminum or the like to serve as a source terminal 5.
- the gate electrode is made of polysilicon (Poly-Si) 20 and is located on the channel region of the P + diffusion layer.
- the thin gate insulating film is used to form the N + diffusion layer as a source and a drain. It is formed so as to straddle the layer 25.
- One end of the gate electrode 20 is extended to the gate cutting circuit 2 and is also used as a part of a wiring between the gate electrode 20 and the gate cutting circuit 2.
- the gate cutting circuit 2 includes a P-type insulating separation layer 23 formed on the above-mentioned epitaxial layer 25, and an N-cell (WELL) region 24 for forming a lateral P-channel MOSFET. Is formed. In the remaining portion of the epitaxial layer 25, a P-type well region 24 for forming a lateral N-channel MOSFET is formed. In the lateral P-channel MOSFET, a P + type source and drain are formed in the metal layer 24, and a gate electrode is formed so as to straddle the source-drain. Although not particularly limited, the source and drain connected to the vertical power MOSFET side for higher breakdown voltage, etc. In the W region, a P-type diffusion layer is formed, and the gate electrode is formed such that the P- layer becomes a substantial source and drain region.
- the gate electrode of the vertical power MOSFET is connected to the source and drain of the horizontal P-channel MOSFET by a wiring layer such as aluminum.
- N + layer is formed adjacent to the other P + layer constituting the source and drain to obtain a good ohmic contact with the N ⁇ type cell region 24, and is formed by a wiring means such as aluminum. Commonly connected and connected to gate terminal 1.
- the lateral N-channel MOSFET described above has N +
- a 10-type source and drain are formed, and a gate electrode is formed so as to straddle the source-drain.
- a gate electrode is formed so as to straddle the source-drain.
- N-type diffusion layers are formed in the source and drain regions connected to the gate of the lateral P-channel MOSFET to increase the breakdown voltage and the like.
- the gate electrode is formed so as to be the source and drain regions.
- a P + layer is formed adjacent to the N-type MOSFET to obtain good uniform contact with the P-type transistor region 24. And is connected to the source terminal 5 by the wiring means such as.
- the vertical MO S F E T constituting the current detection circuit 3 is
- the current of 2500 is set to flow through the vertical MOSFET for current detection. Since the gate of the vertical MOSFET is connected to the gate terminal 1 and the drain is shared by the substrate layer 26, the vertical MOSFET 1 is in a current mirror form.
- the source of the vertical MOSFET for current detection is connected to one end of a polysilicon resistor 21 by wiring means such as aluminum, and the other end of the polysilicon resistor 21 is connected to the source terminal 5.
- Wiring for obtaining a divided voltage is provided from the middle part, and is connected to the gate of the lateral N-channel MOSFET. Thereby, a semiconductor device as shown in the equivalent circuit of FIG. 2 can be obtained.
- FIG. 4 is a configuration diagram for explaining the parasitic capacitance in the vertical power MOSFET as described above.
- the parasitic capacitances of the gate and source capacitance CGS, gate and drain capacitance CGD, and the drain and source capacitance CDS are as shown in the cross-sectional view of FIG. Become.
- Gate-source capacitance CGS is the capacitance between the source electrode 5 made of aluminum or the like and the gate electrode made of a polysilicon layer.
- the drain-source capacitance CGD is a parasitic capacitance having a gate insulating film formed under the gate electrode and a depletion layer formed in the channel region as a dielectric.
- Gate-drain capacitance CDS is a parasitic capacitance that uses the depletion layer between the source and drain regions as a dielectric.
- a gate disconnection circuit is provided between the gate of each vertical power MOSFET and the input terminal, and the P-channel M 0 SFET constituting such a gate disconnection circuit is turned off.
- the gate terminal 4 which is a human-powered terminal and the gate of the vertical power MOSFET 1
- Parasitic capacitance Coss is inserted in series. This parasitic capacitance Coss is much smaller than the input capacitance CGS + CGD of the power MOSFET, and the input capacitance CGS + CGD can be made invisible from the input terminal 4.
- the current is supplied from the vertical MOS FET 14 for current detection.
- this current flows into the resistor circuit and the divided voltage generated by the resistors 12 and 13 reaches the threshold voltage of the lateral N-channel MOSFET 11, the MOSFET 11 is turned on, A reference voltage (low level) corresponding to source pad 5 is supplied to the gate of horizontal P-channel MOSFET 10.
- the horizontal P-channel MOSFET 10 is turned on, and the input signal supplied from the gate pad 4 as the input terminal is transmitted to the vertical power MOSFET gate, and the vertical power MOSFET Supplies the output current.
- the output current is supplied through the vertical power MOSFET, and a detection current corresponding to the size ratio between the vertical power MOSFET 1 and the vertical MOS FET 14 for current detection flows.
- the lateral MOS FET 11 is turned on by the divided voltage generated in the resistors 12 and 13 by the current, and the on state of the lateral MOSFET 10 is maintained.
- the number of vertical power MOSFETs connected in parallel automatically increases in response to the required output current. This means that the parasitic capacitance of the vertical power MOSFET changes in accordance with the output current, and the charge and discharge current consumed for the switch control changes in accordance with the output current, minimizing the loss. Can be suppressed.
- FIG. 12 is a block diagram showing one embodiment of a switching power supply circuit to which the vertical power MOSFET according to the present invention is applied.
- this switching power supply circuit the primary coil of the transformer 62 is driven by the switching element 61 according to the present invention, and the rectifier diode 63 and the power smoothing capacitor 64 are connected to the secondary coil of the transformer 62.
- the output voltage Vout is detected by an output voltage monitoring circuit, and a control voltage corresponding to a difference between the output voltage Vout and a desired voltage is formed, so that the output voltage Vout becomes a desired voltage. (Pulse width modulation)
- the duty of the pulse supplied to the switch element 61 is adjusted by the control circuit.
- the switch element 61 itself includes a current detection circuit and a gate disconnection circuit, and is connected in parallel according to a current required to drive a load.
- the number of power MOSFETs is switched. Therefore, as a switching power supply circuit, it is possible to obtain a switching power supply circuit in which loss in a low current region is significantly reduced without adding a special control system. As a result, the number of circuit elements constituting the switching power supply circuit can be reduced, so that the number of assembling steps can be reduced and the size and size of the mounting board can be reduced.
- FIG. 6 is a configuration diagram of another embodiment of the semiconductor device according to the present invention.
- FIG. 2A shows a plan view thereof
- FIG. 2B shows a corresponding cross-sectional view.
- the horizontal P-channel type MOSFET included in the gate cutting circuit shown in FIG. 2 is constituted by a semiconductor device of another chip.
- the semiconductor device of this embodiment includes a semiconductor chip composed of an N-channel vertical MOSFET and a horizontal MOSFET, a semiconductor chip composed of a P-channel lateral MOSFET and a hybrid IC. Be composed.
- the vertical power MOSFET 1, current detection circuit 3, and horizontal ⁇ -channel MOSFET divided into three as described above are formed on a ⁇ -channel semiconductor chip ( ⁇ -M ⁇ SIC) 40.
- ⁇ -M ⁇ SIC ⁇ -channel semiconductor chip
- P-MOS P-channel semiconductor chip
- the above semiconductor chip is mounted on the metal frame 42.
- An insulating substrate 43 is provided on the metal frame 42, and a semiconductor chip 41 is mounted thereon for insulation separation.
- the input terminal (gate electrode) as a hybrid IC is connected to the gate pad 4 by a metal wire 45, and the source electrode as a hybrid IC is connected to the source pad 5 of the semiconductor chip 40 by the metal wire 45. Connected.
- the semiconductor chips 40 and 41 are integrally sealed to form one semiconductor device (a hybrid IC).
- FIG. 7 is a circuit diagram showing another embodiment of the semiconductor device according to the present invention.
- FIG. 1 shows one vertical power MOSFET 1, a current detection circuit 3 and a gate cutting circuit 2 as a control circuit thereof. Therefore, in the case of being divided into a plurality of vertical power MOSFETs as described above, a plurality of voltage dividing resistance circuits of the current detection circuit are provided corresponding to the gate disconnection circuit.
- a horizontal N-channel MOSFET 5 is used between the gate of the vertical power MOSFET 1 and the gate pad 4.
- N-channel MOSFET it is not necessary to form the insulating separation layer 23 as shown in FIG. 3, and the gate disconnection circuit 2 as described above can be formed by a relatively simple process.
- the vertical power MOSFET including the current detection circuit 3 can be made into a monolithic IC.
- the control voltage supplied to the gate of the MOSFET 5 is a voltage E obtained by boosting the power supply voltage supplied from the power supply terminal 52 by the charge pump circuit 53.
- the charge pump circuit is composed of an oscillating circuit in which an odd number of inverter circuits are connected in a ring shape, and the oscillating pulse formed by such an oscillating circuit is rectified by a capacitor and a diode or diode type MOSFET to supply voltage. This is for forming a voltage that is raised as described above.
- a booster circuit a widely known circuit such as a booster circuit for forming a word line selection voltage of a dynamic RAM can be used.
- the current detection circuit is configured by connecting three resistors R1 to R3 in series.
- the low divided voltage obtained from the connection point between the resistors R2 and R1 is transmitted to the gate of the MOSFET in the preceding stage.
- the high divided voltage obtained from the junction of resistors R3 and R2 is transmitted to the gate of the subsequent MOSFET.
- the drain and source of the preceding MOSFET are connected between the gate and source of the latter MOSFET.
- the charge pump circuit is started by the drain output of the M ⁇ S FET at the subsequent stage.
- the preceding MOSFET is supplied with a low divided voltage to the gate, and the preceding MOSFET is turned off. Therefore, a relatively high divided voltage is supplied to the gate of the subsequent MOSFET to turn it on.
- the operation of the oscillation circuit is stopped by the ON state of the MOS FET at the subsequent stage.
- the gate voltage of the MOSFET in the subsequent stage will be lowered and the MOSFET in the latter stage will be turned off.
- the charge pump circuit starts operating, increasing the gate voltage of MOSFET5, and ultimately the gate voltage.
- the input signal supplied from the gate pad 4 is transmitted to the vertical MOSFET 1 without any level loss, and the switch is controlled.
- each divided voltage turns on the preceding MOS FET in response to the increase of the output current by the voltage dividing resistor circuit. Then, the subsequent M ⁇ SFET is switched to the off state, and the corresponding charge pump circuit starts operating to turn off the N-channel type gate cutting MO SFET.
- the charge pump circuit may be commonly used for a plurality of gate disconnecting MOSFETs.
- the boosted voltage formed by the charge pump circuit is used as the operating voltage, a high-resistance load resistance is provided between the latter MOSFET and the drain of the driving MOSFET, and the gate disconnection is performed. What is necessary is just to form the control signal of M ⁇ SFET. In other words, the boosted voltage is transmitted to the gate of the gate disconnecting MOSFET 5 via the load resistor by the off-state of the latter-stage MOSFET, and the MOSFET 5 can be turned on.
- FIG. 8 is a circuit diagram of another embodiment of the semiconductor device according to the present invention.
- an operating voltage is supplied from the gate pad 4 which is an input terminal, instead of a configuration in which an independent power supply terminal is provided as in the charge pump circuit shown in FIG.
- the charge pump circuit forms a boosted voltage using the high-level input voltage as an operating voltage.
- the oscillation frequency of the charge pump circuit is set to a sufficiently high frequency for the minimum period during which the gate pad is set to the high level, and in response to the change of the gate pad 4 to the high level, Within a short time A predetermined boosted voltage is formed.
- the other configuration is the same as that of the seventh embodiment, and a description thereof will be omitted.
- This configuration eliminates the need for a power supply terminal, and provides a power M ⁇ SFET composed of an easy-to-use monolithic IC.
- the voltage dividing resistance circuit may be a circuit as shown in FIG. 2, and a control signal for the charge pump circuit may be formed by one N-channel MOSFET receiving the divided voltage.
- the divided voltage rises in response to the increase in the output current, and the charge pump circuit starts operating to form the boosted voltage by the ON state of the N-channel M ⁇ SFET. do it.
- the charge pump circuits shown in FIGS. 7 and 8 may be provided in one-to-one correspondence with gate cutting MOSFETs of a plurality of vertical power MOSFETs.
- FIG. 9 is an equivalent circuit diagram for explaining another embodiment of the unit power M ⁇ S FET according to the present invention.
- a current detection circuit 3 and a gate cutting circuit 2 are provided in one-to-one correspondence with the 3 ⁇ -type power MOSFET 1.
- Such a vertical power MOSFET 1, a gate disconnection circuit 2, and a current detection circuit 3 constitute a set of unit circuits (functional blocks).
- N unit circuits corresponding to the maximum output current are formed on one semiconductor substrate to constitute a power switch M0SFET.
- Each of the N circuits composed of the functional blocks 1 to N is composed of the above unit circuits.
- the resistance ratios of the voltage dividing resistors R 1 and R 2 are different from each other in the respective function blocks 1 to N, and the number of function blocks connected in parallel in proportion to the increase in output current Let it increase.
- FIG. 11 is a circuit diagram of still another embodiment of the semiconductor device according to the present invention.
- a voltage dividing resistor is commonly used for a plurality of gate disconnection circuits 2, 2 ', and 2 ".
- the gate disconnection circuits 2, 2', and 2" are used in this order.
- the threshold voltage of the N-channel MOSFET that receives the above-mentioned partial pressure is increased sequentially.
- the vertical MOSFET and the MOSFET according to the present invention are consumed by the input capacitance by increasing the number of the vertical MOSFETs operated according to the output current as described above.
- the P-channel MOSFET for gate disconnection of the vertical power MOSFET provided to operate immediately in the middle current region is turned on. To form a subsequent output current. If the output current further increases, the vertical power MOSFET that was originally provided to operate in the large current region will also be turned on, and will work to supply the required output current.
- the inoperability of the power MOSFET prevents a loss of vehicle driving control that could lead to a serious accident. In other words, high reliability of the electronically controlled mechanical system can be ensured.
- a transistor that forms an output current is divided into a plurality of transistors, and a control circuit that sequentially increases the number of transistors that operate according to the level of the output current is provided.
- the effect is obtained that the power loss required for switching drive by reducing the input capacitance can be reduced.
- the vertical MO SFET for current detection is formed sufficiently smaller than the vertical power M ⁇ SF ET, and a small detection current corresponding to the size ratio is obtained. Thus, it is possible to obtain an effect that the output current can be detected with high accuracy while achieving the above.
- the M ⁇ SFET for gate disconnection is a horizontal P-channel M ⁇ SFET, and the control device is composed of a horizontal N-channel MOSFET that receives the divided voltage between its gate and the source pad.
- the control circuit can be configured with a simple circuit The effect is obtained.
- the above-mentioned P-channel MOSFET is formed on a separate chip, and is mounted on a single mounting board together with the semiconductor chips on which the above-mentioned vertical and horizontal N-channel MOSFETs are formed.
- the effect of simplifying the process of the semiconductor chip on which one M 0 SFET is mounted can be obtained.
- the M0 SFET for gate disconnection is composed of a horizontal N-channel M0 SFET, and the drain output of a control M ⁇ SFET composed of the horizontal N-channel M0 SFET receiving the divided voltage
- a control M ⁇ SFET composed of the horizontal N-channel M0 SFET receiving the divided voltage
- SFETs and control M ⁇ SFETs are provided in a one-to-one correspondence to form a unit circuit, and by configuring a semiconductor device from multiple unit circuits, multiple types of power MOSFETs corresponding to various maximum output currents can be realized. The effect that the semiconductor device provided can be easily configured can be obtained.
- the gate pad 4 may be constantly connected to the gate of one vertical power MOSFET, so that one vertical power MOSFET always operates.
- the number of divided vertical power MOSFETs may be three, four, etc. as described above.
- Vertical power MO split The areas of the SFETs need not be equal to each other. In general, the vertical MOSFETs are divided relatively finely within the widely used range, and the number of vertical MOSFETs connected in accordance with the output current is switched frequently according to the output current, and the normal current is reduced.
- a relatively large MOSFET corresponding to the maximum current is formed, and the large MOSFET operates when the output current exceeds the normal current use area.
- the elements constituting the power element and its control circuit are constituted by using a bipolar transistor in addition to the MOS SFET, or constituted by combining a bipolar transistor and an M ⁇ SFET. Is also good. Industrial applicability
- the present invention can be widely used for a semiconductor device including the above-described vertical power MOSFET.
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A plurality of output MOSFETs (1) whose drains and sources are made common and control circuits (2) containing MOSFETs (10) for cutting gates connected between the gates of the output MOSFETs (1) and the input terminals are formed on one semiconductor substrate or one mounting substrate. The number of the output MOSFETs (1) to which input signals from the input terminal are fed is increased by turning on the MOSFETs (10) by means of the control circuits (2) according to the increase of the output current.
Description
明 細 書 半導体装置 技術分野 Description Semiconductor device technology
この発明は、 半導体装置に関し、 主として縱型パワー MO S F E Tに 利用して有効な技術に関するものである。 背景技術 The present invention relates to a semiconductor device and, more particularly, to a technique effective for use in a vertical power MOS FET. Background art
スイッチング電源回路における損失を低減させる技術として、 スイツ チング M〇 S F E Tの駆動周波数や切り換えるもの、 あるレ、は並列動作 させるスィツチ MO S F E Tの個数を切り換えるようにしたもの力 \ 特 開平 7— 5 9 3 4 6号公報に開示されている。 As a technique for reducing the loss in the switching power supply circuit, switching M〇SFET drive frequency and switching, some are designed to switch the number of switch MO SFETs operated in parallel. No. 46 discloses this.
上記のように出力電流に応じてスィッチング素子の駆動周波数や並列 動作させる個数を制御するものでは、 スイッチング電源のシステム全体 に対して新たな制御系を設ける必要がある。 つまり、 上記特開平 7— 5 9 3 4 6号公報に従えば、 トランスの二次側に発生した負荷電流を負荷 電流検出回路により検出し、 それと基準電圧とをコンパレー夕で比較し 、 上記スィッチ素子の繰り返し周波数を変化させ、 あるいはスィッチン グ素子の数を切り換えるという制御系を設けることが必要となり、 スィ ツチング電源の小型化、 ひいては低コトス化を妨げるものである。 この発明は、 その出力電流に応じた電流供給能力が切り換えられるよ うにした新たな機能を持つパヮ一 M〇 S F E Tを備えた半導体装置を提 供することを目的としている。 この発明の前記ならびにそのほかの目的 と新規な特徴は、 本明細書の記述および添付図面から明らかになるであ ろう。
発明の開示 In the case of controlling the driving frequency of switching elements and the number of switching elements operated in parallel according to the output current as described above, it is necessary to provide a new control system for the entire switching power supply system. In other words, according to the above-mentioned Japanese Patent Application Laid-Open No. 7-59364, the load current generated on the secondary side of the transformer is detected by a load current detection circuit, and the reference current is compared with a reference voltage. It is necessary to provide a control system that changes the repetition frequency of the elements or switches the number of switching elements, which hinders the miniaturization of switching power supplies and, consequently, the reduction in cost. An object of the present invention is to provide a semiconductor device including a power MOSFET having a new function capable of switching a current supply capability according to the output current. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention
本発明は、 1つの半導体基板又は 1つの実装基板上において、 ドレイ ンとソースがそれぞれ共通化された複数の出力 M〇 S F E Tと、 かかる 出力 MOSFETのゲートと入力端子との間に挿入されたゲート切断用 の M 0 S F E Tを含む制御回路とを形成しておき、 上記制御回路により 出力電流の増加に対応してゲート切断用の MOSFETをオン状態にさ せて、 入力端子から供給される入力信号が伝えられる出力 MOSFET の数を増加させる。 図面の簡単な説明 The present invention provides a plurality of output M〇SFETs having a common drain and source on one semiconductor substrate or one mounting substrate, and a gate inserted between the gate of the output MOSFET and the input terminal. A control circuit including an M 0 SFET for disconnection is formed, and the MOSFET for gate disconnection is turned on in response to an increase in output current by the above control circuit, so that an input signal supplied from an input terminal is provided. Increases the number of output MOSFETs transmitted. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 この発明に係るパワー MOSFETの一実施例を示すプロ ック図であり、 第 2図は、 上記第 1図に示したパワー MOSFETの等 価回路図であり、 第 3図は、 上記第 1図に示したパワー MOSFETの 概略素子構造断面図であり、 第 4図は、 パワー MOSFETの寄生容量 を説明するための構成図であり、 第 5図は、 この発明に係るパワー MO SFETの寄生容量を説明するための等価回路図であり、 第 6図は、 こ の発明に係るパワー M〇S F ETの他の一実施例を示す構成図であり、 第 7図は、 この発明に係るパワー MOSFETの他の一実施例を示す要 図等価回路図であり、 第 8図は、 この発明に係るパワー MOSFETの 他の一実施例を示す要部等価回路図であり、 第 9図は、 この発明に係る 単位のパワー M〇 S F E Tの他の一実施例を説明するための等価回路図 であり、 第 10図は、 上記第 9図のパワー MOSFETを用いて構成さ れるパワー MOSFETの一実施例を示すブロック図であり、 第 1 1図 は、 この発明に係るパワー MOSFETの更に他の一実施例を示す等価 回路図であり、 第 12図は、 この発明に係るパワー MOSFETを用い
たスィッチング電源の一実施例を示すプロック図である。 発明を実施するための最良の形態 FIG. 1 is a block diagram showing an embodiment of the power MOSFET according to the present invention, FIG. 2 is an equivalent circuit diagram of the power MOSFET shown in FIG. 1, and FIG. FIG. 4 is a schematic cross-sectional view of the element structure of the power MOSFET shown in FIG. 1, FIG. 4 is a configuration diagram for explaining the parasitic capacitance of the power MOSFET, and FIG. FIG. 6 is an equivalent circuit diagram for explaining the parasitic capacitance of the SFET. FIG. 6 is a configuration diagram showing another embodiment of the power M〇SFET according to the present invention. FIG. FIG. 8 is an essential circuit equivalent circuit diagram showing another embodiment of the power MOSFET according to the present invention. FIG. 8 is an essential circuit equivalent circuit diagram showing another embodiment of the power MOSFET according to the present invention. FIG. 10 is an equivalent circuit diagram for explaining another embodiment of the unit power M〇SFET according to the present invention. FIG. 9 is a block diagram showing an embodiment of a power MOSFET configured using the power MOSFET of FIG. 9; FIG. 11 is an equivalent circuit showing still another embodiment of the power MOSFET according to the present invention; FIG. 12 shows a power MOSFET according to the present invention. FIG. 2 is a block diagram showing an embodiment of a switching power supply. BEST MODE FOR CARRYING OUT THE INVENTION
この発明をより詳細に説述するために、 添付の図面に従ってこれを説 明する。 The present invention will be described in more detail with reference to the accompanying drawings.
第 1図には、 この発明に係るパワー MOSFETの一実施例のブ αッ ク図が示されている。 同図の各回路ブロックは、 公知の半導体製造技術 により、 単結晶シリコンのような 1個の半導体基板上において形成され る。 上記各回路ブロックは、 上記半導体基板上における実際上の幾何学 的な配置にほぼ合わせて描かれている。 FIG. 1 is a block diagram of one embodiment of a power MOSFET according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique. Each of the circuit blocks is drawn substantially in accordance with the actual geometric arrangement on the semiconductor substrate.
この実施例のパワー MOSFETは、 大きく分けると 3個からなる縦 型パワー MOSFET 1 と、 その制御回路 7から構成される。 上記制御 回路 7は、 ゲート切断回路 2、 電流検出回路 3及びこれらを接続する配 線 8から構成される。 上記縦型パワー MOSFET 1のソースは、 ソ一 スパッ ド 5に共通に接続され、 ドレインは裏面のドレイン電極 6により 共通化されている。 そして、 入力端子であるゲートパッ ド 4は、 ゲート 切断回路 2を介して上記 3の縱型パワー MOSFET 1のゲートと接続 される。 電流検出回路 3は、 後述するように上記縦型パワー MOSFE Tの電流ミラ一形態にされた縦型 MOSFETが用いられ、 そのために ゲートは上記ゲートパッ ド 4に接続され、 ドレインは半導体基板そのも ので共通化されており、 上記裏面ドレイン電極と接続される。 The power MOSFET of this embodiment is roughly composed of three vertical power MOSFETs 1 and a control circuit 7 therefor. The control circuit 7 includes a gate disconnection circuit 2, a current detection circuit 3, and a wiring 8 connecting these. The source of the vertical power MOSFET 1 is commonly connected to the source pad 5, and the drain is shared by the drain electrode 6 on the back surface. Then, the gate pad 4 as an input terminal is connected to the gate of the vertical power MOSFET 1 of 3 above via the gate cutting circuit 2. The current detection circuit 3 uses a vertical MOSFET in the form of a current mirror of the vertical power MOSFET, as described later, so that the gate is connected to the gate pad 4 and the drain is the semiconductor substrate itself. It is common and is connected to the back surface drain electrode.
第 2図には、 上記第 1図に示したパワー MO SFE Tの等価回路図が 示されている。 3個の縦型パワー MOS F ET 1のドレイン及び電流検 出回路 3を構成する縦型 MOSFET 1 4のドレインは、 ドレイン電極 6に共通接続される。 上記 3個の縦型パワー MOSFET 1のソースは 、 ソースパッ ド 5に共通にされる。
上記電流検出回路 3は、 縦型 MOSFET 1 4と、 そのソースと上記 ソースパッ ド 5との間に設けられた抵抗回路からなる。 抵抗回路は、 上 記 3個の縱型ノ ヮー M 0 S F E Tに対応して 3個の分圧抵抗回路から構 成される。 上記各抵抗回路は、 特に制限されないが、 それぞれの合成抵 抗は同じ抵抗値を持つようにされ、 上記縦型 MOSFET 1 4のソース , ドレイン電流が 3等分に分流するようにされる。 上言己縱型 MOSFE T 1 4に流れる電流が上記各分圧抵抗回路に分流して等しく流れ、 例示 的に示されているような抵抗 1 2と抵抗 1 3の抵抗比により所定の第 1 の分圧電圧を形成する。 他の分 抵抗回路においても、 それぞれの抵抗 比が異なり、 それぞれ異なる第 2、 第 3の分圧電圧を形成する。 FIG. 2 shows an equivalent circuit diagram of the power MOSFET shown in FIG. The drains of the three vertical power MOSFETs 1 and the drains of the vertical MOSFETs 14 constituting the current detection circuit 3 are commonly connected to a drain electrode 6. The sources of the three vertical power MOSFETs 1 are shared by the source pad 5. The current detection circuit 3 includes a vertical MOSFET 14 and a resistance circuit provided between a source of the MOSFET 14 and the source pad 5. The resistance circuit is composed of three voltage-dividing resistance circuits corresponding to the above-mentioned three vertical type MOSFETs. Although there is no particular limitation on each of the resistor circuits, each of the combined resistors has the same resistance value, and the source and drain currents of the vertical MOSFET 14 are divided into three equal parts. The current flowing through the vertical MOSFET 14 is divided into the respective voltage-dividing resistor circuits and flows equally, and a predetermined first current is obtained by a resistance ratio of the resistors 12 and 13 as shown in the example. Is formed. The other divided resistor circuits also have different resistance ratios and form different second and third divided voltages.
ゲ一ト切断回路 2は、 例示的に示されているように横型の Pチヤンネ ル型 MOSFET 1 0と横型の Nチャンネル型 MOSFET 1 1から構 成される。 上記 Pチャンネル型 MOSFET 1 0は、 入力端子であるゲ ―トパッ ド 4と縦型パワー MOSFETのゲートとの間に設けられる。 この Pチヤンネル型 MOSFET 1 0のゲ一卜とソースパッ ド 5との間 には、 上記 Nチャンネル型 MOSFET 1 1か設けられる。 この Nチヤ ンネル型 MOSFET 1 1のゲー卜には、 上記抵抗 1 2と 1 3で分圧さ れた第 1の分圧電圧が供給される。 The gate cutting circuit 2 is composed of a lateral P-channel MOSFET 10 and a lateral N-channel MOSFET 11 as shown as an example. The P-channel MOSFET 10 is provided between the gate pad 4 as an input terminal and the gate of the vertical power MOSFET. The N-channel MOSFET 11 is provided between the gate of the P-channel MOSFET 10 and the source pad 5. The first divided voltage divided by the resistors 12 and 13 is supplied to the gate of the N-channel MOSFET 11.
他の縦型パワー MOSFETに対応したゲ—卜切断回路 2' 及び 2" も、 上記同様に横型の Pチャンネル型 MOSFETと横型の Nチャンネ ル型 MOSFETの組み合わせにより構成され、 それぞれの Nチャンネ ル型 MOSFETのゲー卜には、 上記分圧抵抗回路により形成された第 2、 第 3の分圧電圧が供給される。 Gate disconnection circuits 2 'and 2 "corresponding to other vertical power MOSFETs are also composed of a combination of horizontal P-channel MOSFETs and horizontal N-channel MOSFETs as described above. The gate of the MOSFET is supplied with the second and third divided voltages formed by the above-mentioned voltage dividing resistor circuit.
第 3図には、 この発明に係る半導体装置の要部素子構造断面図が示さ れている。 同図には、 代表として上記 1つの縦型パワー MOSFET 1 、 ゲート切断回路 2を構成する 2つの横型 MOSFET、 電流検出回路
3を構成する縦型 MOSFET及び抵抗 2 1が示されている。 FIG. 3 is a cross-sectional view of a main element structure of a semiconductor device according to the present invention. In the figure, the above-mentioned one vertical power MOSFET 1, two horizontal MOSFETs composing the gate disconnection circuit 2 and the current detection circuit The vertical MOSFET and the resistor 21 constituting 3 are shown.
この実施例では、 特に制限されないが、 N +からなる半導体基板 26 上に N—からなるェピタキシャル層 25を形成し、 このェピタキシャル 層 24に以下の各素子を構成するための各半導体層が形成される。 縦型パワー MOSFET 1は、 その一部のソース, ドレイン、 及びゲ 一卜が代表として例示的に示されているように、 ェピタキシャル層 25 が上記基板層 26とともにドレイン領域を構成し、 裏面金属薄膜電極 2 7がドレイン端子 6として用いられる。 上記ェピタキシャル層 25の表 面に形成された P+拡散層がチャンネル領域とされ、 かかる P+拡散層 に形成された N +拡散層がソース領域とされる。 上記チャンネルとして の P+拡散層と上記ソースとしての N +拡散層とは、 アルミ二ユウム等 の電極により共通接続され、 ソース端子 5とされる。 ゲート電極は、 ポ リシリコン (Poly- Si) 20からなり、 上記 P +拡散層のチャンネル領域 上であって、 薄いゲ一ト絶縁膜を介して N+拡散層のソースとドレイン としてのェピ夕キンャル層 25を跨ぐように形成される。 かかるゲート 電極 20の一端は、 ゲート切断回路 2に延長され、 ゲート切断回路 2と の間の配線の一部としても利用される。 In this embodiment, although not particularly limited, an epitaxial layer 25 made of N— is formed on a semiconductor substrate 26 made of N +, and each semiconductor layer for constituting each of the following elements is formed on the epitaxial layer 24. It is formed. In the vertical power MOSFET 1, the epitaxy layer 25 constitutes a drain region together with the substrate layer 26, as shown by way of example, a part of the source, the drain and the gate as a representative. The thin film electrode 27 is used as the drain terminal 6. The P + diffusion layer formed on the surface of the epitaxial layer 25 is a channel region, and the N + diffusion layer formed on the P + diffusion layer is a source region. The P + diffusion layer as the channel and the N + diffusion layer as the source are commonly connected by an electrode of aluminum or the like to serve as a source terminal 5. The gate electrode is made of polysilicon (Poly-Si) 20 and is located on the channel region of the P + diffusion layer. The thin gate insulating film is used to form the N + diffusion layer as a source and a drain. It is formed so as to straddle the layer 25. One end of the gate electrode 20 is extended to the gate cutting circuit 2 and is also used as a part of a wiring between the gate electrode 20 and the gate cutting circuit 2.
ゲ一ト切断回路 2は、 上記ェピタキシャル層 25に形成された P型の 絶縁分離層 23が形成され、 ここに横型の Pチャンネル型 MOSFET を形成するための N—のゥヱル (WELL) 領域 24が形成される。 上 記ェピタキシャル層 25の残りの部分には、 横型の Nチャンネル型 MO SFETを形成するための P型からなるゥエル (WELL) 領域 24が 形成される。 上記横型の Pチャンネル型 MOSFETは、 上記ゥ ル層 24に P+型のソース、 ドレインが形成され、 かかるソース一ドレイン を跨ぐようにゲート電極が形成される。 特に制限されないが、 高耐圧化 等のために、 縦型パワー MOSFET側に接続されるソース, ドレイン
W 領域は P—型の拡散層が形成され、 かかる P—層が実質的なソース, ド レイン領域となるように上記ゲート電極が形成される。 The gate cutting circuit 2 includes a P-type insulating separation layer 23 formed on the above-mentioned epitaxial layer 25, and an N-cell (WELL) region 24 for forming a lateral P-channel MOSFET. Is formed. In the remaining portion of the epitaxial layer 25, a P-type well region 24 for forming a lateral N-channel MOSFET is formed. In the lateral P-channel MOSFET, a P + type source and drain are formed in the metal layer 24, and a gate electrode is formed so as to straddle the source-drain. Although not particularly limited, the source and drain connected to the vertical power MOSFET side for higher breakdown voltage, etc. In the W region, a P-type diffusion layer is formed, and the gate electrode is formed such that the P- layer becomes a substantial source and drain region.
上記縦型パワー MOSFETのゲ一ト電極は、 アルミニウム等の配線 層により上記横型の Pチャンネル型 MOSFETのソース, ドレインを The gate electrode of the vertical power MOSFET is connected to the source and drain of the horizontal P-channel MOSFET by a wiring layer such as aluminum.
05 構成する P+層に接続される。 他方のソース, ドレインを構成する P + 層には、 隣接して上記 N—型のゥヱル領域 24に対する良好なォ一ミッ クコンタクトを得るための N+層が形成され、 アルミニウム等の配線手 段によって共通接続されるとともに、 ゲート端子 1に接続される。 上記横型の Nチャンネル型 MOSFETは、 上記ゥエル層 24に N +05 Connected to constituent P + layer. An N + layer is formed adjacent to the other P + layer constituting the source and drain to obtain a good ohmic contact with the N− type cell region 24, and is formed by a wiring means such as aluminum. Commonly connected and connected to gate terminal 1. The lateral N-channel MOSFET described above has N +
10 型のソース、 ドレィンが形成され、 かかるソース一ドレインを跨ぐよう にゲート電極が形成される。 特に制限されないが、 高耐圧化等のために 、 上記横型の Pチャンネル型 MOSFETのゲー卜に接続されるソース , ドレイン領域は N—型の拡散層が形成され、 かかる N—層が実質的な ソース, ドレイン領域となるように上記ゲート電極が形成される。 上記A 10-type source and drain are formed, and a gate electrode is formed so as to straddle the source-drain. Although there is no particular limitation, N-type diffusion layers are formed in the source and drain regions connected to the gate of the lateral P-channel MOSFET to increase the breakdown voltage and the like. The gate electrode is formed so as to be the source and drain regions. the above
15 横型の Nチャンネル型 MOSFETの他方のソース, ドレインを構成す る N+層には、 隣接して上記 P型のゥヱル領域 24に対する良好なォ一 ミ ックコンタクトを得るための P+層が形成され、 アルミニウム等の配 線手段によって共通接続されるとともにソース端子 5に接続される。 電流検出回路 3を構成する縱型 MO S F E Tは、 上記縱型パワー MO15 On the N + layer that constitutes the other source and drain of the lateral N-channel MOSFET, a P + layer is formed adjacent to the N-type MOSFET to obtain good uniform contact with the P-type transistor region 24. And is connected to the source terminal 5 by the wiring means such as. The vertical MO S F E T constituting the current detection circuit 3 is
20 SFET 1と同一の構造にされる。 ただし、 同図では明らかにされてい ないが、 かかる電流検出用の縦型 MOSFETのソース, ドレインの面 積は、 上記縦型のパワー MOSFET 1の面積に対して大幅に小さくさ れ、 その面積比に従った小さな電流しか流さないようにされる。 特に制 限されないが、 縦型パワー MOSFET1の全体の出力電流の 1Z1 0It has the same structure as 20 SFET 1. However, although not clarified in the figure, the area of the source and drain of the vertical MOSFET for current detection is greatly reduced with respect to the area of the vertical power MOSFET 1 described above. Only a small current in accordance with Although not particularly limited, 1Z10 of the total output current of the vertical power MOSFET 1
25 00の電流が、 上記電流検出用の縦型 MO S F E Tに流れるように設定 される。
この縱型 MOSFETのゲートは、 ゲート端子 1に接続され、 ドレイ ンが上記基板層 26によって共通化されていることから、 上記縦型パヮ -MOSFET 1とは電流ミラー形態にされる。 上記電流検出用の縦型 MOSFETのソースは、 アルミニウム等の配線手段によって、 ポリシ リコン抵抗 2 1の一端に接続され、 かかるポリシリコン抵抗 2 1の他端 は、 上記ソース端子 5に接続され、 その中間部から分圧電圧得るための 配線が設けられ、 上記横型の Nチャンネル型 MOSFETのゲートに接 続さている。 これにより、 上記第 2図の等価回路に示したような半導体 装置を得ることができる。 The current of 2500 is set to flow through the vertical MOSFET for current detection. Since the gate of the vertical MOSFET is connected to the gate terminal 1 and the drain is shared by the substrate layer 26, the vertical MOSFET 1 is in a current mirror form. The source of the vertical MOSFET for current detection is connected to one end of a polysilicon resistor 21 by wiring means such as aluminum, and the other end of the polysilicon resistor 21 is connected to the source terminal 5. Wiring for obtaining a divided voltage is provided from the middle part, and is connected to the gate of the lateral N-channel MOSFET. Thereby, a semiconductor device as shown in the equivalent circuit of FIG. 2 can be obtained.
第 4図には、 上記のような縦型パワー MOSFETにおける寄生容量 を説明するための構成図が示されている。 同図 (A) の等価回路に示す ように、 ゲート, ソース容量 CGS、 ゲート, ドレイン容量 CGD、 及 びドレイン, ソース容量 CDSの各寄生容量は、 同図 (B) の断面図に 示すようになる。 FIG. 4 is a configuration diagram for explaining the parasitic capacitance in the vertical power MOSFET as described above. As shown in the equivalent circuit in (A), the parasitic capacitances of the gate and source capacitance CGS, gate and drain capacitance CGD, and the drain and source capacitance CDS are as shown in the cross-sectional view of FIG. Become.
ゲート, ソース間容量 CGSは、 アルミニウム等からなるソース電極 5とポリシリコン層からなるゲ一ト電極との間の容量であり、 Gate-source capacitance CGS is the capacitance between the source electrode 5 made of aluminum or the like and the gate electrode made of a polysilicon layer.
ドレイン, ソース間容量 CGDは、 上記ゲート電極の下に形成された ゲート絶縁膜及びチャンネル領域に形成された空乏層を誘電体とする寄 生容量であり、 The drain-source capacitance CGD is a parasitic capacitance having a gate insulating film formed under the gate electrode and a depletion layer formed in the channel region as a dielectric.
ゲート, ドレイン間容量 CDSは、 ソース領域とドレイン領域との間 の空乏層を誘電体とする寄生容量である。 Gate-drain capacitance CDS is a parasitic capacitance that uses the depletion layer between the source and drain regions as a dielectric.
上記のような縦型パワー MO S F E Tは、 大きな電流供給能力を持つ ようにするために、 大きなサイズにされる。 それ故、 上記各寄生容量は 無視できない大きな容量値を持つものとなる。 したがって、 スィッチン グ電源回路におけるスィッチ素子として用いた場合には、 この寄生容量 に対する充放電電流が損失を増大させる原因となる。
スイッチング電源回路は、 通常 1 00%負荷で使用されることは稀れ である。 言い換えるならば、 最悪条件のときに 1 00%負荷となるよう に余裕をもった電流供給能力に設計されている。 このために、 通常の使 用形態においては、 低負荷での動作となり、 負荷電流が小さい場合には それに対応してスィッチ素子の出力電流は減少させられる。 しかしなが ら、 かかるスィツチ素子を駆動するため常時上記寄生容量を充放電させ るための電流は、 上記出力電流には無関係に一定となり、 低負荷時での 損失が占める割合が大きくなり、 かな DC— D C変換効率を低下させ てしまうという問題が生じる。 Vertical power MOSFETs such as those described above are sized to have a large current supply capability. Therefore, each of the above parasitic capacitances has a large capacitance value that cannot be ignored. Therefore, when used as a switching element in a switching power supply circuit, the charge / discharge current for this parasitic capacitance causes an increase in loss. Switching power supply circuits are rarely used at 100% load. In other words, the current supply capacity is designed to have a margin so that the load becomes 100% under the worst condition. For this reason, in a normal use mode, the operation is performed at a low load, and when the load current is small, the output current of the switch element is correspondingly reduced. However, the current for constantly charging / discharging the parasitic capacitance to drive such a switch element is constant irrespective of the output current. The problem of lowering the DC-DC conversion efficiency occurs.
この実施例では、 前記のように各縦型パワー MOSFETのゲートと 入力端子との間には、 ゲート切断回路が設けられており、 かかるゲート 切断回路を構成する上記 Pチャンネル型 M 0 S F E Tがオフ状態のとき には、 第 5図の等価回路図に示すように、 人力端子であるゲート端子 4 と縦型パワー MOSFET 1のゲートとの間には、 上記 Pチャンネル型 MOSFETのソース, ドレイン間の寄生容量 Coss が直列に挿入され る。 この寄生容量 Coss は、 上記パワー MOSFETの入力容量 CGS + CGDに比べて大幅に小さく、 入力端子 4から上記入力容量 CGS + CGDを見えなくすることができる。 In this embodiment, as described above, a gate disconnection circuit is provided between the gate of each vertical power MOSFET and the input terminal, and the P-channel M 0 SFET constituting such a gate disconnection circuit is turned off. In the state, as shown in the equivalent circuit diagram of FIG. 5, between the gate terminal 4 which is a human-powered terminal and the gate of the vertical power MOSFET 1, there is a connection between the source and the drain of the P-channel MOSFET. Parasitic capacitance Coss is inserted in series. This parasitic capacitance Coss is much smaller than the input capacitance CGS + CGD of the power MOSFET, and the input capacitance CGS + CGD can be made invisible from the input terminal 4.
すなわち、 第 2図の等価回路において、 ドレイン電極 6の出力電流が 零のときには、 縦型 MOSFET 1 4に流れる電流も零であるために、 分圧抵抗回路により形成される分圧電圧が、 ソース電位と同じになるた めに、 横型の Nチャンネル型 MOSFETがオフ状態にされており、 こ れに対応して横型の Pチャンネル型 M OSFETもオフ状態にされる。 それ故、 ゲートパッ ド 4からみると、 上記縱型パワー MOSFET 1の 1/1 000の電流しか流さないように小さく形成された縦型 M〇SF ET 1 4のゲート容量等の入力容量しか見えないので、 例え入力端子で
あるゲ一トパッド 4にハイレベル/ロウレベルの制御信号が供給されて もそこで消費される電流は極小さ 、電流にしか成らなレ、。 That is, in the equivalent circuit of FIG. 2, when the output current of the drain electrode 6 is zero, the current flowing through the vertical MOSFET 14 is also zero, so that the divided voltage formed by the voltage dividing resistor circuit is The horizontal N-channel MOSFET is turned off to make it equal to the potential, and the horizontal P-channel MOSFET is turned off correspondingly. Therefore, when viewed from the gate pad 4, only the input capacitance such as the gate capacitance of the vertical M〇SF ET 14 formed so small that only 1/1000 of the current of the vertical power MOSFET 1 flows can be seen. So, even if the input terminal Even when a high-level / low-level control signal is supplied to a certain gate pad 4, the current consumed there is extremely small, and only a current is generated.
出力電流が流れ始める起動時には、 上記電流検出用の縱型 MOS F E T 1 4から供給される。 この電流が上記抵抗回路に流れ込み、 上記抵抗 1 2と 1 3で発生した分圧電圧が、 横型の Nチャンネル型 MOSFET 1 1のしきい値電圧に到達すると、 かかる MOSFET 1 1がオン状態 となり、 横型の Pチャンネル型 MOSFET 1 0のゲートにソースパッ ド 5に対応した基準電圧 (ロウレベル) を供給する。 これにより、 横型 の Pチャンネル型 MOSFET 1 0がオン状態となり、 上記入力端子で あるゲートパッ ド 4から供給される入力信号は、 縦型のパワー MOSF ETのゲー卜に伝えられ、 この縦型パワー MOSFETによって上記出 力電流が供給される。 At the time of startup when the output current starts to flow, the current is supplied from the vertical MOS FET 14 for current detection. When this current flows into the resistor circuit and the divided voltage generated by the resistors 12 and 13 reaches the threshold voltage of the lateral N-channel MOSFET 11, the MOSFET 11 is turned on, A reference voltage (low level) corresponding to source pad 5 is supplied to the gate of horizontal P-channel MOSFET 10. As a result, the horizontal P-channel MOSFET 10 is turned on, and the input signal supplied from the gate pad 4 as the input terminal is transmitted to the vertical power MOSFET gate, and the vertical power MOSFET Supplies the output current.
以後、 低電流領域においては、 上記縱型パワー MOSFETを通して 出力電流が供給され、 縱型パワー MOSFET 1と電流検出用の縦型 M OSFET 1 4とのサイズ比に対応した検出電流が流れ、 かかる検出電 流によって、 抵抗 1 2と 1 3に発生した分圧電圧により上記横型 MOS FET 1 1がオン状態とされ、 上記横型 MOSFET 1 0のオン状態が 維持される。 Thereafter, in the low current region, the output current is supplied through the vertical power MOSFET, and a detection current corresponding to the size ratio between the vertical power MOSFET 1 and the vertical MOS FET 14 for current detection flows. The lateral MOS FET 11 is turned on by the divided voltage generated in the resistors 12 and 13 by the current, and the on state of the lateral MOSFET 10 is maintained.
上記出力電流が更に増加する中電流領域では、 電流検出用の縱型 MO SFET 1 4に流れる電流が増加し、 それに応じて抵抗回路で発生した 第 2の分圧電圧が上昇して、 ゲート切断回路 2' に対応した横型 MOS F E Tがォン状態にされ、 この結果 2つの縦型ノ ヮー MOSFETを並 列接続された状態となり、 上記中電流領域での出力電流をまかなうもの となる。 In the middle current region where the output current further increases, the current flowing through the vertical MOSFET 14 for current detection increases, and the second divided voltage generated in the resistor circuit increases accordingly, and the gate is disconnected. The lateral MOS FET corresponding to the circuit 2 'is turned on, and as a result, two vertical MOSFETs are connected in parallel, and the output current in the medium current region is covered.
上記出力電流が更に増加する大電流領域では、 電流検出用の縦型 MO SFET 1 4に流れる電流が更に増加し、 それに応じて抵抗回路で発生
した第 3の分圧電圧が上昇して、 ゲート切断回路 2 " に対応した横型 M 0 S F E Tがオン状態にされ、 この結果 3個全ての縦型パワー MO S F E Tを並列接続された状態となり、 上記大電流領域での出力電流をまか なうものとなる。 In the large current region where the output current further increases, the current flowing through the vertical MOSFET 14 for current detection further increases and is generated in the resistor circuit accordingly. The third divided voltage rises, and the horizontal M 0 SFET corresponding to the gate disconnection circuit 2 "is turned on. As a result, all three vertical power MO SFETs are connected in parallel, and It covers the output current in the large current region.
以上のように、 必要な出力電流に対応して自動的に並列接続される縦 型パワー MO S F E Tの数が順次に増加する。 このことは、 出力電流に 対応して縦型パワー MO S F E Tの寄生容量も変化するものとなり、 そ のスィツチ制御のために費やされる充放電電流が出力電流に対応して変 化し、 損失を最小に抑えることができる。 As described above, the number of vertical power MOSFETs connected in parallel automatically increases in response to the required output current. This means that the parasitic capacitance of the vertical power MOSFET changes in accordance with the output current, and the charge and discharge current consumed for the switch control changes in accordance with the output current, minimizing the loss. Can be suppressed.
第 1 2図には、 この発明に係る縦型パワー MO S F E Tが適用される スィツチング電源回路の一実施例のブロック図が示されている。 このス イツチング電源回路は、 この発明に係るスィッチング素子 6 1により ト ランス 6 2の 1次側コィルを駆動し、 上記トランス 6 2の 2次側コィル に整流ダイオード 6 3と電源平滑コンデンサ 6 4かなる平滑回路を設け 、 その出力電圧 Vout を出力電圧監視回路で検出し、 所望の電圧との差 分に対応した制御電圧を形成し、 上記出力電圧 Vout が所望の電圧とな るように P WM (パルス幅変調) 制御回路により上記スィッチ素子 6 1 に供給されるパルスのデューティを調整する。 FIG. 12 is a block diagram showing one embodiment of a switching power supply circuit to which the vertical power MOSFET according to the present invention is applied. In this switching power supply circuit, the primary coil of the transformer 62 is driven by the switching element 61 according to the present invention, and the rectifier diode 63 and the power smoothing capacitor 64 are connected to the secondary coil of the transformer 62. The output voltage Vout is detected by an output voltage monitoring circuit, and a control voltage corresponding to a difference between the output voltage Vout and a desired voltage is formed, so that the output voltage Vout becomes a desired voltage. (Pulse width modulation) The duty of the pulse supplied to the switch element 61 is adjusted by the control circuit.
このようなスイッチング電源回路において、 上記スィッチ素子 6 1力べ それ自体に電流検出回路とゲート切断回路とを備えており、 負荷を駆動 するのに必要な電流に応じて、 並列接続される縦型パワー MO S F E T の数が切り換えられる。 それ故、 スイッチング電源回路としては、 格別 な制御系を追加することなく、 低電流領域での損失を大幅に低減させた スイッチング電源回路を得ることができる。 この結果、 スイッチング電 源回路を構成する回路素子数が低減でき、 その組み立て工数の低減や実 装基板の小型柽量化が可能となる。
上記のようなスィツチング素子自体に電流検出回路ゃゲ一ト切断回路 を付加した場合には、 既存のスィツチング電源回路のスィツチ素子の部 分を上記のような本願発明に係る半導体装置に置き換えるという簡単な 構成により、 低電流領域での D C - D C変換効率を大幅に改善させるこ ともできるようになる。 つまり、 既存のスイッチング電源回路における 制御系は、 そのままで上記のような低電流での効率改善が簡単にできる ようになるものである。 In such a switching power supply circuit, the switch element 61 itself includes a current detection circuit and a gate disconnection circuit, and is connected in parallel according to a current required to drive a load. The number of power MOSFETs is switched. Therefore, as a switching power supply circuit, it is possible to obtain a switching power supply circuit in which loss in a low current region is significantly reduced without adding a special control system. As a result, the number of circuit elements constituting the switching power supply circuit can be reduced, so that the number of assembling steps can be reduced and the size and size of the mounting board can be reduced. In the case where a current detection circuit and a gate disconnection circuit are added to the switching element itself as described above, it is simple to replace the switching element part of the existing switching power supply circuit with the semiconductor device according to the present invention as described above. With such a configuration, the DC-DC conversion efficiency in the low current region can be greatly improved. In other words, the control system in an existing switching power supply circuit can easily improve efficiency at low current as described above.
第 6図には、 この発明に係る半導体装置の他の一実施例の構成図が示 されている。 同図 (A) には、 その平面図が示され、 (B) には、 それ に対応した断面図が示されている。 この実施例では、 第 2図のゲ一ト切 断回路に含まれる横型の Pチャンネル型 MO S F E Tが別チップの半導 体装置により構成される。 つまり、 この実施例の半導体装置は、 Nチヤ ンネル型の縦型 MO SFE T及び横型 MO SFE Tからなる半導体チッ プと、 Pチャンネル型の横型 M OSFETからなる半導体チップとカ 、 ィブリッ ド I Cとして構成される。 FIG. 6 is a configuration diagram of another embodiment of the semiconductor device according to the present invention. FIG. 2A shows a plan view thereof, and FIG. 2B shows a corresponding cross-sectional view. In this embodiment, the horizontal P-channel type MOSFET included in the gate cutting circuit shown in FIG. 2 is constituted by a semiconductor device of another chip. In other words, the semiconductor device of this embodiment includes a semiconductor chip composed of an N-channel vertical MOSFET and a horizontal MOSFET, a semiconductor chip composed of a P-channel lateral MOSFET and a hybrid IC. Be composed.
この理由は、 前記実施例のように 1つの半導体基板上に Pチャンネル 型の M〇 S F E Tを形成するためには、 素子分離のための分離領域を形 成する必要がありプロセスを複雑にしてしまう。 そこで、 かかる Pチヤ ンネル型の MOSFETの部分を別チップとすることにより、 ウェハプ αセスの簡素化が図るものである。 The reason for this is that in order to form a P-channel type M〇 SFET on one semiconductor substrate as in the above embodiment, it is necessary to form an isolation region for element isolation, which complicates the process. . Therefore, the wafer process is simplified by using such a P-channel type MOSFET as a separate chip.
(Α) において、 上記のように 3分割された縱型パワー MOSFET 1、 電流検出回路 3及び横型の Νチャンネル型 MOSFETは、 Νチヤ ンネル型の半導体チップ (Ν— M〇S I C) 40に形成される。 また、 横型の Ρチャンネル型 MOSFETと入力端子としてのゲ一トパッ ド 4 とは、 Pチャンネル型の半導体チップ (P— MOS) 4 1に形成される 。 これらの半導体チップ 40と 4 1には、 それぞれを相互に接続するた
めのボンディングパッドが設けられている。 そして、 これらの相互の接 続は、 金属ワイヤ 44によって相互に接続される。 In (Α), the vertical power MOSFET 1, current detection circuit 3, and horizontal Ν-channel MOSFET divided into three as described above are formed on a Ν-channel semiconductor chip (Ν-MΝSIC) 40. You. The horizontal Ρ-channel MOSFET and the gate pad 4 as an input terminal are formed on a P-channel semiconductor chip (P-MOS) 41. These semiconductor chips 40 and 41 are connected to each other. Bonding pads are provided. These interconnects are interconnected by metal wires 44.
(B) から明らかなように、 金属フレーム 4 2上に上記半導体チップ As is clear from (B), the above semiconductor chip is mounted on the metal frame 42.
40が半田等により接続され、 (A) のように中央部分からドレイン電 極が取り出される。 上記金属フレーム 42上に絶緣基板 4 3を設け、 そ の上に半導体チップ 4 1を搭載して絶縁分離する。 40 is connected by solder or the like, and the drain electrode is taken out from the center as shown in (A). An insulating substrate 43 is provided on the metal frame 42, and a semiconductor chip 41 is mounted thereon for insulation separation.
ハイブリツ ド I Cとしての入力端子 (ゲート電極) と上記ゲートパッ ド 4とは、 金属ワイヤ 45により接続され、 ハイプリッ ド I Cとしての ソース電極は、 上記金属ワイヤ 45により半導体チップ 4 0のソースバ ッ ド 5と接続される。 上記半導体チップ 40と 4 1は、 一体的に封止さ れて iつの半導体装置 (ハイプリッ ド I C) とされる。 The input terminal (gate electrode) as a hybrid IC is connected to the gate pad 4 by a metal wire 45, and the source electrode as a hybrid IC is connected to the source pad 5 of the semiconductor chip 40 by the metal wire 45. Connected. The semiconductor chips 40 and 41 are integrally sealed to form one semiconductor device (a hybrid IC).
第 7図には、 この発明に係る半導体装置の他の一実施例の回路図が示 されている。 同図には、 1つの縱型パワー MOSFET 1と、 その制御 回路としての電流検出回路 3及びゲ一ト切断回路 2が示されいてる。 そ れ故、 前記のように複数の縦型パワー MOSFETに分割して構成され る場合、 電流検出回路の分圧抵抗回路がゲート切断回路に対応して複数 個設けられる。 FIG. 7 is a circuit diagram showing another embodiment of the semiconductor device according to the present invention. FIG. 1 shows one vertical power MOSFET 1, a current detection circuit 3 and a gate cutting circuit 2 as a control circuit thereof. Therefore, in the case of being divided into a plurality of vertical power MOSFETs as described above, a plurality of voltage dividing resistance circuits of the current detection circuit are provided corresponding to the gate disconnection circuit.
この実施例では、 縦型パワー MOSFET 1のゲートとゲートパッ ド 4との間には、 横型の Nチャンネル型 MOSFET5が用いられる。 こ のように Nチャンネル型 MOSFETを用いる場合には、 前記第 3図に 示したような絶縁分離層 23を形成する必要がなく、 比較的簡単なプロ セスにより前記のようなゲー卜切断回路 2及び電流検出回路 3を含む縦 型パワー MOSFETをモノリショク I C化できる。 In this embodiment, a horizontal N-channel MOSFET 5 is used between the gate of the vertical power MOSFET 1 and the gate pad 4. When an N-channel MOSFET is used as described above, it is not necessary to form the insulating separation layer 23 as shown in FIG. 3, and the gate disconnection circuit 2 as described above can be formed by a relatively simple process. In addition, the vertical power MOSFET including the current detection circuit 3 can be made into a monolithic IC.
入力端子であるゲートパッ ド 4と縦型 MOSFET 1のゲー卜との間 に横型の Nチャンネル型 MOSFET5を用いた場合には、 かかる MO SFET5のしきレ、値電圧によりゲートパッ ドから入力される入力信号
が低下させられるのを防ぐ必要がある。 そのため、 かかる MOSFET 5のゲートに供給される制御電圧は、 チャージポンプ回路 53により電 源端子 52から供給された電源電圧が昇圧させられた電 Eとされる。 チャージポンプ回路は、 奇数個のインバー夕回路をリング状に接続し てなる発振回路と、 かかる発振回路で形成された発振パルスをキャパシ 夕とダイォ一ド又はダイォード形態の MOSFETにより整流して電源 電圧以上に高くされた電圧を形成するものである。 このような昇圧回路 は、 例えばダイナミック型 RAMのワード線選択電圧を形成する昇圧回 路等のように広く知られているものを利用することができる。 When a horizontal N-channel MOSFET 5 is used between the gate pad 4 as an input terminal and the gate of the vertical MOSFET 1, an input signal input from the gate pad is generated by the threshold voltage and the value voltage of the MOSFET 5. Must be prevented from being reduced. Therefore, the control voltage supplied to the gate of the MOSFET 5 is a voltage E obtained by boosting the power supply voltage supplied from the power supply terminal 52 by the charge pump circuit 53. The charge pump circuit is composed of an oscillating circuit in which an odd number of inverter circuits are connected in a ring shape, and the oscillating pulse formed by such an oscillating circuit is rectified by a capacitor and a diode or diode type MOSFET to supply voltage. This is for forming a voltage that is raised as described above. As such a booster circuit, a widely known circuit such as a booster circuit for forming a word line selection voltage of a dynamic RAM can be used.
電流検出回路は、 3つの抵抗 R 1〜R 3を直列接続して構成される。 抵抗 R 2と R 1と接続点から得られる低い分圧電圧は、 前段の MOSF ETのゲ一卜に伝えられる。 抵抗 R 3と R 2との接続点から得られる高 い分圧電圧は、 後段の MOSFETのゲートに伝えられる。 この後段の MOSFETのゲートとソースとの間に、 上記前段の MOSFETのド レインとソースがソース接続される。 The current detection circuit is configured by connecting three resistors R1 to R3 in series. The low divided voltage obtained from the connection point between the resistors R2 and R1 is transmitted to the gate of the MOSFET in the preceding stage. The high divided voltage obtained from the junction of resistors R3 and R2 is transmitted to the gate of the subsequent MOSFET. The drain and source of the preceding MOSFET are connected between the gate and source of the latter MOSFET.
上記後段の M〇 S F E Tのドレイン出力により、 特に制限されないが 、 上記チャージポンプ回路が起動される。 出力電流が零の近い微小電圧 のときには、 前段の MOSFETが低い分圧電圧がゲートに供給される 前段の MOSFETがオフ状態にされる。 それ故、 後段の MOSFET のゲートには比較的高い分圧電圧が供給されてオン状態にされる。 この 後段の MO S F ETのォン状態により、 発振回路の動作が停止させらて いる。 Although not particularly limited, the charge pump circuit is started by the drain output of the M〇S FET at the subsequent stage. When the output current is a very small voltage near zero, the preceding MOSFET is supplied with a low divided voltage to the gate, and the preceding MOSFET is turned off. Therefore, a relatively high divided voltage is supplied to the gate of the subsequent MOSFET to turn it on. The operation of the oscillation circuit is stopped by the ON state of the MOS FET at the subsequent stage.
出力電流が流れ出して、 上記前段の MO SFE Tがォン状態にされる と、 後段の MOSFETのゲート電 を低く下げてしまうので後段の M OSFETをオフ伏態にさせる。 この結果、 チャージポンプ回路が動作 を開始して、 MOSFET5のゲート電圧を高くし、 最終的にはゲート
パッド 4から与えられるハイレベルの入力電圧に対して、 MOSFET 5のしきい値電圧以上にする。 これにより、 ゲートパッ ド 4から供給さ れる入力信号がレベル損失なく、 上記縦型 MOSFET 1に伝えられて 、 そのスィッチ制御が行われる。 If the output current starts to flow and the MOSFET in the preceding stage is turned on, the gate voltage of the MOSFET in the subsequent stage will be lowered and the MOSFET in the latter stage will be turned off. As a result, the charge pump circuit starts operating, increasing the gate voltage of MOSFET5, and ultimately the gate voltage. For the high-level input voltage given from pad 4, make it higher than the threshold voltage of MOSFET 5. Thus, the input signal supplied from the gate pad 4 is transmitted to the vertical MOSFET 1 without any level loss, and the switch is controlled.
縦型 MOSFET 1が複数個に分割されて構成される場合、 上記分圧 抵抗回路により、 出力電流の増加に対応して、 それぞれの分圧電圧が上 記前段の MO S F E Tをォン状態にさせると、 後段の M〇 S F E Tがォ フ状態に切り換えられ、 それに対応したチヤ一ジポンプ回路が動作を開 始して上記 Nチヤンネル型のゲ一ト切断 MO S F E Tをォン伏態にさせ る。 チャージポンプ回路は、 複数のゲート切断用の MOSFETに対し て共通に用いるものであってもよい。 この場合、 上記チャージポンプ回 路により形成された昇圧電圧を動作電圧とし、 上記後段の MO SFET を駆動 MOSFETのドレインとの間に高抵抗値の負荷抵抗を設け、 上 記ゲ一ト切断用の M〇 SFE Tの制御信号を形成するようにすればよい 。 つまり、 上記後段の MOSFETのオフ状態により、 昇圧電圧が上記 負荷抵抗を介して上記ゲ一ト切断用の MOSFET 5のゲートに伝えら れて、 かかる MOSFET 5をオン状態にさせることができる。 In the case where the vertical MOSFET 1 is divided into a plurality of parts, each divided voltage turns on the preceding MOS FET in response to the increase of the output current by the voltage dividing resistor circuit. Then, the subsequent M〇SFET is switched to the off state, and the corresponding charge pump circuit starts operating to turn off the N-channel type gate cutting MO SFET. The charge pump circuit may be commonly used for a plurality of gate disconnecting MOSFETs. In this case, the boosted voltage formed by the charge pump circuit is used as the operating voltage, a high-resistance load resistance is provided between the latter MOSFET and the drain of the driving MOSFET, and the gate disconnection is performed. What is necessary is just to form the control signal of M〇SFET. In other words, the boosted voltage is transmitted to the gate of the gate disconnecting MOSFET 5 via the load resistor by the off-state of the latter-stage MOSFET, and the MOSFET 5 can be turned on.
第 8図には、 この発明に係る半導体装置の他の一実施例の回路図が示 されている。 この実施例では、 第 7図に示したチャージポンプ回路のよ うに独立した電源端子を設ける構成に代えて、 入力端子であるゲートパ ッド 4から動作電圧を与えるようにしたものである。 この構成では、 ゲ 一卜パッド 4にハイレベルの入力電圧が与えられたとき、 かかるハイレ ベルの入力電圧を動作電圧としてチャージボンプ回路が昇圧電圧を形成 する。 このため、 チャージポンプ回路の発振周波数は、 上記ゲートパッ ドがハイレベルのされる最小期間に対して十分高い周波数に設定され、 上記ゲ一卜パッド 4のハイレベルへの変化に応答して、 極短い時間内に
所定の昇圧電圧を形成するようにされる。 他の構成は、 前記第 7の実施 例と同様であるので、 その説明を省略する。 この構成では、 電源端子が 不用となり、 使い勝手のよいモノリシック I Cで構成されるパワー M〇 SFETを得ることができる。 FIG. 8 is a circuit diagram of another embodiment of the semiconductor device according to the present invention. In this embodiment, an operating voltage is supplied from the gate pad 4 which is an input terminal, instead of a configuration in which an independent power supply terminal is provided as in the charge pump circuit shown in FIG. In this configuration, when a high-level input voltage is applied to the gate pad 4, the charge pump circuit forms a boosted voltage using the high-level input voltage as an operating voltage. For this reason, the oscillation frequency of the charge pump circuit is set to a sufficiently high frequency for the minimum period during which the gate pad is set to the high level, and in response to the change of the gate pad 4 to the high level, Within a short time A predetermined boosted voltage is formed. The other configuration is the same as that of the seventh embodiment, and a description thereof will be omitted. This configuration eliminates the need for a power supply terminal, and provides a power M〇SFET composed of an easy-to-use monolithic IC.
上記分圧抵抗回路は、 前記第 2図に示したような回路とし、 かかる分 圧電圧を受ける 1つの Nチャンネル型 MOSFETにより、 上記チヤ一 ジポンプ回路の制御信号を形成するようにしてもよい。 つりま、 出力電 流の増大に対応して分圧電圧が上昇し、 上記 Nチャンネル型 M〇 SFE Tのオン状態により、 チャージボンプ回路が動作を開始して上記昇圧電 圧を形成するようにすればよい。 The voltage dividing resistance circuit may be a circuit as shown in FIG. 2, and a control signal for the charge pump circuit may be formed by one N-channel MOSFET receiving the divided voltage. In other words, the divided voltage rises in response to the increase in the output current, and the charge pump circuit starts operating to form the boosted voltage by the ON state of the N-channel M 型 SFET. do it.
上記第 7図及び第 8図に示された上記チャージポンプ回路は、 複数の 縦型パワー MOSFETのゲ一ト切断用 MOSFETに一対一に対応し て設ける構成としてもよい。 The charge pump circuits shown in FIGS. 7 and 8 may be provided in one-to-one correspondence with gate cutting MOSFETs of a plurality of vertical power MOSFETs.
第 9図には、 この発明に係る単位のパワー M〇 S F E Tの他の一実施 例を説明するための等価回路図が示されている。 この実施例では、 3έ型 パワー MOSFET 1に一対一に対応して電流検出回路 3とゲ一ト切断 回路 2とが設けられる。 このような縱型パワー MOSFET 1、 ゲート 切断回路 2及び電流検出回路 3は 1組の単位回路 (機能プロック) とさ れる。 FIG. 9 is an equivalent circuit diagram for explaining another embodiment of the unit power M〇S FET according to the present invention. In this embodiment, a current detection circuit 3 and a gate cutting circuit 2 are provided in one-to-one correspondence with the 3έ-type power MOSFET 1. Such a vertical power MOSFET 1, a gate disconnection circuit 2, and a current detection circuit 3 constitute a set of unit circuits (functional blocks).
上記のような単位回路は、 第 1 0図に示すように最大出力電流に対応 して N個の単位回路を 1つの半導体基板上に形成されて、 パワースィッ チ M 0 S F E Tを構成する。 機能ブロック 1ないし機能ブロック Nから なる N個の各回路は、 上記それぞれが上記単位回路から構成される。 た だし、 分圧抵抗 R 1 と R 2の抵抗比がそれぞれの機能プロック 1ないし Nで相互に異なるようにされており、 出力電流の増大に比例して並列接 続される機能ブロックの数が増加するようにされる。
上記のような単位回路を設計しておけば、 最大出力電流に対応して組 み合わせるだけで所望の最大出力電流を得ることができるパワースィッ チ MOSFETを簡単に製造することができる。 つまり、 最大出力電流 に対応して、 上記単位回路の数を選ぶだけで所望の最大出力電流を持つ パワー M〇 SFE Tを形成することができる。 In the unit circuit as described above, as shown in FIG. 10, N unit circuits corresponding to the maximum output current are formed on one semiconductor substrate to constitute a power switch M0SFET. Each of the N circuits composed of the functional blocks 1 to N is composed of the above unit circuits. However, the resistance ratios of the voltage dividing resistors R 1 and R 2 are different from each other in the respective function blocks 1 to N, and the number of function blocks connected in parallel in proportion to the increase in output current Let it increase. By designing the unit circuit as described above, it is possible to easily manufacture a power switch MOSFET that can obtain a desired maximum output current simply by combining it in accordance with the maximum output current. That is, a power M〇SFET having a desired maximum output current can be formed only by selecting the number of the unit circuits corresponding to the maximum output current.
第 1 1図には、 この発明に係る半導体装置の更に他の一実施例の回路 図が示されている。 この実施例では、 分圧抵抗が複数のゲート切断回路 2、 2' 及び 2" に対して共通に用いられる。 出力電流の増大に対応し てゲート切断回路 2、 2' 及び 2" の順で、 ゲート切断用の Pチャンネ ル型 MOSFETを順次段階的にオン状態にさせるために、 上記分圧電 圧を受ける Nチャンネル型 M OSFETのしきし、値電圧が順次に高くさ れる。 このようなしきい値電圧を高くする方法としては、 特に制限され なレ、が、 MOSFETのチャンネル領域に P型不純物をィォン打ち込み 技術により選択的に導入するもの、 あるいはゲート絶縁膜の膜圧を厚く 形成するもの、 あるいはゲート長を長くするもの、 及びこれらを組み合 わせるもの等種々の実施形態を採ることができる。 FIG. 11 is a circuit diagram of still another embodiment of the semiconductor device according to the present invention. In this embodiment, a voltage dividing resistor is commonly used for a plurality of gate disconnection circuits 2, 2 ', and 2 ". In response to an increase in output current, the gate disconnection circuits 2, 2', and 2" are used in this order. In order to sequentially turn on the P-channel MOSFET for gate disconnection in a stepwise manner, the threshold voltage of the N-channel MOSFET that receives the above-mentioned partial pressure is increased sequentially. Although there are no particular restrictions on such a method of increasing the threshold voltage, a method in which a P-type impurity is selectively introduced into the channel region of the MOSFET by ion implantation, or a method in which the film thickness of the gate insulating film is increased. Various embodiments can be adopted, such as those that are formed, those that increase the gate length, and those that combine these.
以上のような本発明に係る縱型ノ、'ヮ— MO S F E Tは、 前記のように 出力電流に応じて動作させられる縦型 MOSFETの数が増加させられ ることにより、 入力容量で消費させられる無効電力を低減させるという ように使うこと、 あるいは既存のスイッチング電源回路のシステム構成 の変更無しに、 上記低電流領域での損失を低減させるというように使う こと及び次のように高信頼性のスィツチ MOSFETとしても用いるこ とができる。 As described above, the vertical MOSFET and the MOSFET according to the present invention are consumed by the input capacitance by increasing the number of the vertical MOSFETs operated according to the output current as described above. Use to reduce the reactive power, or to reduce the loss in the above low current region without changing the system configuration of the existing switching power supply circuit, and to use a highly reliable switch as follows: It can also be used as a MOSFET.
前記のようなトランスやコイル等のインダク夕ンス性の負荷を駆動す るものでは、 逆起電圧により高い電圧が供給されて素子破壊が発生たり 、 パワー MOSFETはそもそもが比較的大きな出力電流を流すように
用いられることから、 一部の結晶欠陥があるとそこに電流が集中して素 子破壊が生たりすることが十分予測される。 このような場合でも、 この 実施例のパワー MOS F ETでは、 直ちにその機能が停止することがな い。 例えば、 低電流領域での動作中において、 動作中の 1つの MOSF ETが何らかの原因で破壊されて動作不能になると、 そのときに必要と される出力電流は上記電流検出用 MO S F E Tから供給されることとな り、 上記分圧電圧を高くするに作用するので、 直ちに中電流領域で動作 するような設けられた縦型パワー MOSFETのゲ一ト切断用の Pチヤ ンネル型 MO S F E Tをォン状態として以後の出力電流を形成する。 更 に出力電流が増加すれば、 もともとは大電流領域で動作するように設け られた縦型パワー MO SFE Tもオン状態となり、 上記必要な出力電流 を流すように働くものとなる。 In the case of driving an inductive load such as a transformer or a coil as described above, a high voltage is supplied due to the back electromotive force, which causes element destruction, or a power MOSFET originally flows a relatively large output current. like Because it is used, it is fully expected that if there are some crystal defects, the current will be concentrated there and element destruction will occur. Even in such a case, the function does not stop immediately in the power MOSFET of this embodiment. For example, during operation in the low current region, if one of the operating MOSFETs is destroyed for some reason and becomes inoperable, the output current required at that time is supplied from the current detection MOSFET described above. In other words, since this acts to increase the divided voltage, the P-channel MOSFET for gate disconnection of the vertical power MOSFET provided to operate immediately in the middle current region is turned on. To form a subsequent output current. If the output current further increases, the vertical power MOSFET that was originally provided to operate in the large current region will also be turned on, and will work to supply the required output current.
したがって、 自動車搭載用等のパワー MOSFETにおいて、 それが 動作不能になることにより、 重大な事故につながるような自動車の運転 制御不能を防止することができる。 言い換えるならば、 電子制御される メカニカルシステムの高信頼性を確保することができる。 Therefore, in a power MOSFET mounted on a vehicle or the like, the inoperability of the power MOSFET prevents a loss of vehicle driving control that could lead to a serious accident. In other words, high reliability of the electronically controlled mechanical system can be ensured.
上記の実施例から得られる作用効果は、 下記の通りである。 The operational effects obtained from the above embodiment are as follows.
(1) スィツチング機能を持つ半導体装置において、 出力電流を形成 するトランジスタを複数個に分割し、 出力電流のレベルに応じて動作す るトランジスタの数を順次に増加させる制御回路を設けることにより、 低出力電流領域では入力容量を減らしてスィッチング駆動するのに必要 な電力損失を低減させることができるという効果が得られる。 (1) In a semiconductor device having a switching function, a transistor that forms an output current is divided into a plurality of transistors, and a control circuit that sequentially increases the number of transistors that operate according to the level of the output current is provided. In the output current region, the effect is obtained that the power loss required for switching drive by reducing the input capacitance can be reduced.
(2) 1つの半導体基板又は 1つの実装基板上において、 ドレインと ソースがそれぞれ共通化された複数の出力 M〇 S F E Tと、 かかる出力 MOSFETのゲートと入力端子との間に挿入されたゲ一ト切断用の M OSFE Tを含む制御回路とを形成しておき、 上記制御回路により出力
電流の増加に対応してゲ一ト切断用の MOSFETをオン状態にさせて 、 入力端子から供給される入力信号をが伝えられる出力 MOSFETの 数を増加させることにより、 低出力電流領域では入力容量を減らしてス イツチング駆動するのに必要な電力損失を低減させることができるとい う効果が得られる。 (2) On one semiconductor substrate or one mounting substrate, a plurality of output M〇SFETs with a common drain and source, and a gate inserted between the gate and input terminal of the output MOSFET A control circuit including a MOSFET for disconnection is formed, and output is performed by the control circuit. The gate cutting MOSFET is turned on in response to the increase in current, and the number of output MOSFETs that can transmit the input signal supplied from the input terminal is increased. This leads to an effect that power loss required for switching driving can be reduced by reducing power consumption.
(3) 縦型パワー MOSFETを複数個に分割し、 それぞれのゲート と入力端子との間にゲート切断用の MOSFETを設けるとともに、 上 記入力端子にゲートが接綾され、 上記ドレインにそのドレィンが接続さ れてなる縦型の電流検出用の縦型 M〇 S F E T及び上記電流検出用縦型 MOSFETのソースに設けられ、 それに流れる電流に対応した電圧を 発生させる分圧抵抗回路及びかかる分圧電圧を受けて、 そのしきい値電 圧との相対的な関係により分圧電圧の上昇に対応して上記ゲート切断用 の M〇 S F E Tを段階的に順次にォン状態にさせる制御用 M〇 SFET とを設け、 出力電流の増加に対応してゲート切断用の MOSFETをォ ン状態にさせて、 動作させられる縦型パワー MOSFETの数を増加さ せることにより、 低出力電流領域では入力容量を減らしてスィッチング 駆動するのに必要な電力損失を低減させることができるという効果が得 られる。 (3) Divide the vertical power MOSFET into multiple parts, provide a gate disconnecting MOSFET between each gate and the input terminal, connect the gate to the input terminal, and connect the drain to the drain. A voltage dividing resistor circuit that is provided at the source of the connected vertical M〇 SFET for current detection and the vertical MOSFET for current detection, and generates a voltage corresponding to the current flowing therethrough, and the divided voltage In response to this, the control M〇SFET for turning on the gate disconnection M 切断 SFET in a stepwise manner in response to the rise of the divided voltage based on the relative relationship with the threshold voltage. In order to increase the number of vertical power MOSFETs that can be operated by turning on the MOSFET for gate disconnection in response to the increase in output current, the input capacitance is reduced in the low output current region. Driving There is an advantage that it is possible to reduce the power loss required for that.
( 4 ) 上記電流検出用の縦型 MO S F E Tを上記縦型パワー M〇 S F ETに比べて十分に小さく形成し、 そのサイズ比に対応した小さな検出 電流を得るようにすることにより、 高集積化を図りつつ、 出力電流を高 精度で検出することができるという効果が得られる。 (4) The vertical MO SFET for current detection is formed sufficiently smaller than the vertical power M〇SF ET, and a small detection current corresponding to the size ratio is obtained. Thus, it is possible to obtain an effect that the output current can be detected with high accuracy while achieving the above.
(5) 上記ゲート切断用の M〇 S F E Tを横型の Pチャンネル型 M〇 SFETとし、 そのゲートと上記ソースパッ ドとの間に上記分圧電圧を 受ける横型の Nチャンネル型 MOSFETから構成された制御用 M〇S FETを用いることにより、 制御回路が簡単な回路で構成できるという
効果が得られる。 (5) The M〇 SFET for gate disconnection is a horizontal P-channel M〇 SFET, and the control device is composed of a horizontal N-channel MOSFET that receives the divided voltage between its gate and the source pad. By using M〇S FET, the control circuit can be configured with a simple circuit The effect is obtained.
(6) 上記 Pチャンネル型 MOSFETを別チップにより構成し、 上 記縦型及び横型の Nチャンネル型 MOSFETが形成される半導体チッ プとともに 1つの実装基板に搭載させることにより、 縱型ノ、'ヮ一 M 0 S F E Tが搭載される半導体チップのプロセスの簡素化できるという効果 が得られる。 (6) The above-mentioned P-channel MOSFET is formed on a separate chip, and is mounted on a single mounting board together with the semiconductor chips on which the above-mentioned vertical and horizontal N-channel MOSFETs are formed. The effect of simplifying the process of the semiconductor chip on which one M 0 SFET is mounted can be obtained.
(7) 上記ゲート切断用の M 0 S F E Tを横型の Nチャンネル型 M 0 S F E Tにより構成し、 上記分圧電圧を受ける横型の Nチャンネル型 M 0 S F E Tから構成された制御用 M〇 S F E Tのドレイン出力によりチ ヤージポンプ回路で形成された昇圧電圧を上記ゲート切断用の MOSF ETのゲ一卜に伝えるようにすることにより、 全ての素子を Nチャンネ ル型 MOSFETにより構成でき、 モノリシック I C化された縦型パヮ -MO SFE Tのプロセスの簡素化ができるという効果が得られる。 (7) The M0 SFET for gate disconnection is composed of a horizontal N-channel M0 SFET, and the drain output of a control M〇SFET composed of the horizontal N-channel M0 SFET receiving the divided voltage By transmitting the boosted voltage formed by the charge pump circuit to the gate of the gate cutting MOSFET described above, all the elements can be configured with N-channel MOSFETs, and the vertical type is made into a monolithic IC. The effect of simplifying the process of power-MO SFET can be obtained.
(8) 上記分割された 1つの縱型パワー MOSFETに対して、 上記 電流検出用縱型 M〇SFET、 分圧抵抗回路、 上記ゲート切断用の MO(8) For the above one divided vertical power MOSFET, the vertical M〇SFET for current detection, the voltage dividing resistor circuit, and the MO for gate disconnection
S F E T、 制御用 M〇 SFETとが一対一に対応して設けて単位回路を 構成し、 複数の単位回路から半導体装置を構成することにより、 種々の 最大出力電流に対応した複数種類のパワー MOSFETを備えた半導体 装置を簡単に構成できるという効果が得られる。 SFETs and control M〇 SFETs are provided in a one-to-one correspondence to form a unit circuit, and by configuring a semiconductor device from multiple unit circuits, multiple types of power MOSFETs corresponding to various maximum output currents can be realized. The effect that the semiconductor device provided can be easily configured can be obtained.
以上本発明者よりなされた発明を実施例に基づき具体的に説明したが 、 本願発明は前記実施例に限定されるものではなく、 その要旨を逸脱し ない範囲で種々変更可能であることはいうまでもない。 例えば、 第 2図 において、 1つの縦型パワー MOSFETのゲートに、 ゲートパッ ド 4 を定常的に接続し、 常に 1つの縦型パワー MOSFETを動作させるよ うにしてもよい。 分割される縦型パワー MOSFETの数は、 上記のよ うに 3個、 4個等設ける構成としてもよい。 分割される縦型パワー MO
SFETの面積はそれぞれが互いに等しくさせる必要はない。 一般的に 広く使用される範囲で、 比較的細かく縦型ノ、'ヮ一 M 0 S F E Tを分割し 、 出力電流に対応して接続される縱型 MOSFETの数を頻繁に切り換 えて通常の電流使用領域での上記無効電力を効率よく削減するとともに 、 最大電流に対応した比較的大きな 1つの MOSFETを形成しておい て、 上記通常の電流使用領域を超えた出力電流時に上記大きな MOSF ETを動作させるようにする等、 種々の実施形態を採ることができるも のである。 また、 パワー素子及びその制御回路を構成する素子は、 MO SFETの他に、 バイポーラ型トランジスタを用いて構成するもの、 あ るいはバイポーラ型トランジスタと M〇 S F E Tとを組み合わせて構成 するものであってもよい。 産業上の利用可能性 Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, in FIG. 2, the gate pad 4 may be constantly connected to the gate of one vertical power MOSFET, so that one vertical power MOSFET always operates. The number of divided vertical power MOSFETs may be three, four, etc. as described above. Vertical power MO split The areas of the SFETs need not be equal to each other. In general, the vertical MOSFETs are divided relatively finely within the widely used range, and the number of vertical MOSFETs connected in accordance with the output current is switched frequently according to the output current, and the normal current is reduced. In addition to efficiently reducing the reactive power in the use area, a relatively large MOSFET corresponding to the maximum current is formed, and the large MOSFET operates when the output current exceeds the normal current use area. For example, various embodiments can be adopted. In addition, the elements constituting the power element and its control circuit are constituted by using a bipolar transistor in addition to the MOS SFET, or constituted by combining a bipolar transistor and an M〇SFET. Is also good. Industrial applicability
以上のように、 この発明は、 前記のような縱型パワー MOSFETを 含む半導体装置に広く利用することができる。
As described above, the present invention can be widely used for a semiconductor device including the above-described vertical power MOSFET.
Claims
1. スィッチング機能を持つ半導体装置において、 1. In a semiconductor device having a switching function,
出力電流を形成するトランジスタを複数個に分割し、 Dividing the transistor that forms the output current into multiple
出力電流のレベルに応じて動作するトランジスタの数を I頃次に増加 させる制御回路を設けてなることを特徴とする半導体装置。 A semiconductor device, comprising: a control circuit for increasing the number of transistors operating according to the level of an output current to about I.
2. ドレインとソースがそれぞれ共通化され、 複数に分割されてなる縱 型パワー MOSFETと、 2. A vertical power MOSFET with a common drain and source and divided into multiple
入力端子と上記複数の ¾έ型パワー MOSFETのゲートとの間にそ れぞれ設けられた複数からなるゲート切断用の MOSFETと、 A plurality of gate disconnection MOSFETs respectively provided between the input terminal and the gates of the plurality of ¾έ-type power MOSFETs;
上記入力端子にゲー卜が接続され、 上記ドレインにそのドレインが 接続されてなる縦型の電流検出用の縦型 MO S F Ε Τと、 A vertical current detection vertical MO S F Τ て having a gate connected to the input terminal and a drain connected to the drain,
上記電流検出用縱型 MOSFETのソースに設けられ、 それに流れ る電流に対応した電圧を発生させる分圧抵抗回路と、 A voltage-dividing resistor circuit that is provided at the source of the vertical MOSFET for current detection and generates a voltage corresponding to the current flowing therethrough;
上記分圧抵抗回路の分圧電圧を受けて、 かかる分圧電圧とそのしき レ、値電圧との相対的な関係により分圧電圧の上昇に対応して上記ゲート 切断用の M〇 S F E Tを段階的に順次にォン状態にさせるスィッチ制御 信号を形成する複数の制御用 M 0 S F E Tとを備えてなることを特徴と する半導体装置。 In response to the divided voltage of the voltage dividing resistor circuit, the M〇SFET for gate disconnection is stepped in response to the rise of the divided voltage according to the relative relationship between the divided voltage, the threshold, and the value voltage. A semiconductor device, comprising: a plurality of control M 0 SFETs for forming a switch control signal for sequentially and sequentially turning on.
3. 上記電流検出用の縱型 MOSFETは、 上記縦型パワー MOSFE Tに比べて十分に小さく形成され、 そのサイズ比に対応した小さな検出 電流を形成するものであることを特徴とする請求の範囲第 2項記載の半 導体装置。 3. The vertical MOSFET for current detection is formed sufficiently smaller than the vertical power MOSFET and forms a small detection current corresponding to the size ratio. The semiconductor device according to paragraph 2.
4. 上記ゲ一ト切断用の MOSFETは、 横型の Pチャンネル型 MOS FETから構成され、 そのゲートと上記ソースとの間に上記分圧電圧を 受ける横型の Nチャンネル型 MOSFETから構成された制御用 MOS
FETが設けられるものであることを特徴とする請求の範囲第 2項記載 の半導体装置。 4. The gate cutting MOSFET is composed of a horizontal P-channel MOSFET, and a control N-channel MOSFET that receives the divided voltage between its gate and the source. MOS 3. The semiconductor device according to claim 2, wherein a FET is provided.
5. 上記 Pチャンネル型 MOSFETと Nチャンネル型 MOSFETと は、 上記縦型 MO SFETとともに 1つの半導体基板上に形成されるも のであることを特徴とする請求の範囲第 4項記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the P-channel MOSFET and the N-channel MOSFET are formed on one semiconductor substrate together with the vertical MOSFET.
6. 上記 Pチャンネル型 MOSFETは、 別チップにより構成されてお り、 上記縱型及び横型の Nチャンネル型 MOSFETが形成される半導 体チップとともに 1つの実装基板に搭載されるものであることを特徴と する請求の範囲第 4項記載の半導体装置。 6. The P-channel MOSFET is composed of separate chips, and is mounted on a single mounting board together with the semiconductor chips on which the vertical and horizontal N-channel MOSFETs are formed. 5. The semiconductor device according to claim 4, wherein the semiconductor device is characterized in that:
7. 上記ゲート切断用の MOSFETは、 横型の Nチャンネル型 M〇S FETからなり、 上記分圧電圧を受ける横型の Nチャンネル型 MOSF ETから構成された制御用 MOSFETのドレイン出力によりチャージ ポンプ回路で形成された昇圧電圧が上記ゲ一ト切断用の M〇 S F E Tの ゲートに伝えられるものであることを特徴とする請求の範囲第 2項記載 の半導体装置。 7. The above MOSFET for gate disconnection is composed of a horizontal N-channel MOSFET, and the drain of a control MOSFET composed of a horizontal N-channel MOSFET receiving the divided voltage is used as a charge pump circuit. 3. The semiconductor device according to claim 2, wherein the formed boosted voltage is transmitted to the gate of the gate cutting M〇SFET.
8. 上記分割された 1つの縦型パワー MOSFETに対して、 上記電流 検出用縦型 MOSFET、 分圧抵抗回路、 上記ゲート切断用の MOSF E丁、 制御用 MO SFETとが一対一に対応して設けて単位回路を構成 し、 複数の単位回路から構成されるものであることを特徴とする請求の 範囲第 2項記載の半導体装置。 8. One vertical power MOSFET is divided into one vertical MOSFET for current detection, a voltage-dividing resistor circuit, one MOSFET for gate disconnection, and one MOSFET for control. 3. The semiconductor device according to claim 2, wherein the semiconductor device is provided to form a unit circuit, and is configured by a plurality of unit circuits.
9. 上記トランジスタは、 縦型パワー M〇S FETであり、 それぞれの ゲート電極が互いに分離されることにより上記複数個に分割されるもの であることを特徴とする請求の範囲第 1項記載の半導体装置。
9. The method according to claim 1, wherein the transistor is a vertical power MOSFET and is divided into the plurality by dividing each gate electrode from each other. Semiconductor device.
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PCT/JP1996/001425 WO1997045957A1 (en) | 1996-05-28 | 1996-05-28 | Semiconductor device |
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PCT/JP1996/001425 WO1997045957A1 (en) | 1996-05-28 | 1996-05-28 | Semiconductor device |
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WO2000062422A1 (en) * | 1999-04-13 | 2000-10-19 | Koninklijke Philips Electronics N.V. | A power switching circuit |
EP1143618A1 (en) * | 1999-09-20 | 2001-10-10 | Mitsubishi Denki Kabushiki Kaisha | Overcurrent control circuit of power semiconductor device |
JP2014187483A (en) * | 2013-03-22 | 2014-10-02 | Oki Electric Ind Co Ltd | Load drive circuit |
WO2018042881A1 (en) * | 2016-09-01 | 2018-03-08 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2000062422A1 (en) * | 1999-04-13 | 2000-10-19 | Koninklijke Philips Electronics N.V. | A power switching circuit |
EP1143618A1 (en) * | 1999-09-20 | 2001-10-10 | Mitsubishi Denki Kabushiki Kaisha | Overcurrent control circuit of power semiconductor device |
EP1143618A4 (en) * | 1999-09-20 | 2002-11-20 | Mitsubishi Electric Corp | Overcurrent control circuit of power semiconductor device |
US6633473B1 (en) | 1999-09-20 | 2003-10-14 | Mitsubishi Denki Kabushiki Kaisha | Overcurrent control circuit of power semiconductor device |
JP2014187483A (en) * | 2013-03-22 | 2014-10-02 | Oki Electric Ind Co Ltd | Load drive circuit |
WO2018042881A1 (en) * | 2016-09-01 | 2018-03-08 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
JP2018037932A (en) * | 2016-09-01 | 2018-03-08 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
US10763845B2 (en) | 2016-09-01 | 2020-09-01 | Hitachi Automotive Systems, Ltd. | Semiconductor device |
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