WO1997045957A1

WO1997045957A1 - Semiconductor device

Info

Publication number: WO1997045957A1
Application number: PCT/JP1996/001425
Authority: WO
Inventors: Atsushi Fujiki; Eiji Yanokura; Tetsuo Iijima; Kyoichi Takagawa; Masatoshi Nakasu
Original assignee: Hitachi, Ltd.; Hitachi Toubu Semiconductor, Ltd.
Priority date: 1996-05-28
Filing date: 1996-05-28
Publication date: 1997-12-04

Abstract

A plurality of output MOSFETs (1) whose drains and sources are made common and control circuits (2) containing MOSFETs (10) for cutting gates connected between the gates of the output MOSFETs (1) and the input terminals are formed on one semiconductor substrate or one mounting substrate. The number of the output MOSFETs (1) to which input signals from the input terminal are fed is increased by turning on the MOSFETs (10) by means of the control circuits (2) according to the increase of the output current.

Description

Description Semiconductor device technology

The present invention relates to a semiconductor device and, more particularly, to a technique effective for use in a vertical power MOS FET. Background art

As a technique for reducing the loss in the switching power supply circuit, switching M〇SFET drive frequency and switching, some are designed to switch the number of switch MO SFETs operated in parallel. No. 46 discloses this.

In the case of controlling the driving frequency of switching elements and the number of switching elements operated in parallel according to the output current as described above, it is necessary to provide a new control system for the entire switching power supply system. In other words, according to the above-mentioned Japanese Patent Application Laid-Open No. 7-59364, the load current generated on the secondary side of the transformer is detected by a load current detection circuit, and the reference current is compared with a reference voltage. It is necessary to provide a control system that changes the repetition frequency of the elements or switches the number of switching elements, which hinders the miniaturization of switching power supplies and, consequently, the reduction in cost. An object of the present invention is to provide a semiconductor device including a power MOSFET having a new function capable of switching a current supply capability according to the output current. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The present invention provides a plurality of output M〇SFETs having a common drain and source on one semiconductor substrate or one mounting substrate, and a gate inserted between the gate of the output MOSFET and the input terminal. A control circuit including an M 0 SFET for disconnection is formed, and the MOSFET for gate disconnection is turned on in response to an increase in output current by the above control circuit, so that an input signal supplied from an input terminal is provided. Increases the number of output MOSFETs transmitted. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an embodiment of the power MOSFET according to the present invention, FIG. 2 is an equivalent circuit diagram of the power MOSFET shown in FIG. 1, and FIG. FIG. 4 is a schematic cross-sectional view of the element structure of the power MOSFET shown in FIG. 1, FIG. 4 is a configuration diagram for explaining the parasitic capacitance of the power MOSFET, and FIG. FIG. 6 is an equivalent circuit diagram for explaining the parasitic capacitance of the SFET. FIG. 6 is a configuration diagram showing another embodiment of the power M〇SFET according to the present invention. FIG. FIG. 8 is an essential circuit equivalent circuit diagram showing another embodiment of the power MOSFET according to the present invention. FIG. 8 is an essential circuit equivalent circuit diagram showing another embodiment of the power MOSFET according to the present invention. FIG. 10 is an equivalent circuit diagram for explaining another embodiment of the unit power M〇SFET according to the present invention. FIG. 9 is a block diagram showing an embodiment of a power MOSFET configured using the power MOSFET of FIG. 9; FIG. 11 is an equivalent circuit showing still another embodiment of the power MOSFET according to the present invention; FIG. 12 shows a power MOSFET according to the present invention. FIG. 2 is a block diagram showing an embodiment of a switching power supply. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of one embodiment of a power MOSFET according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique. Each of the circuit blocks is drawn substantially in accordance with the actual geometric arrangement on the semiconductor substrate.

The power MOSFET of this embodiment is roughly composed of three vertical power MOSFETs 1 and a control circuit 7 therefor. The control circuit 7 includes a gate disconnection circuit 2, a current detection circuit 3, and a wiring 8 connecting these. The source of the vertical power MOSFET 1 is commonly connected to the source pad 5, and the drain is shared by the drain electrode 6 on the back surface. Then, the gate pad 4 as an input terminal is connected to the gate of the vertical power MOSFET 1 of 3 above via the gate cutting circuit 2. The current detection circuit 3 uses a vertical MOSFET in the form of a current mirror of the vertical power MOSFET, as described later, so that the gate is connected to the gate pad 4 and the drain is the semiconductor substrate itself. It is common and is connected to the back surface drain electrode.

FIG. 2 shows an equivalent circuit diagram of the power MOSFET shown in FIG. The drains of the three vertical power MOSFETs 1 and the drains of the vertical MOSFETs 14 constituting the current detection circuit 3 are commonly connected to a drain electrode 6. The sources of the three vertical power MOSFETs 1 are shared by the source pad 5. The current detection circuit 3 includes a vertical MOSFET 14 and a resistance circuit provided between a source of the MOSFET 14 and the source pad 5. The resistance circuit is composed of three voltage-dividing resistance circuits corresponding to the above-mentioned three vertical type MOSFETs. Although there is no particular limitation on each of the resistor circuits, each of the combined resistors has the same resistance value, and the source and drain currents of the vertical MOSFET 14 are divided into three equal parts. The current flowing through the vertical MOSFET 14 is divided into the respective voltage-dividing resistor circuits and flows equally, and a predetermined first current is obtained by a resistance ratio of the resistors 12 and 13 as shown in the example. Is formed. The other divided resistor circuits also have different resistance ratios and form different second and third divided voltages.

The gate cutting circuit 2 is composed of a lateral P-channel MOSFET 10 and a lateral N-channel MOSFET 11 as shown as an example. The P-channel MOSFET 10 is provided between the gate pad 4 as an input terminal and the gate of the vertical power MOSFET. The N-channel MOSFET 11 is provided between the gate of the P-channel MOSFET 10 and the source pad 5. The first divided voltage divided by the resistors 12 and 13 is supplied to the gate of the N-channel MOSFET 11.

Gate disconnection circuits 2 'and 2 "corresponding to other vertical power MOSFETs are also composed of a combination of horizontal P-channel MOSFETs and horizontal N-channel MOSFETs as described above. The gate of the MOSFET is supplied with the second and third divided voltages formed by the above-mentioned voltage dividing resistor circuit.

FIG. 3 is a cross-sectional view of a main element structure of a semiconductor device according to the present invention. In the figure, the above-mentioned one vertical power MOSFET 1, two horizontal MOSFETs composing the gate disconnection circuit 2 and the current detection circuit The vertical MOSFET and the resistor 21 constituting 3 are shown.

In this embodiment, although not particularly limited, an epitaxial layer 25 made of N— is formed on a semiconductor substrate 26 made of N +, and each semiconductor layer for constituting each of the following elements is formed on the epitaxial layer 24. It is formed. In the vertical power MOSFET 1, the epitaxy layer 25 constitutes a drain region together with the substrate layer 26, as shown by way of example, a part of the source, the drain and the gate as a representative. The thin film electrode 27 is used as the drain terminal 6. The P + diffusion layer formed on the surface of the epitaxial layer 25 is a channel region, and the N + diffusion layer formed on the P + diffusion layer is a source region. The P + diffusion layer as the channel and the N + diffusion layer as the source are commonly connected by an electrode of aluminum or the like to serve as a source terminal 5. The gate electrode is made of polysilicon (Poly-Si) 20 and is located on the channel region of the P + diffusion layer. The thin gate insulating film is used to form the N + diffusion layer as a source and a drain. It is formed so as to straddle the layer 25. One end of the gate electrode 20 is extended to the gate cutting circuit 2 and is also used as a part of a wiring between the gate electrode 20 and the gate cutting circuit 2.

The gate cutting circuit 2 includes a P-type insulating separation layer 23 formed on the above-mentioned epitaxial layer 25, and an N-cell (WELL) region 24 for forming a lateral P-channel MOSFET. Is formed. In the remaining portion of the epitaxial layer 25, a P-type well region 24 for forming a lateral N-channel MOSFET is formed. In the lateral P-channel MOSFET, a P + type source and drain are formed in the metal layer 24, and a gate electrode is formed so as to straddle the source-drain. Although not particularly limited, the source and drain connected to the vertical power MOSFET side for higher breakdown voltage, etc. In the W region, a P-type diffusion layer is formed, and the gate electrode is formed such that the P- layer becomes a substantial source and drain region.

The gate electrode of the vertical power MOSFET is connected to the source and drain of the horizontal P-channel MOSFET by a wiring layer such as aluminum.

05 Connected to constituent P + layer. An N + layer is formed adjacent to the other P + layer constituting the source and drain to obtain a good ohmic contact with the N− type cell region 24, and is formed by a wiring means such as aluminum. Commonly connected and connected to gate terminal 1. The lateral N-channel MOSFET described above has N +

A 10-type source and drain are formed, and a gate electrode is formed so as to straddle the source-drain. Although there is no particular limitation, N-type diffusion layers are formed in the source and drain regions connected to the gate of the lateral P-channel MOSFET to increase the breakdown voltage and the like. The gate electrode is formed so as to be the source and drain regions. the above

15 On the N + layer that constitutes the other source and drain of the lateral N-channel MOSFET, a P + layer is formed adjacent to the N-type MOSFET to obtain good uniform contact with the P-type transistor region 24. And is connected to the source terminal 5 by the wiring means such as. The vertical MO S F E T constituting the current detection circuit 3 is

It has the same structure as 20 SFET 1. However, although not clarified in the figure, the area of the source and drain of the vertical MOSFET for current detection is greatly reduced with respect to the area of the vertical power MOSFET 1 described above. Only a small current in accordance with Although not particularly limited, 1Z10 of the total output current of the vertical power MOSFET 1

The current of 2500 is set to flow through the vertical MOSFET for current detection. Since the gate of the vertical MOSFET is connected to the gate terminal 1 and the drain is shared by the substrate layer 26, the vertical MOSFET 1 is in a current mirror form. The source of the vertical MOSFET for current detection is connected to one end of a polysilicon resistor 21 by wiring means such as aluminum, and the other end of the polysilicon resistor 21 is connected to the source terminal 5. Wiring for obtaining a divided voltage is provided from the middle part, and is connected to the gate of the lateral N-channel MOSFET. Thereby, a semiconductor device as shown in the equivalent circuit of FIG. 2 can be obtained.

FIG. 4 is a configuration diagram for explaining the parasitic capacitance in the vertical power MOSFET as described above. As shown in the equivalent circuit in (A), the parasitic capacitances of the gate and source capacitance CGS, gate and drain capacitance CGD, and the drain and source capacitance CDS are as shown in the cross-sectional view of FIG. Become.

Gate-source capacitance CGS is the capacitance between the source electrode 5 made of aluminum or the like and the gate electrode made of a polysilicon layer.

The drain-source capacitance CGD is a parasitic capacitance having a gate insulating film formed under the gate electrode and a depletion layer formed in the channel region as a dielectric.

Gate-drain capacitance CDS is a parasitic capacitance that uses the depletion layer between the source and drain regions as a dielectric.

Vertical power MOSFETs such as those described above are sized to have a large current supply capability. Therefore, each of the above parasitic capacitances has a large capacitance value that cannot be ignored. Therefore, when used as a switching element in a switching power supply circuit, the charge / discharge current for this parasitic capacitance causes an increase in loss. Switching power supply circuits are rarely used at 100% load. In other words, the current supply capacity is designed to have a margin so that the load becomes 100% under the worst condition. For this reason, in a normal use mode, the operation is performed at a low load, and when the load current is small, the output current of the switch element is correspondingly reduced. However, the current for constantly charging / discharging the parasitic capacitance to drive such a switch element is constant irrespective of the output current. The problem of lowering the DC-DC conversion efficiency occurs.

In this embodiment, as described above, a gate disconnection circuit is provided between the gate of each vertical power MOSFET and the input terminal, and the P-channel M 0 SFET constituting such a gate disconnection circuit is turned off. In the state, as shown in the equivalent circuit diagram of FIG. 5, between the gate terminal 4 which is a human-powered terminal and the gate of the vertical power MOSFET 1, there is a connection between the source and the drain of the P-channel MOSFET. Parasitic capacitance Coss is inserted in series. This parasitic capacitance Coss is much smaller than the input capacitance CGS + CGD of the power MOSFET, and the input capacitance CGS + CGD can be made invisible from the input terminal 4.

That is, in the equivalent circuit of FIG. 2, when the output current of the drain electrode 6 is zero, the current flowing through the vertical MOSFET 14 is also zero, so that the divided voltage formed by the voltage dividing resistor circuit is The horizontal N-channel MOSFET is turned off to make it equal to the potential, and the horizontal P-channel MOSFET is turned off correspondingly. Therefore, when viewed from the gate pad 4, only the input capacitance such as the gate capacitance of the vertical M〇SF ET 14 formed so small that only 1/1000 of the current of the vertical power MOSFET 1 flows can be seen. So, even if the input terminal Even when a high-level / low-level control signal is supplied to a certain gate pad 4, the current consumed there is extremely small, and only a current is generated.

At the time of startup when the output current starts to flow, the current is supplied from the vertical MOS FET 14 for current detection. When this current flows into the resistor circuit and the divided voltage generated by the resistors 12 and 13 reaches the threshold voltage of the lateral N-channel MOSFET 11, the MOSFET 11 is turned on, A reference voltage (low level) corresponding to source pad 5 is supplied to the gate of horizontal P-channel MOSFET 10. As a result, the horizontal P-channel MOSFET 10 is turned on, and the input signal supplied from the gate pad 4 as the input terminal is transmitted to the vertical power MOSFET gate, and the vertical power MOSFET Supplies the output current.

Thereafter, in the low current region, the output current is supplied through the vertical power MOSFET, and a detection current corresponding to the size ratio between the vertical power MOSFET 1 and the vertical MOS FET 14 for current detection flows. The lateral MOS FET 11 is turned on by the divided voltage generated in the resistors 12 and 13 by the current, and the on state of the lateral MOSFET 10 is maintained.

In the middle current region where the output current further increases, the current flowing through the vertical MOSFET 14 for current detection increases, and the second divided voltage generated in the resistor circuit increases accordingly, and the gate is disconnected. The lateral MOS FET corresponding to the circuit 2 'is turned on, and as a result, two vertical MOSFETs are connected in parallel, and the output current in the medium current region is covered.

In the large current region where the output current further increases, the current flowing through the vertical MOSFET 14 for current detection further increases and is generated in the resistor circuit accordingly. The third divided voltage rises, and the horizontal M 0 SFET corresponding to the gate disconnection circuit 2 "is turned on. As a result, all three vertical power MO SFETs are connected in parallel, and It covers the output current in the large current region.

As described above, the number of vertical power MOSFETs connected in parallel automatically increases in response to the required output current. This means that the parasitic capacitance of the vertical power MOSFET changes in accordance with the output current, and the charge and discharge current consumed for the switch control changes in accordance with the output current, minimizing the loss. Can be suppressed.

FIG. 12 is a block diagram showing one embodiment of a switching power supply circuit to which the vertical power MOSFET according to the present invention is applied. In this switching power supply circuit, the primary coil of the transformer 62 is driven by the switching element 61 according to the present invention, and the rectifier diode 63 and the power smoothing capacitor 64 are connected to the secondary coil of the transformer 62. The output voltage Vout is detected by an output voltage monitoring circuit, and a control voltage corresponding to a difference between the output voltage Vout and a desired voltage is formed, so that the output voltage Vout becomes a desired voltage. (Pulse width modulation) The duty of the pulse supplied to the switch element 61 is adjusted by the control circuit.

In such a switching power supply circuit, the switch element 61 itself includes a current detection circuit and a gate disconnection circuit, and is connected in parallel according to a current required to drive a load. The number of power MOSFETs is switched. Therefore, as a switching power supply circuit, it is possible to obtain a switching power supply circuit in which loss in a low current region is significantly reduced without adding a special control system. As a result, the number of circuit elements constituting the switching power supply circuit can be reduced, so that the number of assembling steps can be reduced and the size and size of the mounting board can be reduced. In the case where a current detection circuit and a gate disconnection circuit are added to the switching element itself as described above, it is simple to replace the switching element part of the existing switching power supply circuit with the semiconductor device according to the present invention as described above. With such a configuration, the DC-DC conversion efficiency in the low current region can be greatly improved. In other words, the control system in an existing switching power supply circuit can easily improve efficiency at low current as described above.

FIG. 6 is a configuration diagram of another embodiment of the semiconductor device according to the present invention. FIG. 2A shows a plan view thereof, and FIG. 2B shows a corresponding cross-sectional view. In this embodiment, the horizontal P-channel type MOSFET included in the gate cutting circuit shown in FIG. 2 is constituted by a semiconductor device of another chip. In other words, the semiconductor device of this embodiment includes a semiconductor chip composed of an N-channel vertical MOSFET and a horizontal MOSFET, a semiconductor chip composed of a P-channel lateral MOSFET and a hybrid IC. Be composed.

The reason for this is that in order to form a P-channel type M〇 SFET on one semiconductor substrate as in the above embodiment, it is necessary to form an isolation region for element isolation, which complicates the process. . Therefore, the wafer process is simplified by using such a P-channel type MOSFET as a separate chip.

In (Α), the vertical power MOSFET 1, current detection circuit 3, and horizontal Ν-channel MOSFET divided into three as described above are formed on a Ν-channel semiconductor chip (Ν-MΝSIC) 40. You. The horizontal Ρ-channel MOSFET and the gate pad 4 as an input terminal are formed on a P-channel semiconductor chip (P-MOS) 41. These semiconductor chips 40 and 41 are connected to each other. Bonding pads are provided. These interconnects are interconnected by metal wires 44.

As is clear from (B), the above semiconductor chip is mounted on the metal frame 42.

40 is connected by solder or the like, and the drain electrode is taken out from the center as shown in (A). An insulating substrate 43 is provided on the metal frame 42, and a semiconductor chip 41 is mounted thereon for insulation separation.

The input terminal (gate electrode) as a hybrid IC is connected to the gate pad 4 by a metal wire 45, and the source electrode as a hybrid IC is connected to the source pad 5 of the semiconductor chip 40 by the metal wire 45. Connected. The semiconductor chips 40 and 41 are integrally sealed to form one semiconductor device (a hybrid IC).

FIG. 7 is a circuit diagram showing another embodiment of the semiconductor device according to the present invention. FIG. 1 shows one vertical power MOSFET 1, a current detection circuit 3 and a gate cutting circuit 2 as a control circuit thereof. Therefore, in the case of being divided into a plurality of vertical power MOSFETs as described above, a plurality of voltage dividing resistance circuits of the current detection circuit are provided corresponding to the gate disconnection circuit.

In this embodiment, a horizontal N-channel MOSFET 5 is used between the gate of the vertical power MOSFET 1 and the gate pad 4. When an N-channel MOSFET is used as described above, it is not necessary to form the insulating separation layer 23 as shown in FIG. 3, and the gate disconnection circuit 2 as described above can be formed by a relatively simple process. In addition, the vertical power MOSFET including the current detection circuit 3 can be made into a monolithic IC.

When a horizontal N-channel MOSFET 5 is used between the gate pad 4 as an input terminal and the gate of the vertical MOSFET 1, an input signal input from the gate pad is generated by the threshold voltage and the value voltage of the MOSFET 5. Must be prevented from being reduced. Therefore, the control voltage supplied to the gate of the MOSFET 5 is a voltage E obtained by boosting the power supply voltage supplied from the power supply terminal 52 by the charge pump circuit 53. The charge pump circuit is composed of an oscillating circuit in which an odd number of inverter circuits are connected in a ring shape, and the oscillating pulse formed by such an oscillating circuit is rectified by a capacitor and a diode or diode type MOSFET to supply voltage. This is for forming a voltage that is raised as described above. As such a booster circuit, a widely known circuit such as a booster circuit for forming a word line selection voltage of a dynamic RAM can be used.

The current detection circuit is configured by connecting three resistors R1 to R3 in series. The low divided voltage obtained from the connection point between the resistors R2 and R1 is transmitted to the gate of the MOSFET in the preceding stage. The high divided voltage obtained from the junction of resistors R3 and R2 is transmitted to the gate of the subsequent MOSFET. The drain and source of the preceding MOSFET are connected between the gate and source of the latter MOSFET.

Although not particularly limited, the charge pump circuit is started by the drain output of the M〇S FET at the subsequent stage. When the output current is a very small voltage near zero, the preceding MOSFET is supplied with a low divided voltage to the gate, and the preceding MOSFET is turned off. Therefore, a relatively high divided voltage is supplied to the gate of the subsequent MOSFET to turn it on. The operation of the oscillation circuit is stopped by the ON state of the MOS FET at the subsequent stage.

If the output current starts to flow and the MOSFET in the preceding stage is turned on, the gate voltage of the MOSFET in the subsequent stage will be lowered and the MOSFET in the latter stage will be turned off. As a result, the charge pump circuit starts operating, increasing the gate voltage of MOSFET5, and ultimately the gate voltage. For the high-level input voltage given from pad 4, make it higher than the threshold voltage of MOSFET 5. Thus, the input signal supplied from the gate pad 4 is transmitted to the vertical MOSFET 1 without any level loss, and the switch is controlled.

In the case where the vertical MOSFET 1 is divided into a plurality of parts, each divided voltage turns on the preceding MOS FET in response to the increase of the output current by the voltage dividing resistor circuit. Then, the subsequent M〇SFET is switched to the off state, and the corresponding charge pump circuit starts operating to turn off the N-channel type gate cutting MO SFET. The charge pump circuit may be commonly used for a plurality of gate disconnecting MOSFETs. In this case, the boosted voltage formed by the charge pump circuit is used as the operating voltage, a high-resistance load resistance is provided between the latter MOSFET and the drain of the driving MOSFET, and the gate disconnection is performed. What is necessary is just to form the control signal of M〇SFET. In other words, the boosted voltage is transmitted to the gate of the gate disconnecting MOSFET 5 via the load resistor by the off-state of the latter-stage MOSFET, and the MOSFET 5 can be turned on.

FIG. 8 is a circuit diagram of another embodiment of the semiconductor device according to the present invention. In this embodiment, an operating voltage is supplied from the gate pad 4 which is an input terminal, instead of a configuration in which an independent power supply terminal is provided as in the charge pump circuit shown in FIG. In this configuration, when a high-level input voltage is applied to the gate pad 4, the charge pump circuit forms a boosted voltage using the high-level input voltage as an operating voltage. For this reason, the oscillation frequency of the charge pump circuit is set to a sufficiently high frequency for the minimum period during which the gate pad is set to the high level, and in response to the change of the gate pad 4 to the high level, Within a short time A predetermined boosted voltage is formed. The other configuration is the same as that of the seventh embodiment, and a description thereof will be omitted. This configuration eliminates the need for a power supply terminal, and provides a power M〇SFET composed of an easy-to-use monolithic IC.

The voltage dividing resistance circuit may be a circuit as shown in FIG. 2, and a control signal for the charge pump circuit may be formed by one N-channel MOSFET receiving the divided voltage. In other words, the divided voltage rises in response to the increase in the output current, and the charge pump circuit starts operating to form the boosted voltage by the ON state of the N-channel M 型 SFET. do it.

The charge pump circuits shown in FIGS. 7 and 8 may be provided in one-to-one correspondence with gate cutting MOSFETs of a plurality of vertical power MOSFETs.

FIG. 9 is an equivalent circuit diagram for explaining another embodiment of the unit power M〇S FET according to the present invention. In this embodiment, a current detection circuit 3 and a gate cutting circuit 2 are provided in one-to-one correspondence with the 3έ-type power MOSFET 1. Such a vertical power MOSFET 1, a gate disconnection circuit 2, and a current detection circuit 3 constitute a set of unit circuits (functional blocks).

In the unit circuit as described above, as shown in FIG. 10, N unit circuits corresponding to the maximum output current are formed on one semiconductor substrate to constitute a power switch M0SFET. Each of the N circuits composed of the functional blocks 1 to N is composed of the above unit circuits. However, the resistance ratios of the voltage dividing resistors R 1 and R 2 are different from each other in the respective function blocks 1 to N, and the number of function blocks connected in parallel in proportion to the increase in output current Let it increase. By designing the unit circuit as described above, it is possible to easily manufacture a power switch MOSFET that can obtain a desired maximum output current simply by combining it in accordance with the maximum output current. That is, a power M〇SFET having a desired maximum output current can be formed only by selecting the number of the unit circuits corresponding to the maximum output current.

FIG. 11 is a circuit diagram of still another embodiment of the semiconductor device according to the present invention. In this embodiment, a voltage dividing resistor is commonly used for a plurality of gate disconnection circuits 2, 2 ', and 2 ". In response to an increase in output current, the gate disconnection circuits 2, 2', and 2" are used in this order. In order to sequentially turn on the P-channel MOSFET for gate disconnection in a stepwise manner, the threshold voltage of the N-channel MOSFET that receives the above-mentioned partial pressure is increased sequentially. Although there are no particular restrictions on such a method of increasing the threshold voltage, a method in which a P-type impurity is selectively introduced into the channel region of the MOSFET by ion implantation, or a method in which the film thickness of the gate insulating film is increased. Various embodiments can be adopted, such as those that are formed, those that increase the gate length, and those that combine these.

As described above, the vertical MOSFET and the MOSFET according to the present invention are consumed by the input capacitance by increasing the number of the vertical MOSFETs operated according to the output current as described above. Use to reduce the reactive power, or to reduce the loss in the above low current region without changing the system configuration of the existing switching power supply circuit, and to use a highly reliable switch as follows: It can also be used as a MOSFET.

In the case of driving an inductive load such as a transformer or a coil as described above, a high voltage is supplied due to the back electromotive force, which causes element destruction, or a power MOSFET originally flows a relatively large output current. like Because it is used, it is fully expected that if there are some crystal defects, the current will be concentrated there and element destruction will occur. Even in such a case, the function does not stop immediately in the power MOSFET of this embodiment. For example, during operation in the low current region, if one of the operating MOSFETs is destroyed for some reason and becomes inoperable, the output current required at that time is supplied from the current detection MOSFET described above. In other words, since this acts to increase the divided voltage, the P-channel MOSFET for gate disconnection of the vertical power MOSFET provided to operate immediately in the middle current region is turned on. To form a subsequent output current. If the output current further increases, the vertical power MOSFET that was originally provided to operate in the large current region will also be turned on, and will work to supply the required output current.

Therefore, in a power MOSFET mounted on a vehicle or the like, the inoperability of the power MOSFET prevents a loss of vehicle driving control that could lead to a serious accident. In other words, high reliability of the electronically controlled mechanical system can be ensured.

The operational effects obtained from the above embodiment are as follows.

(1) In a semiconductor device having a switching function, a transistor that forms an output current is divided into a plurality of transistors, and a control circuit that sequentially increases the number of transistors that operate according to the level of the output current is provided. In the output current region, the effect is obtained that the power loss required for switching drive by reducing the input capacitance can be reduced.

(2) On one semiconductor substrate or one mounting substrate, a plurality of output M〇SFETs with a common drain and source, and a gate inserted between the gate and input terminal of the output MOSFET A control circuit including a MOSFET for disconnection is formed, and output is performed by the control circuit. The gate cutting MOSFET is turned on in response to the increase in current, and the number of output MOSFETs that can transmit the input signal supplied from the input terminal is increased. This leads to an effect that power loss required for switching driving can be reduced by reducing power consumption.

(3) Divide the vertical power MOSFET into multiple parts, provide a gate disconnecting MOSFET between each gate and the input terminal, connect the gate to the input terminal, and connect the drain to the drain. A voltage dividing resistor circuit that is provided at the source of the connected vertical M〇 SFET for current detection and the vertical MOSFET for current detection, and generates a voltage corresponding to the current flowing therethrough, and the divided voltage In response to this, the control M〇SFET for turning on the gate disconnection M 切断 SFET in a stepwise manner in response to the rise of the divided voltage based on the relative relationship with the threshold voltage. In order to increase the number of vertical power MOSFETs that can be operated by turning on the MOSFET for gate disconnection in response to the increase in output current, the input capacitance is reduced in the low output current region. Driving There is an advantage that it is possible to reduce the power loss required for that.

(4) The vertical MO SFET for current detection is formed sufficiently smaller than the vertical power M〇SF ET, and a small detection current corresponding to the size ratio is obtained. Thus, it is possible to obtain an effect that the output current can be detected with high accuracy while achieving the above.

(5) The M〇 SFET for gate disconnection is a horizontal P-channel M〇 SFET, and the control device is composed of a horizontal N-channel MOSFET that receives the divided voltage between its gate and the source pad. By using M〇S FET, the control circuit can be configured with a simple circuit The effect is obtained.

(6) The above-mentioned P-channel MOSFET is formed on a separate chip, and is mounted on a single mounting board together with the semiconductor chips on which the above-mentioned vertical and horizontal N-channel MOSFETs are formed. The effect of simplifying the process of the semiconductor chip on which one M 0 SFET is mounted can be obtained.

(7) The M0 SFET for gate disconnection is composed of a horizontal N-channel M0 SFET, and the drain output of a control M〇SFET composed of the horizontal N-channel M0 SFET receiving the divided voltage By transmitting the boosted voltage formed by the charge pump circuit to the gate of the gate cutting MOSFET described above, all the elements can be configured with N-channel MOSFETs, and the vertical type is made into a monolithic IC. The effect of simplifying the process of power-MO SFET can be obtained.

(8) For the above one divided vertical power MOSFET, the vertical M〇SFET for current detection, the voltage dividing resistor circuit, and the MO for gate disconnection

SFETs and control M〇 SFETs are provided in a one-to-one correspondence to form a unit circuit, and by configuring a semiconductor device from multiple unit circuits, multiple types of power MOSFETs corresponding to various maximum output currents can be realized. The effect that the semiconductor device provided can be easily configured can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, in FIG. 2, the gate pad 4 may be constantly connected to the gate of one vertical power MOSFET, so that one vertical power MOSFET always operates. The number of divided vertical power MOSFETs may be three, four, etc. as described above. Vertical power MO split The areas of the SFETs need not be equal to each other. In general, the vertical MOSFETs are divided relatively finely within the widely used range, and the number of vertical MOSFETs connected in accordance with the output current is switched frequently according to the output current, and the normal current is reduced. In addition to efficiently reducing the reactive power in the use area, a relatively large MOSFET corresponding to the maximum current is formed, and the large MOSFET operates when the output current exceeds the normal current use area. For example, various embodiments can be adopted. In addition, the elements constituting the power element and its control circuit are constituted by using a bipolar transistor in addition to the MOS SFET, or constituted by combining a bipolar transistor and an M〇SFET. Is also good. Industrial applicability

As described above, the present invention can be widely used for a semiconductor device including the above-described vertical power MOSFET.

Claims

The scope of the claims

1. In a semiconductor device having a switching function,

Dividing the transistor that forms the output current into multiple

A semiconductor device, comprising: a control circuit for increasing the number of transistors operating according to the level of an output current to about I.

2. A vertical power MOSFET with a common drain and source and divided into multiple

A plurality of gate disconnection MOSFETs respectively provided between the input terminal and the gates of the plurality of ¾έ-type power MOSFETs;

A vertical current detection vertical MO S F Τ て having a gate connected to the input terminal and a drain connected to the drain,

A voltage-dividing resistor circuit that is provided at the source of the vertical MOSFET for current detection and generates a voltage corresponding to the current flowing therethrough;

In response to the divided voltage of the voltage dividing resistor circuit, the M〇SFET for gate disconnection is stepped in response to the rise of the divided voltage according to the relative relationship between the divided voltage, the threshold, and the value voltage. A semiconductor device, comprising: a plurality of control M 0 SFETs for forming a switch control signal for sequentially and sequentially turning on.

3. The vertical MOSFET for current detection is formed sufficiently smaller than the vertical power MOSFET and forms a small detection current corresponding to the size ratio. The semiconductor device according to paragraph 2.

4. The gate cutting MOSFET is composed of a horizontal P-channel MOSFET, and a control N-channel MOSFET that receives the divided voltage between its gate and the source. MOS 3. The semiconductor device according to claim 2, wherein a FET is provided.

5. The semiconductor device according to claim 4, wherein the P-channel MOSFET and the N-channel MOSFET are formed on one semiconductor substrate together with the vertical MOSFET.

6. The P-channel MOSFET is composed of separate chips, and is mounted on a single mounting board together with the semiconductor chips on which the vertical and horizontal N-channel MOSFETs are formed. 5. The semiconductor device according to claim 4, wherein the semiconductor device is characterized in that:

7. The above MOSFET for gate disconnection is composed of a horizontal N-channel MOSFET, and the drain of a control MOSFET composed of a horizontal N-channel MOSFET receiving the divided voltage is used as a charge pump circuit. 3. The semiconductor device according to claim 2, wherein the formed boosted voltage is transmitted to the gate of the gate cutting M〇SFET.

8. One vertical power MOSFET is divided into one vertical MOSFET for current detection, a voltage-dividing resistor circuit, one MOSFET for gate disconnection, and one MOSFET for control. 3. The semiconductor device according to claim 2, wherein the semiconductor device is provided to form a unit circuit, and is configured by a plurality of unit circuits.

9. The method according to claim 1, wherein the transistor is a vertical power MOSFET and is divided into the plurality by dividing each gate electrode from each other. Semiconductor device.