JP4600180B2 - Semiconductor circuit using field effect type power semiconductor element - Google Patents

Semiconductor circuit using field effect type power semiconductor element Download PDF

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JP4600180B2
JP4600180B2 JP2005185898A JP2005185898A JP4600180B2 JP 4600180 B2 JP4600180 B2 JP 4600180B2 JP 2005185898 A JP2005185898 A JP 2005185898A JP 2005185898 A JP2005185898 A JP 2005185898A JP 4600180 B2 JP4600180 B2 JP 4600180B2
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voltage
terminal
semiconductor element
power semiconductor
low
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JP2007006658A (en
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光造 坂本
篤雄 渡辺
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株式会社日立製作所
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The present invention relates to a preferred semiconductor circuits in the field effect power semiconductor device or an electrostatic induction type transistor normally characteristic or threshold voltage has a low normally-off characteristic.

  Wide band gap semiconductor elements such as SiC (silicon carbide), GaN (gallium nitride), and diamond on semiconductor substrates have excellent characteristics as power semiconductor elements, but are typical semiconductor elements using these wide band gap semiconductor elements. Some JFETs (junction FETs), SITs (electrostatic induction transistors), MESFETs (Metal-Semiconductor-Field-Effect-Transistors), HFETs (Heterojunction Field Effect Transistors), and HEMTs (High Electron Mobility Transistors) And storage FETs, etc., are semiconductor elements having normally-on characteristics in which current flows when the gate voltage is zero, or semiconductor elements having a low threshold voltage, so that the power semiconductor element can be reliably turned off by the control circuit. A power supply circuit for negative gate voltage is required.

  Further, in a semiconductor element such as the above-described JFET that controls the drain current by controlling the spread of the depletion layer formed in the channel portion by the gate voltage, the p-type impurity semiconductor region that is the gate region is not particularly activated at a low temperature. Therefore, even if a reverse bias voltage is applied between the gate and the source, a depletion layer is hardly formed in the n-type impurity semiconductor region. For this reason, it is difficult to cut off the drain current even if a reverse bias voltage is applied between the gate and the source in a low temperature state of −20 ° C. to −40 ° C. required in the in-vehicle field. For this reason, in the low temperature state of −20 ° C. to −40 ° C. or lower, the same driving method as in the room temperature state cannot be used.

  Patent Document 1 discloses a normally-off high breakdown voltage SiC JFET in which drain current flows even when the gate voltage is zero volts, and a normally-off low breakdown voltage MOSFET in which drain current does not flow when the gate voltage is zero volts is cascode-connected to provide a high breakdown voltage and low loss normally-off. A method of realizing a type switching element with a composite element is disclosed.

  Patent Document 2 discloses a SIT activation circuit in which a time difference is applied to the application of a gate voltage and a source voltage in order to stably activate a normally-on transistor SIT (electrostatic induction transistor).

  Patent Document 3 discloses a method for driving a normally-on type JFET, particularly a control circuit that can keep the gate current low even when a JFET having a different gate-source diode withstand voltage is used.

Japanese translation of PCT publication No. 9-508492 (description of FIGS. 5A and 5B) Japanese Patent Laid-Open No. 7-23570 (description of FIGS. 1 and 2) Patent Application Publication US2003 / 0179035A1 (described in FIGS. 3 to 6)

  In the above prior art, the one described in Patent Document 1 allows a normally-on characteristic JFET to be controlled by a normal normally-off type power semiconductor device circuit, but a normally-off characteristic power MOSFET is used as a normally-on characteristic JFET. There is a problem that it is complicated because only a number is required.

  Patent Document 2 discloses a start circuit for SIT in which a time difference is applied to the application of gate voltage and source voltage in order to drive SIT which is a normally-on transistor. In the case of starting the circuit at a low temperature of 40 ° C. or lower, a countermeasure for the problem that the drain current of the SIT cannot be cut off in the normal gate-source voltage range has not been considered.

  The thing of patent document 3 was not considered regarding the control circuit which produces | generates a negative gate voltage, without using a transformer.

An object of the present invention is to provide a suitable semiconductor circuits to drive the power semiconductor element power semiconductor element or threshold voltage is low has the normally-on characteristics.

  In the present invention, a negative power supply voltage generation circuit using a diode and a capacitor as a rectifying element is provided in order to reduce the number of floating batteries, transformers and ordinary batteries.

  Furthermore, in the present invention, even when the power semiconductor circuit is used in a low temperature state of −20 ° C. to −40 ° C. or lower, the power semiconductor element is connected in order to control the power semiconductor element without greatly adversely affecting the load. Before raising the voltage of the high-voltage side voltage terminal to the target voltage, the field effect power semiconductor element is heated to increase the threshold voltage, or the negative gate that exceeds the gate-source voltage range during normal driving The source voltage (high reverse voltage) is applied to suppress the drain leakage current, and then the high voltage power source is raised.

  Further, in the field effect power semiconductor element used in the semiconductor circuit of the present invention, the shape of the source diffusion layer is made close to a circle, and the concentration of the gate diffusion layer is lowered.

  In the present invention, the control circuit for the power semiconductor element having a negative or low threshold voltage is simplified, and the semiconductor circuit is easily downsized and integrated into an IC.

  In the semiconductor circuit of the present invention, at least one power semiconductor element is wired between the first power supply voltage terminal and the reference voltage terminal, the load whose power is controlled by the power semiconductor element, and the power semiconductor element are controlled. A control circuit is provided, and the control circuit operates between a high-voltage side voltage terminal separated from a source voltage of the power semiconductor element by a predetermined first voltage and a low-voltage side voltage terminal separated in a second negative voltage direction. In the first use temperature range, the threshold voltage of the power semiconductor element is a voltage between the first voltage and the second voltage, and in the second use temperature range, the threshold voltage of the power semiconductor element is the first voltage. The voltage may exceed the voltage range between the voltage and the second voltage. Thereby, the voltage of the low-voltage side voltage terminal of the control circuit of the power semiconductor element is set to a high negative voltage that can cut off the power semiconductor element even at −20 ° C. to −40 ° C. or lower, or the voltage of the low-voltage side voltage terminal is always Therefore, it is not necessary to prepare a complicated circuit for controlling so that the frequency can be constantly changed. The high-voltage side voltage terminal is a terminal having a higher voltage than the low-voltage side voltage terminal, and may be a voltage that is separated in the negative direction with respect to the source voltage. The first voltage is a voltage including zero volts.

  Furthermore, in the semiconductor circuit of the present invention, at least one power semiconductor element and an output terminal are wired between a reference voltage terminal and a first power supply voltage terminal whose voltage is higher than the voltage of the reference voltage terminal, and the power semiconductor element is A control circuit for controlling is provided, and each of the control circuits operates between a predetermined high voltage side voltage separated from a source voltage of the power semiconductor element and a low voltage side voltage separated in the second voltage negative direction. The low-voltage side voltage is lower than the source voltage, and a first capacitor and a first rectifying element are connected in series between the output terminal and the second power supply voltage terminal, and the voltage at the output terminal rises. In this case, the first capacitor was charged, and the voltage increased by charging the first capacitor was used to increase the voltage at the low-voltage side voltage terminal in the negative direction. As a result, a negative power supply voltage for driving a power device having a normally-off characteristic or a power device having a low threshold voltage can be generated without using a floating power supply or a transformer, and the control circuit can be made simple and compact.

  Hereinafter, details of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of this embodiment, and FIG. 2 is a drive timing chart. FIG. 3 is a level shift circuit used in FIG. Although a circuit using an n-channel type JFET is shown as the power semiconductor elements 101 and 102, other field effect type power semiconductor elements other than JFET, electrostatic induction type transistors, HEMT (High Electron Mobility Transistor), and current gain This is the same even when a bipolar switching element having a high base current and a small base current is used. In this embodiment, a case where normally-on type SiC power semiconductor elements are used as the power semiconductor elements 101 and 102 will be described.

  In this embodiment, a high-side switch power semiconductor element 101 is connected between the high voltage terminal 503 and the output terminal 505, and a low-side switch power semiconductor is connected between the output terminal 505 and the reference voltage terminal 504. This is a bridge circuit in which an element 102 is arranged and a load 104 whose power is controlled by the power semiconductor element 101 for the high-side switch and the power semiconductor element 102 for the low-side switch is connected to an output terminal 505. A control circuit 110 for the high side switch is provided to control the power semiconductor element 101 for the high side switch, and a control circuit 111 for the low side switch is provided to control the power semiconductor element 102 for the low side switch. is there.

  In this embodiment, the high voltage side voltage terminal of the control circuit 110 for the high side switch has the same potential as the source terminal of the power semiconductor element 101 and is connected to the output terminal 505. Reference numeral 510 denotes a low voltage side voltage terminal of the control circuit 110 for the high side switch. Further, the high voltage side voltage terminal of the control circuit 111 for the low side switch has the same potential as the source terminal of the power semiconductor element 102 and is connected to the reference voltage terminal 504. Reference numeral 509 denotes a low voltage side voltage terminal of the control circuit 111 for the low side switch.

  In this embodiment, the voltages at the voltage terminals 500, 506, 501, 502, and 513 are set to, for example, 100V, 90V, 3V, 0V, and −10V by the batteries 126, 127, 128, and 129, respectively. Of course, it may replace with a battery and may be a power supply device which generates each voltage. The voltage terminals 506, 501, 502, and 513 are connected to the voltage terminals 511 and 507, the reference voltage terminal 504, and the low-voltage side voltage terminal 509 through the switches 115, 116, 117, and 118, respectively, but the circuit leakage current is ignored. If possible, the switches 115, 116, 117, and 118 may be omitted and always connected. The switches 115, 116, 117, and 118 may be switches using mechanical relays or semiconductor switches. Further, in this embodiment, for example, the voltage at the voltage terminal 500 is illustrated as being generated by connecting the batteries 128, 127, and 126, and the voltage at the voltage terminals 500, 506, and 501 is generated. You may produce | generate independently with each separate battery.

  In this embodiment, a capacitor 114 and a diode 113 as a rectifying element are connected between an output terminal 505 and a voltage terminal 511, and the high side switch is switched by the voltage charged in the capacitor 114 when the output terminal 505 becomes a high potential. Generating a voltage at the low-voltage side voltage terminal 510 of the control circuit 110 for use. The voltage of the low voltage side voltage terminal 510 is {(voltage of the high voltage terminal 503) − (voltage of the voltage terminal 511) − (forward voltage of the diode 113)] from the voltage of the output terminal 505 which is the source terminal of the power semiconductor element 101. }, The capacitor 114 is charged and used as a floating power supply for negative voltage. That is, in the case of the present embodiment, the capacitor 114 is charged by the source current of the power semiconductor 101, and the voltage at the low-voltage side voltage terminal 510 of the circuit 110 that brakes the power semiconductor element 101 is more negative than the source voltage. It is generated as follows.

  For this reason, there is no need to connect a floating battery or generate a floating power supply using a transformer for the control circuit of the high side switch. In this embodiment, the threshold voltage of the power semiconductor element 101 is 0 V, − {(voltage of the high voltage terminal 503) − (voltage of the voltage terminal 511) − (forward voltage of the diode 113)} V, The value is between.

  FIG. 2 shows a drive timing chart. Vdd is the voltage at the high voltage terminal 503, and Vout is the voltage at the output terminal 505. In this embodiment, the time when the switch 117 is turned on and the time when the main switch is turned on are shown simultaneously. When the switches 116 and 118 are turned on, the power supply voltages of the control circuit 134 and the control circuit 111 rise, the capacitor 114 is charged, and the power supply voltage of the control circuit 110 also rises. Thereafter, the switches 105 and 115 are turned on. In the semiconductor circuit of this embodiment, at least at one time during the time when the voltage at the high voltage terminal 503 is raised to Vdd (80%) which is 80% of the final target voltage Vdd (100%) after the main switch is turned on. The driving is performed so that more than half of the supply current Isup from the high voltage terminal 503 becomes the drain current Ifet of the power semiconductor element 101. At this time, the drain current flowing through the power semiconductor element 101 is 0.1% or more of the maximum drain current flowing through the power semiconductor element 101. At this time, the boosting speed of the high voltage terminal 503 is suppressed so that the output voltage Vout becomes a voltage equal to or lower than 30% of the final target voltage Vdd (100%).

  For this reason, in this embodiment, when the drain current of the power semiconductor element is increased by using the impedances 108 and 109 and the switches 106 and 107, the impedance of the path of the supply current Isup is increased to decrease the supply current Isup. During the period from t2 to t3, a current is passed through the power semiconductor element to cause self-heating, thereby increasing the junction temperature of the power semiconductor element and reducing the drain leakage current of the power semiconductor element. Once the semiconductor chip generates heat, the temperature does not drop rapidly, so the drain leakage current can be kept low. By turning on the switch 106 at the time t3 when the drain current decreases, the impedance of the path of the supply current Isup is slightly reduced, and the capacitor 103 and the parasitic capacitance of the power semiconductor element are charged. At time t4 when the voltage at the high voltage terminal 503 almost reaches the target voltage, the switch 107 is turned on, the impedance of the path of the supply current Isup is made zero, and the normal drive mode is entered.

  In this embodiment, the self-heating of the power semiconductor element is used to increase the threshold voltage of the power semiconductor element. However, the voltage Vdd at the high voltage terminal 503 is set to the target voltage using means such as heating by a heater or induction heating. The power semiconductor element may be heated before being raised. Note that, as a method of gradually increasing the voltage of the high voltage terminal 503, the above is realized by using the resistors 108 and 109 and the switch elements 105, 106, and 107, but without using these resistors and switches. It may be realized by using a booster circuit using a chopper or the like and controlling the boosting speed.

  In the control circuit of the prior art, when the voltage at the high voltage terminal 503 is increased, the power semiconductor element is driven off, and the drain current at that time is from zero to less than 0.1% of the maximum current of the power semiconductor element. . For this reason, if it is attempted to determine the voltage at the low voltage side voltage terminal of the control circuit under the condition that the power semiconductor element whose threshold voltage has decreased in a low temperature state of −20 ° C. to −40 ° C. can be determined, the power semiconductor element is A voltage (high negative voltage) lower than the voltage of the low-voltage side voltage terminal necessary for shutting off is required. For this reason, it is necessary to always increase the voltage amplitude of the gate drive circuit, and the charge / discharge power increases. Further, when trying to use a control circuit in which the voltage at the low-voltage side voltage terminal is always the optimum value, the control circuit becomes complicated.

  Further, in the conventional inrush current prevention circuit, when the voltage of the high voltage terminal 503 is increased, the power semiconductor element is driven off, so that no drain current flows through the power semiconductor element, and the supply current Isup is the capacitor 103 or the power semiconductor element. A value such as impedance 109 is selected on the assumption that the parasitic capacitances 101 and 102 are used only for charging. For this reason, when trying to drive a power semiconductor device having a reduced drain current blocking capability using the conventional inrush current prevention circuit, the drain leakage current suddenly increases too much, and the output voltage Vout applied to the output terminal is the final value. The voltage is 30% or more of the target voltage Vdd (100%). For this reason, there is a possibility that the power semiconductor element is destroyed or the actuator as a load malfunctions. Alternatively, an overcurrent or overvoltage protection circuit may operate and the circuit may not be activated. On the other hand, in this embodiment, these problems can be avoided.

  In this embodiment, the drain current blocking capability of the power semiconductor element is lowered. In the low temperature state of −20 ° C. to −40 ° C. or lower, the power semiconductor element is heated to increase the threshold voltage, or the gate / source of the power semiconductor element Although the circuit diagram is such that the reverse voltage applied between them can be temporarily increased at the same time, only one of the methods may be used. The diode 138 is a diode for preventing a current flowing backward from the load, and is not necessary depending on the application. That is, for example, when the diode 138 is eliminated and the current flowing back from the load becomes excessive, the switches 107 and 106 are turned off, the load current is suppressed by the resistors 108 and 109, and the current flowing back from the load decreases. First, the switch 106 may be turned on and then the switch 107 may be turned on.

  A terminal 508 in FIG. 1 is an input terminal, and a control signal passes through the control circuit 134 and the level shift circuit 125 to control the control circuit 111 for the low side switch, and further controls the high side switch via the level shift circuit 112. The circuit 110 is controlled. FIG. 3 shows a configuration example of the level shift circuit 125 and the level shift circuit 112. The level shift circuit 125 lowers the voltage level from the signal level of the voltage terminal 507 / reference voltage terminal 504 to the reference voltage terminal 504 / low voltage side voltage terminal 509. In order to transmit “H”, the MOSFET 307 is turned on and the MOSFET 308 is turned off. As a result, the latch circuit 313 is set and the output Q1 becomes “H”. In order to transmit “L”, the MOSFET 308 is turned on and the MOSFET 307 is turned off. As a result, the latch circuit 313 is reset and the output Q1 becomes “L”. The level shift circuit 112 increases the voltage level from the signal level of the reference voltage terminal 504 / low voltage side voltage terminal 509 to the signal level of the output terminal 505 / low voltage side voltage terminal 510. In order to transmit “H”, the MOSFET 300 is turned on and the MOSFET 301 is turned off. As a result, the latch circuit 306 is set and the output Q2 becomes “H”. In order to transmit “L”, the MOSFET 300 is turned on and the MOSFET 301 is turned off. As a result, the latch circuit 306 is reset and the output Q2 becomes “L”.

  If a voltage level is directly shifted from the voltage level of the voltage terminal 507 / reference voltage terminal 504 to the voltage level of the output terminal 505 / low voltage side voltage terminal 510, the voltage range is lowered to the high potential side depending on the voltage state of the output terminal 505. Since the voltage needs to be transmitted also to the side, the circuit becomes complicated. On the other hand, in this embodiment, the signal from the input terminal is also level-shifted once to the negative voltage side, and then level-shifted to the high voltage side. That is, in this embodiment, the voltage range to be level shifted in each level shift circuit is only in the high potential side direction or the low potential side direction, so that the control circuit is simplified. In FIG. 3, a capacitor may be provided between the MOSFET 307 and the MOSFET 311, between the MOSFET 308 and the MOSFET 309, between the MOSFET 304 and the MOSFET 301, and between the MOSFET 302 and the MOSFET 300, and the level shift may be performed using capacitive coupling. Alternatively, optical means such as a photocoupler may be used as a signal transmission means for controlling the power semiconductor element, or a signal may be transmitted by a transformer.

  When the reverse bias voltage is not applied between the gate and the source of the power semiconductor element 101 when the main switch is turned on, that is, when the capacitor 114 is not charged, the power semiconductor element 101 cannot be turned off, and the high voltage terminal 503 When the voltage is increased to the target voltage, the voltage at the output terminal 505 also increases at the same time. Therefore, in this embodiment, when the main switch is turned on, the MOSFET 123 which is a switch element connected to the low voltage terminal 509 is turned on so that the high side switch control circuit can be driven off. Furthermore, in this embodiment, when it becomes difficult to turn off the power semiconductor element 101 in a low temperature state of −20 ° C. to −40 ° C. or lower, the MOSFET 123 is kept turned on, whereby the low voltage side voltage of the control circuit of the power semiconductor element 101 is increased. The terminal 510 can be kept at the voltage of the low-voltage side voltage terminal 509. For this reason, when the voltage of the output terminal 505, which is also the source terminal, rises, a low voltage (high reverse voltage) exceeding the normal gate voltage range can be applied between the gate and source of the power semiconductor element 101. Terminal) voltage rise is minimized. When the MOSFET 123 is used, the power semiconductor element 101 is turned on when the power semiconductor element 101 is in the off state, and is driven to turn off when the drain current of the MOSFET 123 becomes equal to or higher than the specified current. The voltage at the low-voltage side voltage terminal 510 can be lowered until the diode reaches the breakdown voltage or until the Zener diode 142 connected between the gate and the source of the power semiconductor element 101 breaks down. Thereby, whenever the threshold voltage of the power semiconductor element 101 becomes low, a high negative gate-source voltage necessary for turning off the power semiconductor element 101 can be applied, and unnecessary current loss can be suppressed. Here, the role of the switch element 123 has been described in the case where the power semiconductor element becomes too low temperature to be turned off, but the threshold voltage decreases at a high temperature and the power semiconductor element becomes difficult to turn off. Even if used in some cases, the same effect is obtained. The switch element 123 is preferably connected to the negative voltage terminal 504, but may be connected to the reference voltage terminal 504.

  The Zener diode 142 is provided to protect the MOSFETs 119 and 120 used in the control circuit 110 from overvoltage, but is not necessary when there is no concern about overvoltage. The resistor 100 is not necessarily provided to suppress the current of the MOSFET 123. Alternatively, when the MOSFET 123 is eliminated and only the resistor 100 having a large resistance value is provided, a current always flows through the resistor 100. However, before the voltage at the high voltage terminal 503 is raised, the capacitor 114 is connected by the negative low voltage terminal 509. The power semiconductor element 101 can be off-controlled by being easily charged. The control circuits 134, 110, and 111 are partly connected with capacitors and diodes. However, MOSFETs or the like as switch elements can be miniaturized by integrating them on a single chip.

  In this embodiment, a normally-on type JFET is used as the power semiconductor element. However, in the present invention, a general control circuit for a field effect type power semiconductor element including a normally-on type power MOSFET is used. Is preferred. However, it is particularly suitable when a JFET, SIT, MES • FET, or a storage field effect transistor whose ability to cut off the drain current is lowered at a low temperature of −20 ° C. to −40 ° C. is used.

  FIG. 4 is a circuit diagram of this embodiment. In this embodiment, a MOSFET 123 is connected to the gate terminal of the power semiconductor element 101 as means for forcibly turning off the power semiconductor element 101 for the high-side switch, and further, the gate terminal and the low-voltage side voltage terminal of the power semiconductor element 101. The only difference from the first embodiment is that a diode 130 that is a rectifying element is provided between the first and second embodiments, and the rest is the same as the first embodiment. When the diode 130 is not provided, a high negative voltage is applied between the gate and the source of the power semiconductor element 101 by a parasitic diode existing between the drain and the source of the MOSFET 120 which is a switch element, and the voltage at the low voltage side voltage terminal 510 is also Therefore, the operation is the same as that of the first embodiment shown in FIG. When the diode 130 is present, a voltage lower than the low-voltage side voltage terminal 510 can be applied between the gate and the source of the power semiconductor element 101, so that the power semiconductor element 101 does not have to have a high breakdown voltage. A high negative voltage can be applied between the gate and the source.

  FIG. 5 is a circuit diagram of the present embodiment. This embodiment is different from the first embodiment in that the control circuit 134 is a circuit that operates between the reference voltage terminal 504 and the low-voltage side voltage terminal 509. In this embodiment, there is an advantage that the level shift circuit 125 is not required. Others are the same as in the first embodiment.

  FIG. 6 is a circuit diagram of this embodiment. Compared with the circuit diagram of the first embodiment shown in FIG. 1, the present embodiment differs from the first embodiment in that the high-voltage side voltage terminal is 512 and the voltage is higher than the source terminal 505 of the power semiconductor element 101. Therefore, the gate-source voltage ranges of the high-side switch power semiconductor element 101 and the low-side switch power semiconductor element 102 can be applied not only in the negative direction but also in the positive direction. For this reason, the gate-source voltage of the power semiconductor element 101 can be increased, and the on-resistance can be decreased. Further, even when the power semiconductor elements 101 and 102 are normally-off elements, they can be used. The circuit configuration of this embodiment is provided with a capacitor 131 and a diode 132 that is a rectifying element, and the high-voltage side voltage terminal of the high-side switch power semiconductor element is a voltage terminal 512. When the output terminal 505 is at a low potential, the capacitor 131 is charged and the voltage is increased. This voltage causes the voltage at the voltage terminal 512 to be the voltage at the output terminal 505 to which the source terminal of the power semiconductor element 101 is connected. It becomes a value higher than {(voltage of the voltage terminal 507) − (forward voltage of the diode 132)}. The low-voltage side voltage terminal of the high-side switch power semiconductor element is the same as FIG. In this embodiment, the threshold voltage of the power semiconductor element 101 for the high side switch is {(voltage of the voltage terminal 507) − (forward voltage of the diode 132)} V and − {(high voltage voltage terminal 503). Voltage) − (voltage at voltage terminal 511) − (forward voltage of diode 113)} V.

  The high voltage side voltage terminal of the power semiconductor element for the low side switch is the voltage terminal 514. In this embodiment, the high-side voltage terminal of the low-side switch power semiconductor element may be the voltage terminal 507, but in order to make the voltages of the high-side switch power semiconductor element and the high-side voltage terminal of the low-side switch power semiconductor element uniform. A diode 133 which is a rectifying element is provided. In the case of JFET, the forward voltage between the gate and the source is as low as about 0.7 V in the case of the Si substrate and about 2.5 V in the case of the SiC substrate. Since the current flows from the gate to the drain if the positive voltage is too high, voltage control of the voltage terminal 507 is important.

  By optimally controlling the voltage at the voltage terminal 507 with the configuration of this circuit, the upper limit values of the gate-source voltages of both the high-side switch power semiconductor element 101 and the low-side switch power semiconductor element 102 are set to substantially the same value. Can be set. Therefore, the high-side switch power semiconductor element 101 and the low-side switch power semiconductor element 102 can be optimally controlled. When the diode 133 which is a rectifying element is provided, the threshold voltage of the power semiconductor element 102 for the low-side switch is {(voltage of the voltage terminal 507) − (forward voltage of the diode 133)} V and (low voltage side voltage) The voltage between the terminal 509 and the voltage V).

  In this embodiment, the power semiconductor element is suitable for a general control circuit intended for a field effect type power semiconductor element including a power MOSFET. In particular, it is particularly suitable when a JFET, SIT, MES • FET, or a storage field effect transistor whose ability to cut off the drain current is lowered in a low temperature state of −20 ° C. to −40 ° C. or lower is used.

  In the case of a normally-off type power semiconductor device, it can be turned off by setting the gate-source voltage to zero volt. Therefore, it is not always necessary to apply a negative voltage between the gate and the source as in this embodiment, but as in this embodiment. In addition, when a negative voltage is applied between the gate and source of the power semiconductor element to turn it off, it is possible to prevent the power semiconductor element from being turned on by mistake due to noise applied to the gate terminal. Others are the same as in the first embodiment.

  FIG. 7 is a circuit diagram of this embodiment. Compared with the circuit diagram of the fourth embodiment shown in FIG. 6, the present embodiment is different in that the MOSFET 124 and the comparator 135 are used instead of the diode 132 as the rectifying element. The comparator 135 turns on the MOSFET 124 only when the voltage at the voltage terminal 512 becomes lower than the voltage at the voltage terminal 507, and turns off the MOSFET 124 only when the voltage at the voltage terminal 512 becomes higher than the voltage at the voltage terminal 507. Therefore, although the circuit is a little complicated, the forward voltage drop of the diode 132 in FIG. 6 can be lowered. For this reason, the diode 133 of FIG. 6 can also be deleted in this embodiment. Others are the same as the fourth embodiment.

  FIG. 8 is a circuit diagram of this embodiment. Compared to the circuit diagram of the fourth embodiment shown in FIG. 6, the present embodiment is different in that the capacitor 136 is used instead of the capacitor 114. The voltage at the low voltage side voltage terminal of the control circuit for the high side switch is determined by the difference between the voltages charged in the capacitor 136 and the capacitor 131. In the case of this embodiment, there is no capacitor 114, but there are a capacitor 136 and a capacitor 131, so that it is substantially the same as FIG. Therefore, the features and effects of the present embodiment are the same as those of the fourth embodiment.

  FIG. 9 is a circuit diagram of this embodiment. Compared with the circuit diagram of the first embodiment shown in FIG. 1, in this embodiment, the negative voltage of the low-voltage side voltage terminal 509 of the control circuit 111 of the power semiconductor element 102 for the low-side switch is generated without the battery 129. Is different. In order to generate a voltage at the low-voltage side voltage terminal 509, a diode 139 that is a rectifying element is connected between the capacitor 114 and the low-voltage side voltage terminal 509 for the low-side switch.

  Thus, the capacitor 114 is charged when the output terminal 505 becomes high voltage, and a part of the energy charged in the capacitor 114 when the output terminal 505 becomes low potential is used to charge the capacitor 141. ing. That is, the capacitor 141 is used instead of the battery 129 shown in FIG. Further, since the power semiconductor elements 101 and 102 are driven off before the main switch is turned on and the voltage at the high voltage terminal 503 rises, a negative voltage is applied from the reference voltage terminal 504 by the charge pump circuit 137 as shown in FIG. Is generated at the low voltage side voltage terminal 509 to charge the capacitor 141 in advance. In FIG. 10, MOSFETs 319 to 323 operate as diodes (rectifying elements), and a terminal to which the gate is connected operates as an anode, and a terminal to which the gate is not connected operates as a cathode. Reference numerals 324 to 327 denote capacitors, which operate the clocks φ1 and φ2 in opposite phases to move charges from the low voltage side voltage terminal 509 to the reference voltage terminal 504, thereby making the low voltage side voltage terminal 509 negative voltage. The clock frequency is about several hundred kHz to several tens of MHz. The control circuits 134, 110, and 111 and the charge pump circuit 137 are externally provided with a capacitor and a part of the diode, but the MOSFET or the like that is a switching element can be integrated into a single chip and miniaturized. Others are the same as in the first embodiment.

  FIG. 11 is a circuit diagram of this embodiment. Compared with the circuit diagram of the fourth embodiment shown in FIG. 6, as in the seventh embodiment shown in FIG. 9, the negative voltage of the low-voltage side voltage terminal 509 of the high-side switch control circuit is generated without the battery 129. The only difference is that Others are the same as the fourth embodiment. If the low-side switch power semiconductor element 102 is a normally-off type element, the charge pump circuit 137 may be omitted.

  FIG. 12 is a circuit diagram of this embodiment. In this embodiment, the power semiconductor element 101 is used for a high-side switch circuit. The present embodiment is the same as the seventh embodiment except that there is no circuit related to the power semiconductor element 102 for the low-side switch in the seventh embodiment shown in FIG.

  FIG. 13 is a circuit diagram of this embodiment. In this embodiment, the power semiconductor element 102 is used for the low-side switch circuit. The present embodiment is the same as the seventh embodiment except that there is no circuit related to the power semiconductor element 101 for the high-side switch in the seventh embodiment shown in FIG.

  FIG. 14 is a circuit diagram of the present embodiment. Compared with the circuit diagram of the first embodiment shown in FIG. 1, in this embodiment, the voltage terminals 506 and 511 and the switch 115 for supplying the low-voltage side voltage of the high-side switch element shown in FIG. The difference is that the capacitor 143 is added to generate the voltage at the voltage terminal 510 on the low voltage side of the high side switch element. For this reason, the voltage terminal 511 in FIG. 1 is not used and is used in common with the voltage terminal 507. The batteries 126 and 127 are collectively shown as a battery 144. Note that the voltage at the voltage terminal 507 may be generated by the power supply device without using the battery 144.

  In this embodiment, when the high voltage terminal 503 is 100 V and the voltage terminal 501 is 3 V, for example, the Zener diode 142 is not necessary to set the voltage between the output terminal 505 and the low voltage terminal 510 to 10 V. The capacitance ratio between the capacitor 114 and the capacitor 143 may be 87:10. Note that this capacitance ratio ignores the parasitic capacitance, the forward voltage drop of the diode, and the on-voltage of the power semiconductor element. By using the Zener diode 142 having a breakdown voltage of 10V, the voltage between the output terminal 505 and the low-voltage side voltage terminal 510 can be 10V even if the capacitance ratio of the capacitor is shifted. In the present embodiment, the voltage terminals 506 and 511 and the switch 115 are eliminated, but the rest is the same as the first embodiment.

  FIG. 15 is a circuit diagram of this embodiment. Compared with the circuit diagram of the eighth embodiment shown in FIG. 11, in this embodiment, the negative voltage at the low-voltage side voltage terminal 509 of the high-side switch control circuit is set to the absence of the battery 129 as in the eleventh embodiment shown in FIG. It is different that it is generated by. Therefore, in this embodiment, the voltage terminals 506 and 511 and the switch 115 in FIG. 11 can be eliminated. The present embodiment is the same as the eighth embodiment except that the voltage terminals 506 and 511 and the switch 115 are not provided.

  FIG. 16 is a circuit block diagram of the present embodiment. In the present embodiment, the case where the voltages of the high voltage terminal 503, the voltage terminal 507, and the low voltage terminal 509 are generated from an AC circuit will be described by taking the embodiment 12 shown in FIG. 15 as an example. In this embodiment, when the main switch is turned on, the switch 145 and the switch 146 are turned on, and a voltage is generated at the voltage terminal 507 and the low-voltage side voltage terminal 509 by the transformer 152. Further, as described with reference to FIG. 2, the switch 200 for the high voltage terminal 503 gradually decreases the internal resistance when the high voltage circuit is activated, and the rectifier circuit 156 including the diode 147 to the diode 150 and the capacitor 151 reduces the pulsating flow to generate a voltage at the high voltage terminal 503. In the present embodiment, in the circuit of the twelfth embodiment shown in FIG. 15, the switch 200 is a switch circuit for alternating current.

  FIG. 18 is a plan view of the power semiconductor element of this example, and FIG. 17 is a cross-sectional view taken along the line AA ′ of FIG. The semiconductor element of this embodiment is a JFET or SIT using SiC, which is a wide band gap semiconductor having a band gap of 2.0 eV or more, as a semiconductor substrate. The wide band gap semiconductor substrate includes GaN (gallium nitride) and diamond in addition to SiC. 17 and 18, reference numeral 1 denotes a drain electrode, 2 denotes a high concentration n-type substrate, 3 denotes a low concentration n-type drain region, 4a denotes a high concentration n-type source region, 6a denotes a high concentration p-type gate region, and 7a denotes The low-concentration p-type gate region, 5a is a source electrode provided for making ohmic contact with the high-concentration n-type source region 4a, 8a is a gate electrode provided for making ohmic contact with the high-concentration p-type gate region 6a, 9a Is a second source electrode, and 9b is a second gate electrode. In the low-concentration p-type gate region 7a, a p-type impurity layer is formed by oblique ion implantation after forming a trench. Reference numeral 10 denotes a region where a gate pad is formed. Further, although the position of the source pad is not shown in FIG. 18, it is formed on the same plane as the region 10 where the gate pad is formed.

  When a reverse bias voltage is applied between the gate and the source, a depletion layer between the low-concentration p-type gate region 7a, the gate electrode 8a, and the low-concentration n-type drain region 3 spreads, and the high-concentration n-type source region No current flows in the channel region surrounded by the trench immediately below 4a. Conversely, when the gate-source reverse bias voltage is lowered and a gate voltage higher than the threshold voltage is applied, a current flows between the drain-source.

  In the case of the power MOSFET of the prior art, the cells have been made circular or polygonal in order to increase the gate length per unit area and lower the on-resistance. That is, the ratio of the planar dimensions X and Y in FIG. 18 is reduced. In the case of the prior art JFET, the drain current is proportional to the plan view size of the channel. Therefore, in the prior art, in order to reduce the on-resistance, the high-concentration n-type source region 4a is elongated, that is, the planar dimension X The ratio X: Y between Y and Y was as large as possible.

  However, in the case where a gate semiconductor region is formed using a trench to form a junction type FET having a high gm as in this embodiment, the threshold voltage is likely to vary if the ratio of the planar dimensions X and Y is increased. It has been found. In addition, since the breakdown points between the drain and the source are concentrated at the corners of the elongated channel region, the breakdown voltage characteristics of the drain are soft breakdown characteristics as shown in the graph shown in FIG.

  In the JFET of this embodiment, the ratio X / Y of the planar dimension X to Y of the high-concentration n-type source region 4a is from 1/10 to 1/1, that is, the planar dimension X is 10% to 100% of Y, more preferably The ratio X / Y of the planar dimensions X and Y was set to 1/5 to 1/1, that is, the planar dimension X was 20% to 100% of Y. Further, a high concentration n-type source region 4a, which is a source region surrounded by the trench region, and a plurality of channel regions immediately below the high concentration n-type source region 4a are arranged in the vertical direction and the horizontal direction to reduce the on-resistance. It became current. As a result, the number of breakdown points between the drain and the source increases and becomes uniform, so that the rising portion of the drain current becomes steep as shown in the graph of FIG. Down and increased breaking strength. Further, in this embodiment, since the shape of the channel region surrounded by the low-concentration p-type gate region 7a and the gate electrode 8a can be easily made uniform, the variation in threshold voltage is reduced. Note that the planar shape of the high-concentration n-type source region 4a is more preferably a polygonal shape, an elliptical shape, a circular shape, or a competition track shape in which a semicircle and a straight line are combined instead of a square shape.

  It has been found that when the device temperature is as low as about −20 ° C. to −40 ° C., the p-type impurity is not activated and it is difficult to form a depletion layer in the channel portion. In order to easily shut off the JFET even in such a low temperature state, it is necessary to apply a high reverse voltage between the gate and the source. When the source semiconductor region and the gate semiconductor region are in contact with each other at a high concentration, the breakdown voltage of the gate-source diode is lowered. Therefore, in this embodiment, a low-concentration p-type gate region 7a is provided and the reverse voltage of the gate-source diode is provided. The pressure resistance against is increased. Therefore, in the JFET of this embodiment, even when a high negative gate voltage that can be turned off at a low temperature of −20 ° C. to −40 ° C. is applied, the leakage current between the gate and the source can be ignored. This structure is also effective when a high negative gate voltage is applied when the JFET becomes high temperature and the threshold voltage becomes low.

  In order to form a narrow trench, the gate electrode 8a used for making an ohmic contact with the high-concentration p-type gate region 6a for the gate at the bottom of the trench cannot be thickened. For this reason, it is difficult to extend the gate electrode 8a over the trench. On the other hand, in order to form a wiring from the high-concentration p-type gate region 6a at the bottom of the trench to the region 10 where the gate pad is formed, the trench is connected via the low-concentration p-type gate region 7a formed on the sidewall of the trench. Although it is easy to connect from the bottom to the top of the trench, the gate resistance increases.

  Therefore, in the semiconductor element of this embodiment, in order to reduce the gate wiring resistance from the gate electrode 8a to the region 10 where the gate pad is formed, the gate electrode 8a is used to make an ohmic contact with the high-concentration p-type gate region 6a. And connected to the second gate electrode 9b having a thickness larger than that of the gate electrode 8a, and connected to the region 10 where the gate pad is formed. Further, in order to reduce the resistance of the source electrode, a second source electrode 9a having a thickness greater than that of the high concentration n-type source electrode 4a is provided. Here, the second source electrode 9a and the second gate electrode 9b can be formed in the same process.

  In this embodiment, in order to increase the breakdown voltage between the drain and the source, the high concentration p-type regions 6b and 6c formed at the bottom of the trench and the low concentration p-type regions 7b and 7c formed on the sidewall of the trench are A floating field limiting ring is formed by being separated by the high-concentration n-type regions 4b and 4c formed on the trench. The high-concentration n-type region 4b is formed in the same process as the high-concentration n-type source region 4a for the source, and the high-concentration p-type regions 6b and 6c and the low-concentration p-type regions 7b and 7c are the high-concentration p-type region 6a for the gate. It can be formed in the same process as the low concentration p-type gate region 7a for the gate. When the high-concentration n-type regions 4a, 4b, and 4c are formed apart from the p-type regions 7a, 7b, and 7c so that the high-concentration impurities do not contact each other, the p-type regions 7a, 7b, and 7c on the trench sidewalls are formed. Even if the impurity concentration is high, the withstand voltage can be secured.

  As described above, in this embodiment, the field effect type power semiconductor element is described as being an n-channel type. However, in the case of a p-channel type power semiconductor element, the same is achieved by reversing the polarity of the circuit and the conductivity type of the impurity layer. Needless to say, a simple structure can be realized and the same effect can be obtained.

1 is a circuit diagram of Embodiment 1. FIG. 2 is a drive timing chart of the semiconductor circuit diagram of Embodiment 1. FIG. FIG. 3 is a level shift circuit diagram of the circuit diagram of the first embodiment. FIG. 6 is a semiconductor circuit diagram of Example 2. FIG. 6 is a semiconductor circuit diagram of Example 3. FIG. 6 is a semiconductor circuit diagram of Example 4. FIG. 10 is a semiconductor circuit diagram of Example 5. FIG. 10 is a semiconductor circuit diagram of Example 6. FIG. 10 is a semiconductor circuit diagram of Example 7. FIG. 10 is a charge pump circuit diagram according to a seventh embodiment. FIG. 10 is a semiconductor circuit diagram of Example 8. FIG. 10 is a semiconductor circuit diagram of Example 9. FIG. 10 is a semiconductor circuit diagram of Example 10. FIG. 18 is a semiconductor circuit diagram of Example 11. FIG. 20 is a semiconductor circuit diagram of Example 12. FIG. 18 is a semiconductor circuit diagram of Example 13; Sectional drawing of the junction type semiconductor element of Example 14. FIG. The top view of the junction type semiconductor element of Example 14. FIG. FIG. 20 is a characteristic diagram of the junction semiconductor element according to Example 14;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Drain electrode, 2 ... High concentration n type substrate, 3 ... Low concentration n type drain region, 4a ... High concentration n type source region, 4b, 4c, 4d, 4e ... High concentration n type region, 5a ... Source electrode, 5b to 5e, 8b, 8c, 8d ... metal layer, 6a ... high concentration p-type gate region, 6b-6d ... high concentration p-type region, 7a ... low concentration p-type gate region, 7b-7d ... low concentration p-type region 8a ... first gate metal layer, 9a ... second source electrode, 9b ... second gate electrode, 9c ... field plate metal layer, 9d ... drain field plate metal layer, 10 ... region where the gate pad is formed, DESCRIPTION OF SYMBOLS 11 ... Insulating layer, 100 ... Resistance, 101, 102 ... Power semiconductor element, 103, 114, 131, 136, 141, 143, 151, 324-327 ... Capacitor, 104 ... Load, 105-107, 115 18, 145, 146, 200 ... switch, 108, 109 ... impedance, 110, 111, 134 ... control circuit, 112, 125 ... level shift circuit, 113, 130, 132, 133, 138, 139, 147-150 ... diode DESCRIPTION OF SYMBOLS 119-124 ... MOSFET, 126-129, 144 ... Battery, 135 ... Comparator, 137 ... Charge pump circuit, 142, 157 ... Zener diode, 152 ... Transformer, 153 ... Plug for alternating current, 154, 155 ... Power supply circuit, 156: Rectifier circuit, 300-305, 307-312, 314-323 ... MOSFET, 306, 313 ... Latch circuit, 500, 501, 502, 506, 507, 511-514 ... Voltage terminal, 503 ... High voltage terminal, 504 ... Reference voltage terminal, 505 ... Output terminal 508 ... input terminal, 509, 510 ... the low-pressure side voltage terminal.

Claims (17)

  1. Wiring a power semiconductor element between the first power supply voltage terminal and the reference voltage terminal;
    A load whose power is controlled by the power semiconductor element;
    A control circuit for controlling the power semiconductor element;
    The control circuit has a first voltage positive or negative direction that is predetermined with respect to the voltage of the source terminal of the power semiconductor element, or a high voltage terminal that is equal to the voltage of the source terminal, and a voltage of the source terminal. In contrast, it operates with a low-voltage side voltage terminal that is separated in the negative direction of the second voltage predetermined,
    In the first operating temperature range, a threshold voltage of the power semiconductor element is a voltage between the first voltage and the second voltage,
    In the second use temperature range, the threshold voltage of the power semiconductor element is a voltage exceeding the voltage range between the first voltage and the second voltage in the first use temperature range.
  2.   2. The control circuit according to claim 1, wherein the control circuit heats the power semiconductor element, and a threshold voltage of the power semiconductor element exceeds a voltage range between the first voltage and the second voltage in the first use temperature range. A semiconductor circuit, wherein the value is changed to a value between the first voltage and the second voltage in the first operating temperature range.
  3.   3. The semiconductor circuit according to claim 2, wherein a voltage is applied between the drain and source of the power semiconductor element to heat the drain by flowing a drain current.
  4.   4. The method according to claim 3, wherein during the voltage increase period until the first power supply voltage terminal reaches 80% of the target voltage value after the main switch is turned on, half or more of the current supplied from the first power supply voltage terminal is the power. A drain current of the semiconductor element is allowed to flow, and an output voltage applied to the load is maintained at 30% or less of a maximum output voltage to generate heat, and the threshold voltage of the power semiconductor element is set to the first potential. And changing the value to a value between the first potential and the second potential, and then increasing the voltage of the first power supply voltage terminal so as to reach a target voltage.
  5.   2. The device according to claim 1, wherein the control circuit applies a voltage exceeding a voltage range between the first voltage and the second voltage in the first operating temperature range between a gate and a source of the power semiconductor element. The semiconductor circuit, wherein the first power supply voltage terminal is raised to a value of 80% of the final target voltage value.
  6.   In Claim 1, the control circuit provides a semiconductor switch element between the low voltage side voltage terminal and a voltage terminal whose voltage is lower than a reference voltage terminal, or between the low voltage side voltage terminal and the reference voltage terminal, A semiconductor circuit, wherein a voltage exceeding a voltage range between the first voltage and the second voltage in the first use temperature range is applied between a gate and a source of the power semiconductor element.
  7. Wiring a power semiconductor element and an output terminal between a reference voltage terminal and a first power supply voltage terminal having a voltage higher than the reference voltage terminal;
    A control circuit for controlling the power semiconductor element;
    The control circuit is separated in the positive or negative direction of the first voltage predetermined with respect to the voltage of the source terminal of the power semiconductor element or separated in the negative direction of the high voltage side voltage terminal and the second voltage in the negative direction equal to the voltage of the source terminal. Operates with the low-voltage side voltage terminal,
    The voltage of the low-voltage side voltage terminal is a negative voltage lower than the voltage of the source terminal of the power semiconductor element,
    A first capacitor and a first rectifying element are connected in series between the output terminal and the second power supply voltage terminal, and the first capacitor is charged when the voltage at the output terminal rises, A semiconductor circuit, wherein the voltage of the low-voltage side voltage terminal is increased in the negative direction by using the voltage of one capacitor.
  8.   8. The semiconductor circuit according to claim 7, wherein a second capacitor is provided between the first capacitor and the first rectifying element.
  9.   8. The third capacitor according to claim 7, wherein a third capacitor is provided between the output terminal and the high voltage terminal of the power semiconductor element, and a second capacitor is provided between the high voltage terminal and the third power supply voltage terminal of the power semiconductor element. And a voltage that is charged in the third capacitor when the output terminal becomes a low voltage, the voltage at the high-voltage side voltage terminal of the power semiconductor element is increased in the positive direction. circuit.
  10.   The power semiconductor element according to claim 7, wherein the power semiconductor element is a low-side switch power semiconductor element provided between the reference voltage terminal and the output terminal, and a second semiconductor device is connected between the low voltage terminal and the first capacitor. A semiconductor circuit comprising a rectifying element.
  11.   The power semiconductor element for a high side switch according to claim 9, wherein the power semiconductor element is provided between a first power supply voltage terminal and the output terminal, and a power for a low side switch between the output terminal and the reference voltage terminal. A semiconductor circuit, wherein a third rectifier element is provided between a source terminal of the low-side switch power semiconductor element and the third power supply voltage terminal.
  12.   10. The semiconductor circuit according to claim 9, wherein the second power supply voltage terminal and the third power supply voltage terminal are shared.
  13.   8. The semiconductor circuit according to claim 7, wherein a charge pump circuit is used to make the voltage of the low-voltage side voltage terminal lower than that of the reference voltage terminal.
  14.   8. The negative voltage is generated from the reference voltage terminal by a charge pump circuit before the voltage between the first power supply voltage terminal and the reference voltage terminal increases to 80% of the final target voltage. A semiconductor circuit.
  15.   8. The control circuit according to claim 7, wherein the control circuit charges the voltage of the first capacitor before increasing the voltage between the first power supply voltage terminal and the reference voltage terminal to 80% of the final target voltage. A featured semiconductor circuit.
  16. A high-side switch power semiconductor element is connected between the first power supply voltage terminal and the output terminal, a low-side switch power semiconductor element is wired between the output terminal and the reference voltage terminal, and a load is connected to the output terminal. In the semiconductor circuit
    The high-side switch power semiconductor element and the high-side switch control circuit are connected to a high-voltage side voltage terminal and a first high-voltage side voltage terminal that are separated in a positive first voltage positive direction with respect to the voltage of the source terminal of the high-side switch power semiconductor element. Operates between two low voltage terminals that are separated in the negative direction,
    The low-side switch power semiconductor element and the low-side switch control circuit are separated in the positive or negative direction of the first voltage predetermined with respect to the voltage of the source terminal of the low-side switch power semiconductor element, or the voltage of the source terminal Between the high voltage side voltage terminal equal to and the low voltage side voltage terminal separated in the second voltage negative direction,
    A drive signal to the high-side switch control circuit is transmitted with a level shift from a signal level between the reference voltage terminal and a positive voltage terminal to a control signal level of the low-side switch control circuit. A semiconductor circuit.
  17.   17. The semiconductor circuit according to claim 1, wherein the power semiconductor element is a field effect transistor using a semiconductor substrate having a band gap of 2.0 eV or more.
JP2005185898A 2005-06-27 2005-06-27 Semiconductor circuit using field effect type power semiconductor element Expired - Fee Related JP4600180B2 (en)

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