WO1997024806A1 - Dispositif a circuits integres a semi-conducteurs, comportant un circuit de correction de l'erreur de retard - Google Patents

Dispositif a circuits integres a semi-conducteurs, comportant un circuit de correction de l'erreur de retard Download PDF

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Publication number
WO1997024806A1
WO1997024806A1 PCT/JP1996/003875 JP9603875W WO9724806A1 WO 1997024806 A1 WO1997024806 A1 WO 1997024806A1 JP 9603875 W JP9603875 W JP 9603875W WO 9724806 A1 WO9724806 A1 WO 9724806A1
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WIPO (PCT)
Prior art keywords
circuit
delay time
semiconductor
power supply
delay
Prior art date
Application number
PCT/JP1996/003875
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English (en)
Japanese (ja)
Inventor
Toshiyuki Okayasu
Hiroo Suzuki
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to DE19681271T priority Critical patent/DE19681271T1/de
Publication of WO1997024806A1 publication Critical patent/WO1997024806A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032—Dc control of switching transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL

Definitions

  • the present invention relates to a semiconductor integrated circuit device that is useful for a circuit that is required to provide a high-precision delay time, a timing # 4 circuit, or the like, which is constituted by, for example, a plurality of logic elements.
  • the present invention relates to a semiconductor integrated circuit device including a delay error correction circuit capable of improving and stabilizing the accuracy of a delay time generated in a signal propagating through a circuit that needs to be given time.
  • IC tester for testing various semiconductor integrated circuits (hereinafter, referred to as ICs)
  • IC under test Various timing signals are required to generate signals and various control signals.
  • a timing signal generating circuit for generating various timing signals is used in the IC test apparatus.
  • such a timing signal generating circuit includes a plurality of delay elements each composed of a logic element. A delay circuit having a connected circuit configuration is provided, and a timing signal having a desired delay time is generated from each output side of the cascade-connected delay elements or from the output terminal of the delay circuit.
  • TTL Transistor Transistor Logic
  • ECL emitter-Coupled Logic
  • a plurality of cascaded logic gate elements are formed as ICs with a CMOS (complementary MOS) structure, and the delay time from each output side of a number of cascaded CMOS devices is A delay circuit capable of extracting a different signal has been conventionally known.
  • CMOS complementary MOS
  • a delay circuit composed of the above-described M0SIC is often formed as a single IC chip together with other circuits that do not need to have high accuracy in the delay time given to a propagated signal. .
  • Fig. 6 is a block diagram showing an example of the timing signal generation part of an IC tester formed as one IC chip (in this example, a large-scale integrated circuit LSI), which gives a highly accurate delay time to a propagated signal.
  • One IC chip 1 includes a first semiconductor circuit unit 1 including a certain delay circuit and a second semiconductor circuit unit 2 including another logic circuit or the like that does not need to have high accuracy of a delay time given to a signal to be propagated. It is formed in a state separated on 0. A predetermined operating voltage is supplied to each of the first and second semiconductor circuit sections 1 and 2 from a common power source (not shown).
  • the circuit is configured to delay the signal input to the circuit for a predetermined time and output it.However, the number of delay circuits that need to provide a high-precision delay time may be increased or decreased as necessary. Needless to say.
  • the four delay circuits may have different or different delay time forces s applied to the propagating signal, and each delay circuit is configured to independently delay the input signal. Alternatively, the delay may be configured to be delayed by an arbitrary combination of a plurality of delay circuits.
  • the signal path for one of the delay circuits need not be one, for example, a plurality of signal paths mosquito s connected to one delay circuit, so as to delay by entering a logic signal (pulse signal) of different phases Even if configured for multiple signals
  • the configuration may be such that the path is connected to a portion where the delay time of one delay circuit is different.
  • the delay circuit formed as a MOS ⁇ IC may not have a predetermined delay time due to manufacturing variations, and therefore, it is necessary to provide a highly accurate delay time.
  • a delay time adjustment circuit 4 is inserted on the input side, the output side, or both, and the delay time given to the signal by each delay circuit is adjusted to a predetermined value. In FIG. 6, the delay time adjustment circuit 4 is inserted into the input / output sides of the respective delay circuits, and the delay time adjustment circuit 4 is inserted only when it is necessary to actually insert the delay time adjustment circuit 4.
  • FIG. 7 shows an example of the delay time adjustment circuit 4. Since each delay time adjustment circuit 4 may have the same circuit configuration, FIG. 7 shows one of the delay time adjustment circuits 4 on the output side as a substitute.
  • the delay time adjusting circuit 4 has four parallel signal paths between its input terminal T 1 and its output terminal T 2, and these signal paths are connected to the output terminal T 2 via the selector 6. .
  • the first signal path is directly connected to the selector 6 and supplies the input signal to the selector 6 as it is.
  • the second signal path has one logic gate element 5 functioning as a delay element in the signal path, and supplies an input signal to the selector 6 with a delay of one delay element.
  • the third signal path has two serially connected logic gate elements 5 acting as delay elements in the signal path, and supplies an input signal to the selector 6 with a delay by the delay time of the two delay elements.
  • 4th signal path acts as delay element 3
  • a logic gate element 5 connected to the selector 6 in its signal path, and supplies an input signal to the selector 6 with a delay of three delay elements.
  • the delay time adjusting circuit 4 having the above configuration is connected to the input terminal (one of IN 1 to IN 4) of the corresponding signal path of the first semiconductor circuit section 1 via the delay circuit and to the input of the second semiconductor circuit section 2.
  • the propagation delay time of the input signal up to the end is measured, the measured value of the delay time is compared with a reference value, and a signal path having a delay time corresponding to the difference value is selected by the selector 6.
  • the purpose is to adjust the delay time of a signal passing through the semiconductor circuit unit 1 to a predetermined value or an approximate value thereof.
  • the minimum unit of delay time that can be adjusted is one logic gate Since the delay time is caused by the element (delay element) 5, it is impossible to correct a delay time smaller than this. Therefore, there is a disadvantage that the delay time can be corrected only in steps, and the delay time cannot be set with a fine resolution.
  • the heat generation power of the second semiconductor circuit section 2 changes. s changes and its temperature changes.
  • the temperature of the second semiconductor circuit section 2 changes, the temperature of the first semiconductor circuit section 1 on the same chip also changes. Therefore, the CM OS ⁇ IC power s ' of the delay circuit included in the first semiconductor circuit section 1
  • the delay time given to the propagating signal fluctuates relatively largely in response to the temperature change. Of course, the propagation delay time changes even if the heat generation amount of the first semiconductor circuit unit 1 itself changes.
  • FIG. 8 is a graph showing a state in which the delay time T pd force of the delay circuit of the first semiconductor circuit unit 1 fluctuates due to a change in the power consumption P 2 of the second semiconductor circuit unit 2 and, therefore, a change in the temperature T 2 thereof. . From this graph, it can be seen that as the power consumption of the second semiconductor circuit unit 2 ⁇ 2 (therefore, the temperature ⁇ 2 ) increases, the delay time T pd of the delay circuit composed of the CMOS and IC of the first semiconductor circuit unit 1 increases. It can be seen that the force increases.
  • the conventional delay time adjustment circuit does not have a means for correcting the propagation delay time following the temperature fluctuation that changes momentarily during the operation as described above, and thus provides a highly accurate delay time. I could't do that.
  • FIG. 9 shows the power supply voltage supplied to the first semiconductor circuit section 1.
  • 6 is a graph showing a state in which the delay time T pd of the delay circuit of the first semiconductor circuit section 1 fluctuates due to the fluctuation of ⁇ 1. From this graph, as the power supply voltage E 1 becomes higher, the CMOS circuit is configured. It can be seen that the delay time T pd of the delayed circuit decreases.
  • the conventional delay time adjustment circuit does not include a means for correcting the propagation delay time by following such a change in the power supply voltage during operation, and therefore, it is possible to provide a highly accurate delay time. Did not.
  • the delay circuit formed by the MO S ⁇ IC has difficulty varying delay time force? Relatively large give signals that are propagated by temperature variation or voltage variation, or In addition, the propagation delay time is degraded by changes over time, so frequent calibration (calibration) must be performed. However, it is not possible to correct the propagation delay time by following the temperature and voltage fluctuations that change every moment during operation with only calibration. Therefore, there was a drawback that a highly accurate delay time could not be stably provided.
  • An object of the present invention is to provide a delay time correction circuit that can correct a propagation delay time following a temperature change or a voltage change that changes during operation. It is intended to provide a semiconductor integrated circuit device which can be provided as an integrated circuit.
  • a first semiconductor circuit unit including at least one logic element and including a circuit that needs to provide a highly accurate delay time to a signal to be propagated, and a first semiconductor circuit unit And a second semiconductor circuit unit, which does not need to have high accuracy of a delay time given to a signal to be propagated, is integrally formed as one semiconductor integrated circuit, and drives the semiconductor ⁇ ! Circuit.
  • a semiconductor integrated circuit device including a first power supply, wherein the first power supply drives the second semiconductor circuit unit and drives the first semiconductor circuit unit including a circuit which needs to provide the highly accurate delay time.
  • An output voltage variable second power supply is formed integrally with a circuit in the first semiconductor circuit section which needs to provide a highly accurate delay time, and detects a delay time of a signal propagating through this circuit.
  • a delay time monitor circuit for transmitting the high-precision delay time detected by the delay time monitor circuit.
  • the first semiconductor circuit unit and the second semiconductor circuit unit A level conversion circuit for matching the amplitude of the logic signal to the voltages of the second power supply and the first power supply for driving the first body circuit section and the second semiconductor circuit section respectively is provided. .
  • a first semiconductor circuit unit including at least one logic element and including a circuit that needs to provide a highly accurate delay time to a signal to be propagated
  • Two second semiconductor circuit units which are provided before and after the semiconductor circuit unit and do not need to have high accuracy in the delay time given to a signal to be propagated, are integrally formed as one semiconductor integrated circuit.
  • the semiconductor integrated circuit device including a first power supply for driving the semiconductor integrated circuit, it is necessary to drive the two second semiconductor circuit units by the first power supply and to provide the highly accurate delay time.
  • a second power supply that outputs a variable output voltage for driving a first semiconductor circuit section including a circuit, and a second power supply that is integrally formed near a circuit in the first semiconductor circuit section that needs to provide a highly accurate delay time.
  • a delay time monitor circuit for detecting a delay time of a signal propagating in a path, and a propagation delay time of a circuit which needs to provide the high-precision delay time detected by the delay time monitor circuit.
  • a power supply control circuit for controlling an output voltage of the second power supply so as to have a delay time of, and a power control circuit inserted between the first semiconductor circuit portion and the second semiconductor circuit portion of the preceding stage, and the amplitude of a logic signal is A first level conversion circuit for matching the voltages of the second power supply and the first power supply for driving the first semiconductor circuit section and the second semiconductor circuit section, respectively; A second power supply that is inserted between the second semiconductor circuit and the second power supply to match the amplitude of the logic signal to the voltages of the second power supply and the first power supply that drive the first semiconductor circuit and the second semiconductor circuit, respectively; Delay correction including level conversion circuit A semiconductor integrated circuit device having a circuit is provided, and the above object is achieved.
  • the power supply control circuit detects a phase difference between the delay time of the delay time monitor circuit and a reference delay time, and controls the voltage of the second power supply so that the phase difference becomes zero.
  • the is the reference clock signal is used in the semiconductor integrated circuit, a delay to a reference clock signal and the force s the power supply control circuit which is delayed the reference clock signal and by the delay time monitoring circuit as the input signal of the delay time monitor circuit
  • Each is given as a time monitor signal.
  • a plurality of circuits which need to provide a plurality of high-precision delay times are formed in the first semiconductor circuit portion. One is provided in common for circuits that require a delay time.
  • the circuit of the first semiconductor circuit unit which needs to provide a high-precision delay time has a circuit configuration in which a plurality of logic gate elements are cascaded.
  • the delay time monitor circuit is configured to apply a delay time equal to a cycle of a reference clock signal in the semiconductor A product circuit to a propagating logic signal, and the power supply control circuit sets the reference delay time as the reference delay time. The period of the reference clock signal is used.
  • the first semiconductor circuit section, the second semiconductor circuit section, the delay time monitor circuit, and the level conversion circuit are integrally formed as a CMOS (CMOS IC). It may be integrally formed as a CMOS and IC including the circuit.
  • FIG. 1 is a block diagram showing a circuit configuration of an embodiment of a semiconductor integrated circuit according to the present invention.
  • FIG. 2 is a circuit connection diagram showing one signal path of the semiconductor integrated circuit device of FIG. 1 and specifically showing first and second two level conversion circuits.
  • FIG. 3 is a circuit connection diagram showing the ON / OFF state of CMOS FET constituting the second level conversion circuit of FIG.
  • FIG. 4 is a circuit connection diagram specifically showing an example of the delay circuit connected to the semiconductor integrated circuit device of FIG.
  • FIG. 5 is a time chart showing the relationship between the clock signal input to the delay circuit of FIG. 4 and the clock signal delayed by this delay circuit.
  • FIG. 6 is a block diagram showing a circuit configuration of an example of a conventional semiconductor integrated circuit device.
  • FIG. 7 is a circuit connection diagram showing an example of the delay time adjusting circuit provided in the semiconductor integrated circuit device of FIG. CT / JP96 / 03875
  • FIG. 8 is a characteristic diagram showing the relationship between the delay time T pd of the delay circuit included in the first semiconductor circuit unit of the semiconductor integrated circuit device of FIG. 6 and the power consumption P 2 of the second semiconductor circuit unit.
  • FIG. 9 is a characteristic diagram showing the relationship between the delay time T pd of the delay circuit included in the first semiconductor circuit portion of the semiconductor integrated circuit device of FIG. 6 and the power supply voltage E1.
  • a delay circuit of a timing signal generation circuit of a parenthesis is a MOS-IC, in particular, a CMOS MOS IC. It is needless to say that the present invention is not limited to these cases.
  • parts and elements corresponding to those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted unless necessary.
  • FIG. 1 is a block diagram showing a circuit configuration of an embodiment of an integrated circuit device provided with a delay error correction circuit according to the present invention, which is formed as one IC chip (LSI chip in this embodiment).
  • the IC chip 10 includes a first semiconductor circuit unit 1 including a delay circuit constituted by a CMOS and an IC for giving a highly accurate delay time to a signal to be propagated, and a first semiconductor circuit unit 1.
  • first and second level conversion circuits inserted between the input side and output side of the first semiconductor circuit section 1 and the two second ⁇ body circuit sections 2-1 and 2-2, respectively. 12 and 13 are included.
  • the first body circuit section 1, the two second semiconductor circuit sections 211 and 2_2, and the first and second level conversion circuits 12 and 13 are separated from each other. In this state, it is formed as one CMOS / IC.
  • the power supply for driving the IC chip 10 is divided into a first power supply 7 having a normal constant output voltage and a second power supply 8 having a variable output voltage.
  • the semiconductor circuit units 2-1 and 2-2 are driven, and the first semiconductor circuit unit 1 including the delay circuit is driven by the second power supply 8.
  • this A delay time monitor circuit for detecting a propagation delay time of a signal propagating through the delay circuit of the first semiconductor circuit section is integrally formed, and the first semiconductor circuit detected by the delay time monitor circuit is further formed.
  • the power supply control circuit 9 controls the output voltage of the second power supply 8 so that the difference is obtained by comparing the delay time of the unit 1 with a reference value (reference delay time) so that the difference becomes zero. It is provided outside.
  • n number, n is an integer of 1 or more
  • each delay circuit is composed of a plurality of cascaded CMOS logic gate elements.
  • the number of delay circuits that need to provide a high-precision delay time is increased or decreased as needed.
  • the n delay circuits may be different or the same in terms of the delay time 5 ′ given to the propagating signal, and each delay circuit may delay the input signal independently. It may be configured, or may be configured to delay by a combination of arbitrary plural delay circuits. Also, there is no need for one signal path for one delay circuit. For example, multiple signal paths are connected to one delay circuit, and logic signals (pulse signals) with different phases are input and delayed. Or a configuration in which a plurality of signal paths are connected to portions of one delay circuit having different delay times. Incidentally, the input side or the output side of the first semiconductor circuit section 1, or both, even if it is referenced by the delay time adjustment circuit is used in the conventional example explained with 4 force 5 'connected to 6, It need not be connected.
  • the control of the second power supply 8 by the power supply control circuit 9 provided outside the IC chip 10 is performed by the delay time monitor circuit 3 provided near the delay circuit of the first semiconductor circuit section 1.
  • the delay time monitor signals S a and S b supplied the change in the delay time from the delay time monitor circuit 3, first supplied to the first half-conductor circuit 1 2
  • the power supply voltage E2 of the power supply 8 is changed in a direction to cancel the detected change in the delay time.
  • each delay circuit is composed of a plurality of cascade-connected logic gates having a CMOS structure. Since it is composed of elements, a logic gate circuit with the same configuration or the same configuration as a representative one of these delay circuits is used as a delay time monitor circuit 3 at an appropriate place in the first semiconductor circuit section 1. Form integrally.
  • Reference logic signal supplied to the input of the delay time monitor circuit 3 for example, a clock pulse signal
  • the delay time monitor circuit 3 for example, a clock pulse signal
  • the delay time monitor signals S a and S b supplied to the circuit 9 detects the phase difference of the delay time monitor signals S a and S b in the power supply control circuit 9, a second of this phase difference is supplied to the first semiconductor circuit section 1 to be zero It controls the power supply voltage E 2 of the power supply 8.
  • the delay time monitor circuit 3 is provided close to each delay circuit of the first semiconductor circuit section 1, the fluctuation of the delay time of each delay circuit can be detected, but the fluctuation of the individual delay time of each delay circuit can be detected.
  • the operating voltage must be independently supplied from the second power supply 8 to each delay circuit.
  • the circuit configuration becomes considerably complicated. Since the IC chip 10 is a small element, the area occupied by the first semiconductor circuit section 1 is even smaller. As a result of the experiments by the present inventors, it was found that merely providing one common delay time monitor circuit 3 at an appropriate position of a plurality of delay circuits in the first semiconductor circuit section 1 sufficiently changed the delay time of each delay circuit. it has been found that the force s that can be canceled.
  • one delay time monitor circuit 3 common to all the delay circuits is provided, and a delay time monitor circuit is provided for each of the delay circuits, which greatly simplifies the entire circuit configuration.
  • a plurality of delay time monitor circuits smaller than the number of delay circuits may be provided.
  • the delay time T pd of the delay circuit constituted by the CMOS IC of the first semiconductor circuit section 1 is equal to the second semiconductor circuit section 2-1. 2 2 power P 2 force s changes in, if the temperature T 2 is changed, changes as shown in FIG. 8, also supplied from the first ⁇ body circuit section 1 to the second power supply circuit 8 operates
  • the delay time Tpd of the delay circuit changes as shown in FIG. 9 (FIG. 9 shows the relationship between the delay time Tpd and the power supply voltage E1. The relationship between the power supply voltage E2 and the delay time Tpd is also the same).
  • the delay time of the delay time monitor circuit 3 provided in the vicinity of the delay circuit changes similarly to the delay time T pd of the delay circuit. Therefore, according to the circuit configuration of the above embodiment, the second power source 8 so that the phase difference of the delay time monitor signals S a and S b supplied from the delay time monitor circuit 3 by the power control circuit 9 becomes zero port Since the power supply voltage E 2 of the second semiconductor circuit unit 2 _ 1, 2 _ 2 is controlled, the power consumption P 2 power 5 ′ of the second semiconductor circuit unit 2-1, 2-2, for example, increases, thereby The power supply of the second power supply 8 supplied to the first semiconductor circuit section 1 by the power supply control circuit 9 when the delay time T pd of the delay circuit of the first semiconductor circuit section 1 increases due to the increase of the temperature T 2 of the second semiconductor circuit section 1 Control is performed so that the voltage E 2 becomes higher.
  • the delay time T pd of the delay circuit of the first semiconductor circuit section 1 decreases. Therefore, the increase in the delay time of the delay circuit of the first semiconductor circuit section 1 is immediately canceled and returned to the predetermined delay time. As a result, a highly accurate delay time can always be stably given to a signal propagating through the delay circuit of the first semiconductor circuit section 1, and a desired timing signal can be obtained with high accuracy.
  • FIG. 2 shows the first and second levels inserted between the first semiconductor circuit unit 1 and the two first and second second semiconductor circuit units 2-1 and 2-2 in the above embodiment.
  • FIG. 6 is a circuit connection diagram showing one specific example of conversion circuits 12 and 13; These first and second level conversion circuits 12 and 13 are connected to the first semiconductor circuit section 1 and the second semiconductor circuit sections 2-1 and 2-2 by separate first power sources 7 having different output voltages. This is provided so that the and the second power supply 8 can operate satisfactorily without adversely affecting each other.
  • FIG. 2 shows the circuit components (1, 2, 1, 2, 2, 12, 13) associated with one of the signal paths in the embodiment shown in FIG.
  • the circuit portion related to the road may have the same configuration, and is not shown.
  • FIG. 2 shows the first and second level conversion circuits 1 when the output voltage E1 of the first power supply 7 and the variable output voltage E2 of the second power supply 8 have a relationship of E1> E2.
  • 2 shows specific examples of 2 and 13.
  • the first level conversion circuit 12 is a CMOS comprising a series circuit of a p-channel MOS FETQ 1 and an n-channel MOS FETQ 2 in which the base electrode and the drain electrode are connected in common.
  • a drain electrode to each other consists of a series circuit of a p-channel MOS.
  • FET Q3 and the n-channel MO S ⁇ FETs Q 4 which are connected in common, respectively. Since the second semiconductor circuit section 2-1 in the preceding stage is energized by the first power supply 7, the amplitude of its output signal (pulse signal) is substantially equal to the voltage E1 of the first power supply 7.
  • the pulse signal of the second semiconductor circuit section 2-1 at the preceding stage is applied to the gate electrode of the first inverter of the first level conversion circuit 12, where the polarity is inverted and the gate signal of the second inverter is inverted. Supplied to the electrode.
  • the pulse signal whose polarity has been inverted and returned to the original polarity again in the second member is supplied to the delay circuit of the first semiconductor circuit section 1.
  • the second level conversion circuit ⁇ 2 since the second level conversion circuit ⁇ 2 is energized by the second power supply 8, the amplitude of the pulse signal output from the first level conversion circuit 12 is substantially equal to the voltage E 2 of the second power supply 8. This means that the pulse signal is converted into a pulse signal having an amplitude suitable for signal processing in the first semiconductor circuit unit 1 which is also energized by the second power supply 8.
  • the second level converting circuit 1 p-channel MO S ⁇ FET Q5 and n-channel base electrodes of the drain electrode connected together in common, respectively MO S - a series circuit of a F ETQ 6 CMO S C MO S structure consisting of a series circuit of the FETs Q 7 and the n-channel M0 S ⁇ FETQ s - and a third inverter evening structure, which also p-channel base electrodes of the drain electrode connected together in common, respectively M 0 S
  • a first output circuit having a CMOS structure comprising a series circuit of a p-channel MOS.FETQ 9 and an n-channel MOS S.FETQ i 0 having drain electrodes commonly connected to each other;
  • a second output circuit having a CMOS structure including a series circuit of a p-channel M ⁇ S FETQ 11 and an n-channel MOS FETQ i 2 having drain electrodes commonly connected, The first and second output circuits of these CMOS
  • Third output of Inbata is supplied to the n-channel M 0 S ⁇ FETs Q 1 2 Total Ichisu electrodes of the input and the second output circuit of the fourth Inba Ichita, also, the output of the fourth Inba one data is first output Supplied to the base electrode of the n-channel MO S ⁇ FETQ io of the circuit.
  • the first and second output circuits of the positive feedback amplifier only one of the MOS FETs is in operation, and the supplied pulse signal is amplified and output.
  • FIG. 3 shows the third and fourth members when a pulse signal delayed by a predetermined time by the delay circuit of the first semiconductor circuit unit 1 is input to the second level conversion circuit 13 shown in FIG. in the circuit connection diagram showing the pulse signals at the output of the polarity and the M OS ⁇ FETQ 5 ⁇ Q 12 oN constituting these circuits (0 n) // off (off) operation of the first ⁇ Pi second output circuit is there.
  • a positive polarity pulse signal (hereinafter referred to as an LZH signal) delayed by a predetermined time by the delay circuit of the first semiconductor circuit unit 1 is input to the input terminal IN of the second level conversion circuit 13
  • the polarity of the pulse signal is inverted by the third member energized by the second power supply 8 to become a negative polarity pulse signal (hereinafter, referred to as an HZL signal), which is also energized by the second power supply 8
  • the amplitude of this HZL signal is substantially equal to the voltage E 2 of the second power supply 8.
  • the L ZH signal (having an amplitude substantially equal to the voltage E 2 of the second power supply 8) whose polarity has been inverted again by the fourth inverter and returned to the original polarity is a positive signal which is energized by the first power supply 7. It is supplied to the gate electrode of the n-channel MOS FETQ 10 of the first output circuit of the feedback amplifier. Accordingly, the M0 gate electrode of the S ⁇ FETs Q 9 and Q 1 0 of the first output circuit LZH signal is supplied, hand, MOS ⁇ FETs Q 1 1 and Q i 2 of the gate of the second output circuit - DOO electrostatic H signals are supplied to the fences.
  • the positive feedback amplifier energized by the first power supply 7 amplifies the input LZH signal to an amplitude substantially equal to the voltage E1 of the first power supply 7 and outputs the amplified signal.
  • the LZH signal input to the second level conversion circuit 13 is a pulse having an amplitude suitable for signal processing in the second semiconductor circuit unit 2-2 at the subsequent stage similarly energized by the first power supply 7. It has been converted into a signal. That is, the level is converted and supplied to the output terminal OUT.
  • FIG. 2 shows the first and second level conversion circuits 12 and 12 when the output voltage E1 of the first power supply 7 and the variable output voltage E2 of the second power supply 8 have a relationship of E1> E2.
  • a specific example of 13 is shown, a similar circuit configuration is used in the case of E ⁇ ⁇ 2 as well.
  • the first and second level conversion circuits 12 and 13 can be realized. Moreover, both are force s connection of the first level conversion circuit 1 2 to the first power source 7 and the second power source 8 in FIG. 1, the first level conversion circuit 1 2 a first power supply 7 and a second power supply 8
  • a circuit configuration in which the second level conversion circuit 13 is driven by a power supply that drives the second semiconductor circuit 1 and the first and second level conversion circuits 12 and 13 are driven by both. Since there may be a circuit configuration driven by both the power supply 7 and the second power supply 8, FIG. 1 shows a comprehensive connection diagram including modified examples thereof.
  • FIG. 4 shows a specific example of the delay time monitor circuit 3 integrally formed in the first semiconductor circuit section 1.
  • each of the delay circuits in the first semiconductor circuit section 1 is composed of a plurality of cascade-connected logic gate elements having a CMOS structure.
  • a logic gate circuit having the same configuration or the same configuration as one delay circuit is integrally formed as a delay time monitor circuit 3 at an appropriate place in the first semiconductor circuit section 1.
  • the delay time monitor circuit 3 shown in FIG. 4 has the same circuit configuration as one of the delay circuits in the first semiconductor circuit section 1, and is composed of a plurality of logic gate elements G1 to Gn. It is configured.
  • these logic gate elements are inverters formed as CMOS ICs, and the reference logic signal supplied to the input terminal IN, in this example, the reference clock signal CLK: Is output from the output terminal OUT with the same polarity after a predetermined time delay. It is assumed that the reference clock signal CLK has a period T as shown in FIG. 5A.
  • Power control circuit 9 includes a phase comparator, in this phase comparing unit, and the reference clock signal CLK supplied as the delay time monitor evening signals S a, is delayed a predetermined time by the delay time monitoring circuit 3 and the output terminal OUT detecting the phase difference between the reference clock signal CLK supplied as the delay time monitor signal S b from.
  • the target value of the delay time is set so that the delay time monitor circuit 3 outputs the input reference clock signal CLK with a propagation delay time equal to its cycle T. Shall be.
  • the power supply control circuit 9 can use the cycle T of the reference clock CLK as the reference delay time Tr .
  • the phase difference ⁇ becomes a negative value. - 1, the power consumption power of 2-2 s less, thus indicating that the temperature is low.
  • the phase difference may be obtained without detecting the values of the propagation delay time T pd and the reference delay time T r .
  • the second semiconductor circuit section 2 1, 2 2 power P 2 force s decrease in, whereby the second semiconductor circuit section 2 1, 2 - 2 of temperature T 2 is lower connexion first
  • the power supply control circuit 9 detects the power supply voltage E 2 of the second power supply 8 supplied to the first semiconductor circuit section 1 at the detected position. Lower according to the value of phase difference ⁇ .
  • the delay time monitor circuit 3 of the first semiconductor circuit section 1 and therefore the delay time T pd of each delay circuit increases.
  • the decrease in the delay time of each delay circuit of the first semiconductor circuit unit 1 is immediately canceled, and the delay time is returned to the predetermined set delay time.
  • a signal that propagates through the delay circuit of the first semiconductor circuit section 1 can always be given a stable delay time with high precision, and a desired timing signal can be obtained with high precision.
  • the force timing described in the case where the present invention is applied to a timing generation circuit of an IC test apparatus is described as an example.
  • a timing circuit composed of a semiconductor integrated circuit that needs to provide a highly accurate delay time other than the four circuits It can also be applied to various circuits including semiconductor integrated circuits other than IC test equipment, which need to provide a high-precision delay time. . That is, the present invention can be applied to various semiconductor circuits in which a propagating logic signal generates a delay force even if it is not a delay circuit, and the same operation and effect can be obtained.
  • the circuit configuration of the IC chip 10 is not limited to the one shown in FIG.
  • the delay time adjustment circuit 4 described in the conventional example of FIG.
  • the first power supply 7, the second power supply 8, and the power supply control circuit 9 are provided outside the IC chip 10, but the second power supply 8 and the power supply control circuit 9 are provided inside the IC chip 10. In this case, since it can be manufactured as one IC chip 10 including the second power supply 8 and the power supply control circuit 9, the manufacturing efficiency is good and the cost can be reduced.
  • the first semiconductor circuit unit including the circuit that needs to provide a high-precision delay time, and the second semiconductor circuit that does not need to provide the high-precision delay time And a first power supply having a constant output voltage for driving the IC chip.
  • the integrated circuit device includes a circuit that needs to provide the above-described highly accurate delay time.
  • a variable output voltage for driving the semiconductor circuit section is provided integrally with a second power supply and a circuit that needs to provide the above-described high-precision delay time, and is provided for detecting a delay time of a signal propagating through this circuit.
  • the propagation delay time of the delay time monitor circuit and the circuit which needs to provide the above-described highly accurate delay time detected by the delay time monitor circuit is always set to the reference value (reference delay time). 2 power supply Since a delay error correction circuit including a power supply control circuit for controlling the input voltage is provided, a circuit for providing a highly accurate delay time of the first semiconductor circuit portion detected by the delay time monitor circuit is required. When the delay time fluctuates from the reference value, the power supply control circuit controls the second power supply to return the delay time of the delay time monitor circuit to the reference value. Therefore, regardless of changes in the temperature and aging of the IC chip or fluctuations in the power supply voltage, the delay time of the circuit that needs to provide a highly accurate delay time of the first semiconductor circuit is controlled to be always constant. Therefore, the propagation delay time of a signal propagating through a circuit that needs to provide the above-described high-precision delay time is almost always constant and stabilized.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dispositif à circuits intégrés à semi-conducteurs pouvant en permanence donner aux signaux un temps de retard approprié, sans tenir compte des fluctuations de la température ou de la tension de fonctionnement. Le dispositif comprend une première section circuit à semi-conducteur (1) qui nécessite une précision du temps de retard donné aux signaux; deux secondes sections à semi-conducteur (2-1, 2-2) qui ne nécessitent pas de précision du temps de retard, situées aux extrémités avant et arrière de la section (1); et une première alimentation (7) qui entraîne les deux secondes sections. Le dispositif comprend également un circuit de correction de l'erreur de retard, qui comporte une seconde alimentation variable (8) permettant de piloter la première section; un dispositif de surveillance du temps de retard (3) formé d'une pièce avec la première section (1), qui permet de détecter le temps de retard des signaux se propageant dans le circuit; un circuit de commande de l'alimentation (9), qui commande la tension de sortie de la seconde alimentation (8), de façon que le temps de retard de la propagation dans la première section détecté par le dispositif de surveillance (3) puisse toujours devenir un temps de référence; et un premier et un second circuit de conversion de niveaux qui sont reliés entre la première section et les secondes sections avant et arrière, de façon à régler l'amplitude des signaux logiques sur la tension de la seconde et de la première alimentation qui pilotent respectivement la première et les secondes sections circuits à semi-conducteur.
PCT/JP1996/003875 1995-12-28 1996-12-27 Dispositif a circuits integres a semi-conducteurs, comportant un circuit de correction de l'erreur de retard WO1997024806A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19681271T DE19681271T1 (de) 1995-12-28 1996-12-27 Integriertes Halbleiterschaltungselement mit Verzögerungsfehler-Korrekturschaltung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7/343291 1995-12-28
JP34329195 1995-12-28

Publications (1)

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WO1997024806A1 true WO1997024806A1 (fr) 1997-07-10

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KR (1) KR19980702516A (fr)
CN (1) CN1176713A (fr)
DE (1) DE19681271T1 (fr)
WO (1) WO1997024806A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102142272A (zh) * 2010-01-29 2011-08-03 海力士半导体有限公司 半导体器件
JP2011227937A (ja) * 2011-08-16 2011-11-10 Fujitsu Ltd 電源電圧調整装置、記録媒体および電源電圧調整方法
US8063509B2 (en) 2007-03-20 2011-11-22 Fujitsu Limited Power supply voltage adjusting apparatus, recording medium, and power supply voltage adjusting method
US8125261B2 (en) 2003-07-22 2012-02-28 Nec Corporation Multi-power source semiconductor device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3587702B2 (ja) * 1998-10-20 2004-11-10 富士通株式会社 Ｄｌｌ回路を内蔵する集積回路装置
US7453258B2 (en) * 2004-09-09 2008-11-18 Formfactor, Inc. Method and apparatus for remotely buffering test channels
US8281158B2 (en) * 2007-05-30 2012-10-02 Lapis Semiconductor Co., Ltd. Semiconductor integrated circuit
CN106059545B (zh) * 2016-06-16 2018-09-21 电子科技大学 一种用于低功耗流水线的时序控制电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139025U (fr) * 1985-02-19 1986-08-28
JPH02296410A (ja) * 1989-05-11 1990-12-07 Mitsubishi Electric Corp 遅延回路
JPH04213213A (ja) * 1990-12-10 1992-08-04 Fujitsu Ltd ディジタル集積回路装置
JPH04102079U (ja) * 1991-02-14 1992-09-03 株式会社アドバンテスト 可変遅延装置
JPH05259845A (ja) * 1991-11-01 1993-10-08 Hewlett Packard Co <Hp> 遅延線

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139025U (fr) * 1985-02-19 1986-08-28
JPH02296410A (ja) * 1989-05-11 1990-12-07 Mitsubishi Electric Corp 遅延回路
JPH04213213A (ja) * 1990-12-10 1992-08-04 Fujitsu Ltd ディジタル集積回路装置
JPH04102079U (ja) * 1991-02-14 1992-09-03 株式会社アドバンテスト 可変遅延装置
JPH05259845A (ja) * 1991-11-01 1993-10-08 Hewlett Packard Co <Hp> 遅延線

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8125261B2 (en) 2003-07-22 2012-02-28 Nec Corporation Multi-power source semiconductor device
US8063509B2 (en) 2007-03-20 2011-11-22 Fujitsu Limited Power supply voltage adjusting apparatus, recording medium, and power supply voltage adjusting method
CN102142272A (zh) * 2010-01-29 2011-08-03 海力士半导体有限公司 半导体器件
US9000820B2 (en) 2010-01-29 2015-04-07 SK Hynix Inc. Semiconductor device
JP2011227937A (ja) * 2011-08-16 2011-11-10 Fujitsu Ltd 電源電圧調整装置、記録媒体および電源電圧調整方法

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DE19681271T1 (de) 1998-01-22
KR19980702516A (ko) 1998-07-15
CN1176713A (zh) 1998-03-18

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