WO1997007466A1 - Dispositif d'application specifique pouvant etre reconfigure - Google Patents

Dispositif d'application specifique pouvant etre reconfigure Download PDF

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Publication number
WO1997007466A1
WO1997007466A1 PCT/GB1996/002013 GB9602013W WO9707466A1 WO 1997007466 A1 WO1997007466 A1 WO 1997007466A1 GB 9602013 W GB9602013 W GB 9602013W WO 9707466 A1 WO9707466 A1 WO 9707466A1
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WO
WIPO (PCT)
Prior art keywords
data
micro
controller
input
programmable
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Application number
PCT/GB1996/002013
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English (en)
Inventor
Kenneth Austin
Original Assignee
Kenneth Austin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kenneth Austin filed Critical Kenneth Austin
Priority to AU67504/96A priority Critical patent/AU6750496A/en
Publication of WO1997007466A1 publication Critical patent/WO1997007466A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

  • the present invention relates to a re ⁇ configurable integrated circuit, with particular emphasis on a re-configurable application specific device, but without limitation to same.
  • U.K. Patent Application No. 9503003 describes a configurable semi-conductor integrated circuit, eg. a digital signal processor, in which an area thereof is formed with a plurality of cells each having at least one function and interconnections with at least some other said cells. At least some of the plurality of cells have interconnections which are electrically selectable as to their conduction state, and at least some of the plurality of cells have interconnections which are pre-wired. Each cell has two or more possible configurations, each configuration being defined by the cell function and/or its interconnection with other cells according to cell configuration data. Means is provided for storing configuration data for at least two cell configurations (per cell) and means is provided to enable one of the possible cell configurations according to the cell configuration data selected. A control circuit is utilised to pass configuration data, program data and coefficients to an array memory and memory caches.
  • a control circuit is utilised to pass configuration data, program data and coefficients to an array memory and memory caches.
  • the previou ⁇ architecture had fixed programming circuitry and the present invention aims to provide improvements in flexibility and efficiency.
  • the present invention provides a re ⁇ configurable semi-conductor integrated circuit device of the type which, as made, comprises a plurality of cells which have two or more possible configurations, means for storing configuration data for at least two cell configurations (per cell), data memory for the array and input/output channels for the device, the device further comprising a programmable micro-controller and a direct memory access engine controlled by the programmable micro-controller to control the transfer of data to and/or from:- the array memory; the input/output channels and the means storing configuration data.
  • the direct memory engine (hereinafter referred to as a DMA engine) directly generates internal and external addresses transferring a preselected number of data words.
  • the micro ⁇ controller directs data transfer, while the DMA engine is responsible for transferring data at high speed. It receives its instructions from the micro-controller and transfers data in the background.
  • a further advantageous feature is the provision of interrupt logic that can be used to interrupt the main flow of data and cause a new set of transfers to occur. Interrupts may be generated either by an off- chip signal, and on-chip signal or an on-chip event caused by an interrupt timer. It is preferred that the micro-controller ha ⁇ a dedicated interrupt circuit for each of the logic blocks. For this purpose each logic block feeds a control node of the micro-processor which can be used to signify the end of a task or request for more data etc. More preferably still, the micro ⁇ controller has a timer for each logic block and the timer can be used to time a process that the block is performing thereby freeing the block from dedicating some of its cells to this task. A further alternative is for external signals to be routed into the micro ⁇ controller from the input to replace or be used in conjunction with internally generated interrupts.
  • the device further comprise ⁇ a plurality of programmable sequencers which can be programmed individually or in combination to generate a sequence of configuration data storage addresses.
  • a further feature of the invention comprise ⁇ a programmable input/output by which the band width allocated for user input/output of configuration data and program data can be altered according to the application of the device.
  • Figure 1 is a schematic block diagram showing the principal element ⁇ of an integrated circuit device according to the present invention
  • FIG. 2 illustrates the device of Figure 1 in further detail
  • FIG. 3 is a schematic diagram showing in further detail one cell of the logic block for the device of Figures 1 and 2,
  • Figure 4 i ⁇ a ⁇ chematic illu ⁇ trating the logic blocks and the associated circuitry with address line and active cache selection
  • Figure 5 is a schematic of the logic blocks showing the details of the circuitry utilised for selecting and updating the memory caches
  • Figure 6 i ⁇ a block diagram illustrating a ⁇ ingle bit ⁇ equencer for use in the device of Figures 1 and 2
  • Figure 7 is a schematic circuit diagram for a programmable modulo counter as used in the single bit sequencer
  • FIG 8 i ⁇ a flow chart illustrating part of a normal program flow
  • the present invention is described in the context of an integrated circuit intended for an application specific device, one embodiment of which i ⁇ a reconfigurable signal processor (DSP).
  • a device according to Figure 1 comprises a plurality of logic function units or cells 2, programmable inputs and outputs 4 for the logic function units, and a configuration cache 3 storing configuration data for the logic function units.
  • the configuration cache 3 may be on-chip in immediate proximity to the logic function units as part of an array of logic blocks, as illu ⁇ trated in Figure ⁇ 3, 4 and 5.
  • the processor also comprise ⁇ a data memory 5, a micro-sequencer 7, a micro-controller 9, a direct memory acces ⁇ engine 11 and programmable input/output 13 for the DMA engine and micro-controller.
  • each logic block 21 comprises a matrix array of cells, for example an array of 8 x 8 cell.
  • Figure 3 illustrates schematically in further detail one of the logic cells of one of the logic blocks 21. It comprises a cell function unit 22 incorporating the desired logic circuitry, an 8 bit decoder 23, four-8 bit configuration caches 25(a-d), comprising programmable memory (RAM) , two-8 bit ROM configuration memories 27a, b representing two alternative boot-up configurations for the cell function unit.
  • the cells will be di ⁇ po ⁇ ed in group ⁇ , eg. columns which show the same boot up configuration - representing primary functions, eg.
  • decode cells eg. the row of cells at the bottom in Figures 4 and 5.
  • decoder 23 controls the input and output multiplexers and the cell function unit, either in terms of logic function or interconnect function by way of connection line ⁇ 30, 32, 34 and 36, according to which of the configuration cache ⁇ 25a-d, 27a, b is selected.
  • an instruction bus 35 connects into the logical unit from the decode cells and also serve ⁇ to control the function of the logic function unit.
  • caches 25 and 27 have four and two address lines respectively. Addressing of the logic block and transferring of data is described further with reference to Figure 2, 4 and 5.
  • the micro-controller 9 instructs the DMA engine 11 having taken its program instruction ⁇ from the programmable input 13 via multiplexer 41.
  • the program data is read in along program data bus 43.
  • Figure 6 illu ⁇ trates one of eight single bit sequencer ⁇ for the device which make up the micro- sequencer 7 of Figure 1.
  • Each comprise ⁇ , in the illustrated embodiment a four-input multiplexer 601 receiving global clock inputs - CLK1, CLK2, CLK3 and CLK4.
  • modulo counters there are two modulo counters, one, 100, operating on frequency and the other, 101, operating on ⁇ equence length. These are set from the icro- controller.
  • a sequence can be stored in each of RAM block ⁇ A and B.
  • Mean ⁇ i ⁇ provided for selecting which of the sequences is to be output on a global cache line.
  • Figure 6 illustrates the output for global cache-line Gl.
  • Gl there are eight po ⁇ sible outputs G1-G8 for the whole device.
  • the global lines G1-G8 are illustrated in Figure 4. Signals from the 8 global lines can be fed to each logic block 21.
  • the global lines connect with 3, 8 input multiplexer 105, 107 and 109.
  • the micro-controller controls the multiplexers 105, 107, 109 according to the selection of either RAM A or RAM B which has associated read enable, write enable, and data transmission lines 210, 212 and 214 respectively.
  • Outputs from the three multiplexers 105, 107, 109 feed to decoder 115.
  • decoder 115 Furthermore, there are node connections in each logic block and global connections with each logic block, x bu ⁇ es, these can provide a signal source for selection by the multiplexer as an alternative to or in addition to signal ⁇ on lines G1-G8.
  • Decoder 15 has six output lines which connect with the respective RAM and ROM memory cache ⁇ by horizontal connection line ⁇ .
  • Figure 5 illu ⁇ trates for one logic block the circuitry utilised for selecting and/or updating the cache ⁇ of the array of cells.
  • Co-ordinate selection of any of the caches 25a-d, 27a, b of a cell is possible utilising the two decoders 502, 504 by way of the DMA engine 11 under the instruction ⁇ from the micro ⁇ controller.
  • Transferring of data to the selected caches is by data bus 506 with data being passed by the DMA engine under instruction from the micro-controller. Where the data is to be written to the number of the caches is to be same, this can be written simultaneously to these caches.
  • the micro-controller has as ⁇ ociated interrupt logic which can be u ⁇ ed to interrupt the main flow of data and cau ⁇ e a new set of transfers to occur. Interrupts may be generated by either an off-chip signal, for example through the programmable input 13, an on-chip signal or an on-chip event caused by an interrupt timer.
  • the micro-controller 9 ha ⁇ a dedicated interrupt circuitry for each of the 32 array blocks. Furthermore each block can generate in interrupt by taking a control node on the micro-controller high, ⁇ ignalling the end of a task or request for more data. Alternatively, the micro-controller can use one of its 32 timers (not illustrated), ie.
  • External ⁇ ignal ⁇ can be routed into the micro-controller which can replace or be u ⁇ ed in conjunction with other generated interrupt ⁇ .
  • a further feature of the invention i ⁇ the u ⁇ e of programmable input/output which allow ⁇ the de ⁇ igner to allocate pins, ie. band width, to apportion user input/output for configuration data and program data.
  • a program addres ⁇ generator 150 is provided - ⁇ ee Figure 2.
  • a multiplexer 41 sets the band width for the configuration data and the program data under control of the micro-controller 9, in conjunction with the DMA engine and the respective address bus ⁇ es 154, 156 and 158.
  • the band width/number of pins allocated to configuration and program data re ⁇ pectively can be allocated according to the requirement ⁇ for the task to be performed.
  • the program input determines whether one of the prewired ROM configuration 27a, 27b is to be selected. If it is then the required control information is sent to the array as indicated by box 100. If not, then the required configuration data is written to say the first memory cache 25a and the fir ⁇ t logic block. The timer will be set for that logic block a ⁇ will the interrupts for that logic block. The process i ⁇ repeated for all the logic block ⁇ with the configuration data to be written to the blocks being determined by the architecture specification data, whilst the timers and interrupts are set according to control flow information.
  • FIG. 9 illustrates a interrupt service routine in more detail from which it will be seen that interrupts may be array interrupts 61 or timer interrupts 63. There is one for each logic block.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

Un dispositif à circuits intégrés à semiconducteurs, pouvant être reconfiguré comprend une pluralité de cellules (2) présentant deux ou plusieurs configurations possibles, des moyens (3) pour mémoriser les données de configuration d'au moins deux configurations de cellules (par cellule), une mémoire de données (5) pour le groupement de cellules, et des canaux d'entrée/sortie pour le dispositif. Des améliorations peuvent être réalisées en matière de souplesse et de performance en prévoyant un micro-contrôleur programmable (9) et un moteur d'accès direct à la mémoire (11) commandé par le micro-contrôleur programmable pour commander le transfert de données en provenance et/ou à destination de la mémoire d'ensemble; les canaux d'entrée/sortie et les moyens mémorisant les données de configuration. La reconfiguration peut être initiée par des signaux d'interruption générés par un signal non incorporé à la puce, un signal incorporé à la puce ou un évènement se produisant sur la puce. Plusieurs séquenceurs programmables sont utilisés pour générer une séquence d'adresses de mémorisation de données de configuration.
PCT/GB1996/002013 1995-08-17 1996-08-19 Dispositif d'application specifique pouvant etre reconfigure WO1997007466A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU67504/96A AU6750496A (en) 1995-08-17 1996-08-19 Re-configurable application specific device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9516877.9 1995-08-17
GB9516877A GB2304438A (en) 1995-08-17 1995-08-17 Re-configurable application specific device

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WO1997007466A1 true WO1997007466A1 (fr) 1997-02-27

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GB (1) GB2304438A (fr)
WO (1) WO1997007466A1 (fr)

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WO2000017772A2 (fr) * 1998-09-23 2000-03-30 Infineon Technologies Ag Bloc-materiel configurable
WO2000039685A1 (fr) * 1998-12-23 2000-07-06 Axis Ab Voie memoire flexible
US6724833B1 (en) 1996-06-10 2004-04-20 Infineon Technologies Ag Method and apparatus for communicating information
CN100339826C (zh) * 2004-06-24 2007-09-26 富士通株式会社 处理器和半导体器件
WO2010056719A2 (fr) 2008-11-12 2010-05-20 Microchip Technology Incorporated Microcontrôleur avec matrice logique configurable
US11185505B2 (en) 2010-05-28 2021-11-30 Purdue Research Foundation Delivery of agents to inflamed tissues using folate-targeted liposomes

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DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (fr) 1996-12-27 2011-06-22 Richter, Thomas Procédé pour le transfert dynamique automatique de processeurs à flux de données (dfp) ainsi que de modules à deux ou plusieurs structures cellulaires programmables bidimensionnelles ou multidimensionnelles (fpga, dpga ou analogues)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6292916B1 (en) 1998-12-10 2001-09-18 Lucent Technologies Inc. Parallel backtracing for satisfiability on reconfigurable hardware
JP3444216B2 (ja) 1999-01-28 2003-09-08 日本電気株式会社 プログラマブルデバイス
US6442732B1 (en) 1999-04-21 2002-08-27 Lucent Technologies, Inc. Virtual logic system for solving satisfiability problems using reconfigurable hardware
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JP2004506261A (ja) 2000-06-13 2004-02-26 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト パイプラインｃｔプロトコルおよびｃｔ通信
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
EP1514193B1 (fr) 2002-02-18 2008-07-23 PACT XPP Technologies AG Systemes de bus et procede de reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
EP1974265A1 (fr) 2006-01-18 2008-10-01 PACT XPP Technologies AG Procédé de définition de matériels

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Cited By (12)

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Publication number Priority date Publication date Assignee Title
US6724833B1 (en) 1996-06-10 2004-04-20 Infineon Technologies Ag Method and apparatus for communicating information
WO2000017772A2 (fr) * 1998-09-23 2000-03-30 Infineon Technologies Ag Bloc-materiel configurable
WO2000017772A3 (fr) * 1998-09-23 2000-07-27 Siemens Ag Bloc-materiel configurable
US7028162B2 (en) 1998-09-23 2006-04-11 Siemens Aktiengesellschaft Configurable processing block capable of interacting with external hardware
WO2000039685A1 (fr) * 1998-12-23 2000-07-06 Axis Ab Voie memoire flexible
CN100338585C (zh) * 1998-12-23 2007-09-19 安讯士公司 用于数据传输的方法和装置
CN100339826C (zh) * 2004-06-24 2007-09-26 富士通株式会社 处理器和半导体器件
WO2010056719A2 (fr) 2008-11-12 2010-05-20 Microchip Technology Incorporated Microcontrôleur avec matrice logique configurable
WO2010056719A3 (fr) * 2008-11-12 2010-07-08 Microchip Technology Incorporated Microcontrôleur avec matrice logique configurable
CN102209959A (zh) * 2008-11-12 2011-10-05 密克罗奇普技术公司 具有可配置逻辑阵列的微控制器
US9946667B2 (en) 2008-11-12 2018-04-17 Microchip Technology Incorporated Microcontroller with configurable logic array
US11185505B2 (en) 2010-05-28 2021-11-30 Purdue Research Foundation Delivery of agents to inflamed tissues using folate-targeted liposomes

Also Published As

Publication number Publication date
GB2304438A (en) 1997-03-19
AU6750496A (en) 1997-03-12
GB9516877D0 (en) 1995-10-18

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