GB2391671B - Embedded memory blocks for programmable logic - Google Patents

Embedded memory blocks for programmable logic

Info

Publication number
GB2391671B
GB2391671B GB0324461A GB0324461A GB2391671B GB 2391671 B GB2391671 B GB 2391671B GB 0324461 A GB0324461 A GB 0324461A GB 0324461 A GB0324461 A GB 0324461A GB 2391671 B GB2391671 B GB 2391671B
Authority
GB
United Kingdom
Prior art keywords
programmable logic
memory blocks
embedded memory
embedded
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0324461A
Other versions
GB0324461D0 (en
GB2391671A (en
Inventor
Tony Ngai
Sergey Shumarayev
Wei-Jen Huang
Rakesh H Patel
Tin Lai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Priority claimed from GB0016223A external-priority patent/GB2351824B/en
Publication of GB0324461D0 publication Critical patent/GB0324461D0/en
Publication of GB2391671A publication Critical patent/GB2391671A/en
Application granted granted Critical
Publication of GB2391671B publication Critical patent/GB2391671B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
GB0324461A 1999-07-02 2000-06-30 Embedded memory blocks for programmable logic Expired - Fee Related GB2391671B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14214199P 1999-07-02 1999-07-02
GB0016223A GB2351824B (en) 1999-07-02 2000-06-30 Embedded memory blocks for programmable logic

Publications (3)

Publication Number Publication Date
GB0324461D0 GB0324461D0 (en) 2003-11-19
GB2391671A GB2391671A (en) 2004-02-11
GB2391671B true GB2391671B (en) 2004-04-28

Family

ID=30117073

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0324461A Expired - Fee Related GB2391671B (en) 1999-07-02 2000-06-30 Embedded memory blocks for programmable logic

Country Status (1)

Country Link
GB (1) GB2391671B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2286737A (en) * 1994-02-17 1995-08-23 Pilkington Germany No 2 Ltd ASIC with multiple internal reconfiguration stores
GB2304438A (en) * 1995-08-17 1997-03-19 Kenneth Austin Re-configurable application specific device
GB2310064A (en) * 1996-02-09 1997-08-13 Hewlett Packard Co Hybrid programmable logic
WO1997030517A1 (en) * 1996-02-16 1997-08-21 Actel Corporation Flexible, high-performance static ram architecture for field-programmable gate arrays
WO1998010517A1 (en) * 1996-09-03 1998-03-12 Xilinx, Inc. Fpga architecture having ram blocks with programmable word length and width and dedicated address and data lines
EP1005163A2 (en) * 1998-11-18 2000-05-31 Altera Corporation Programmable logic device architectures
WO2000036748A1 (en) * 1998-12-15 2000-06-22 Lattice Semiconductor Corporation Fpga integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2286737A (en) * 1994-02-17 1995-08-23 Pilkington Germany No 2 Ltd ASIC with multiple internal reconfiguration stores
GB2304438A (en) * 1995-08-17 1997-03-19 Kenneth Austin Re-configurable application specific device
GB2310064A (en) * 1996-02-09 1997-08-13 Hewlett Packard Co Hybrid programmable logic
WO1997030517A1 (en) * 1996-02-16 1997-08-21 Actel Corporation Flexible, high-performance static ram architecture for field-programmable gate arrays
WO1998010517A1 (en) * 1996-09-03 1998-03-12 Xilinx, Inc. Fpga architecture having ram blocks with programmable word length and width and dedicated address and data lines
EP1005163A2 (en) * 1998-11-18 2000-05-31 Altera Corporation Programmable logic device architectures
WO2000036748A1 (en) * 1998-12-15 2000-06-22 Lattice Semiconductor Corporation Fpga integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode

Also Published As

Publication number Publication date
GB0324461D0 (en) 2003-11-19
GB2391671A (en) 2004-02-11

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20170630