GB2350456A - Data processing - Google Patents
Data processing Download PDFInfo
- Publication number
- GB2350456A GB2350456A GB9911101A GB9911101A GB2350456A GB 2350456 A GB2350456 A GB 2350456A GB 9911101 A GB9911101 A GB 9911101A GB 9911101 A GB9911101 A GB 9911101A GB 2350456 A GB2350456 A GB 2350456A
- Authority
- GB
- United Kingdom
- Prior art keywords
- data
- reconfiguring
- processing apparatus
- data processing
- handling elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Abstract
A processor 12 (which is an array of programmable logic devices 14) can be reconfigured using reconfiguring programs, e.g. RP#1, to process data from a memory MEM in various ways.
Description
2350456 JKHIMPG/KLBIJPC'rECH 0:\SPECSMPG\Jpctech DATA PROCESSING APPARATUS
AND MEETHOD This invention relates to data processing apparatus and methods, and in particular, those which involve programmable data handling elements.
It is known to provide data handling elements, e.g. logic circuits, in processors at the time of manufacture which can be activated by fuses to replace faulty data handling elements in order to reduce the number of processors which are rejected during testing after manufacture. In one sense, processors of this type can be considered to be programmable.
Another known type of data processing apparatus comprises an array of logic devices whose interconnections, and possibly also their respective functions, can be programmed in the same manner as the class of processors mentioned above in order to provide a processor tailored for performing a certain function in hardware (at a processing speed greater than that achievable by a normal, generic processor using its collection of relatively low-level processing elements (multipliers, accumulators, registers, etc). Such application specific integrated circuits ASICs are desirable for computationally intensive tasks such as crypto analysis, data sorting, and data matching.
A drawback with the two kinds of programmable processors described above is that they are not reprogrammable or reconfigurable. To overcome this lack of flexibility, a third type of processing apparatus comprises an array of programmable logic devices whose functions and interconnections are electronically reconfigurable. For example, the programmable logic devices (PLDs) can each comprise a look-up table which is addressed by the signals on its respective inputs to return an appropriate data item as the desired combination of input signals. A PLD of this kind can be reprogrammed merely by storing different data in its look-up table.
The present invention seeks to provide improved configurable data processing apparatus and -improved methods "of reconfiguring such apparatus.
2 According to a first aspect, the invention provides data processing apparatus comprising a plurality of data handling elements which can be configured to process data in a plurality of ways, and storage means storing information which can be used by the data processing apparatus to guide reconfiguration of the data handling elements.
The data processing device according to the invention is flexible in that it is reconfigurable and it has the advantage that reconfiguration can be achieved more easily by reference to the data in the storage means. The data processing apparatus can be arranged to process data in a first manner using a first configuration of the data handling devices and in a second manner using a second configuration of the data handling devices. The data processed may be data which are output data produced by a configuration of the data handling devices.
In a preferred embodiment, either or both of the functions and the interconnections of the data handling elements are configurable. The data handling elements can be electronically programmable logic devices constituting, for example, a field programmable gate array (FPGA).
The processing apparatus may comprise reconfiguring means for reconfiguring the data handling elements. The reconfiguring means may be arranged to refer to a library of reconfiguring schemes resident in the storage means in order to reconfigure the data handling elements such that the data processing apparatus is capable of processing data in a plurality of ways. The reconfiguring means may have selecting means for selecting a reconfiguring scheme.
The data processing apparatus may be reconfigured to perform a range of data processing activities including searching, sorting, collating, matching, compiling, decompiling, crypto analysis and mathematical data manipulation.
The invention also provides computing equipment including the data processing apparatus.
3 Further, the invention provides a method of reconfiguring data processing apparatus comprising a plurality of data handling elements which are reconfigurable to process data in a plurality of ways, the method comprising retrieving a reconfiguring scheme from data storage and using the scheme to reconfigure the data handling elements. The method also embraces the set-up of the data processing apparatus to perform an initially selected function.
The method may include the step of selecting the scheme from a plurality of reconfiguring schemes. There may be a library of such schemes each providing instructions for reconfiguring the data handling elements to allow the data processing apparatus to process data in a specific manner or to perform a certain function.
In a preferred method, the reconfiguring scheme is used to reconfigure either or both of data handling element interconnections and functions.
The invention additionally provides a method of using data processing apparatus to process data in a first manner, reconfiguring the data processing apparatus according to the method previously described, and using the data processing apparatus to process data in a second manner. The data processed in the second manner may be output data produced by the data processing apparatus in the first manner.
According to yet a further aspect, the invention provides data storage means storing a program which can be processed by reconfiguring means to cause it to reconfigure a plurality of reconfigurable data handling devices so that they process data in a different manner.
Preferably, the data storage means stores a plurality of programs, each of which can be executed by the reconfiguring means to reconfigure the data handling devices differently.
An embodiment of the invention will now be described, by way of example only, with reference to the accompanying figure which is a block diagram of reconfigurable data processing apparatus.
4 As shown in figure 1, the data processing system 10 comprises an electronically programmable logic device array (EPLDA) 12, which comprises an array of programmable logic devices (PLDs) 14, whose functions and interconnections 18 are reconfigurable or reprogrammable. For example, the logic function performed by a PLD could be determined by a look-up table addressed by the inputs to the PLD, its logic function being reprogrammable by altering the contents of the look-up table.
Thus, the EPLDA 12 is configured to perform a specific function and exchanges data and instructions for the performance of this function over bus 20, as will be described later. The EPLDA is particularly useful for computationally intensive processing since it can be configured to perform in hardware tasks which a generic data processor would have to perform in software at lower speed (due to instruction fetching, instruction loading, cache considerations, etc.).
When it is desired to reconfigure EPLDA 12 to perform a different function or to process data in a different manner, reconfiguring unit (RU) 22 reprograms the functions of, and the interconnections between, the PLDs in the EPLDA 12 as necessary over bus 24.
In order to facilitate the process of reconfiguration, the RU 22 retrieves over bus 26 an appropriate reconfiguring program (RP) from a memory 24 which stores a number of reconfiguring programs RM, IN, each of which provides instructions which enable the RU 22 to reconfigure the EPLDA 12 to perform a specific data processing function or to process data in a specific manner. The RU 22 selects the RP which is required and performs it to implement the necessary changes in the EPLDA.
It will be appreciated that the reconfiguration procedure is greatly facilitated by the use of the RPs which enable rapid reconfiguration to take place. When it is desired to change the function of the EPLDA 12 again, the RU 22 runs a further, different RP.
In the embodiment shown in figure 1, the EPLDA 12 is connected via bus 20 to memory device 2 1. The EPLDA 12 is arranged to receive and process input data from the memory device 21 to produce output data which is transferred back to the memory device 21 for storage. The EPLDA 12 may then be reconfigured as described above and begin processing data from the memory device 21 in a different manner. Of course, the reconfigured EPLDA 12 could retrieve from the memory device 21 output data which was generated by the EPLDA in a previous configuration and operate on it in order to produce new Output data.
6
Claims (10)
1. Data processing apparatus comprising a plurality of data handling elements which can be configured to process data in a plurality of ways and storage means storing information which can be used by the data processing apparatus to guide the reconfiguration of the data handling elements.
2. Data processing apparatus according to claim 1, wherein the storage means contains a plurality of programs, each of which can be used by the apparatus to configure the data handling elements to process data in a different way.
3. A method of reconfiguring re-data processing apparatus comprising a plurality of data handling elements which are configurable to process data in a plurality of ways, the method comprising retrieving a reconfiguring scheme from data storage and using the scheme to reconfigure the data handling elements.
4. A method of processing data using data processing apparatus comprising a plurality of data handling elements which are reconfigurable to process data in a plurality of ways, the method comprising processing first data using the apparatus to produce second data, reconfiguring the apparatus using the method of claim 3, and processing third data using the apparatus to produce fourth data.
5. A method of processing data according to claim 4, wherein the third data comprises at least a part of the second data.
6. A program which can be processed by reconfiguring means to cause it to reconfigure a plurality of reconfigurable data handling devices so that they process data in a different manner.
7 7. Reconfigurable data processing apparatus, substantially as hereinbefore described with reference to the accompanying figure.
8. A method of reconfiguring data processing apparatus, substantially as hereinbefore described with reference to the accompanying figure.
9. A method of processing data, substantially as hereinbefore described with reference to the accompanying figure.
10. A reconfiguring program, substantially as hereinbefore described with reference to the accompanying figure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9911101A GB2350456A (en) | 1999-05-13 | 1999-05-13 | Data processing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9911101A GB2350456A (en) | 1999-05-13 | 1999-05-13 | Data processing |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9911101D0 GB9911101D0 (en) | 1999-07-14 |
GB2350456A true GB2350456A (en) | 2000-11-29 |
Family
ID=10853372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9911101A Withdrawn GB2350456A (en) | 1999-05-13 | 1999-05-13 | Data processing |
Country Status (1)
Country | Link |
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GB (1) | GB2350456A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1487107A2 (en) * | 2003-06-10 | 2004-12-15 | Altera Corporation | Apparatus and methods for communicating with programmable logic devices |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2286737A (en) * | 1994-02-17 | 1995-08-23 | Pilkington Germany No 2 Ltd | ASIC with multiple internal reconfiguration stores |
GB2300504A (en) * | 1995-05-02 | 1996-11-06 | Xilinx Inc | Programmable switch for logic array input/output signals |
EP0748051A2 (en) * | 1995-06-05 | 1996-12-11 | International Business Machines Corporation | System and method for dynamically reconfiguring a programmable gate array |
GB2304438A (en) * | 1995-08-17 | 1997-03-19 | Kenneth Austin | Re-configurable application specific device |
US5629637A (en) * | 1995-08-18 | 1997-05-13 | Xilinx, Inc. | Method of time multiplexing a programmable logic device |
EP0785630A2 (en) * | 1996-01-17 | 1997-07-23 | Hewlett-Packard Company | Time multiplexing in field programmable gate arrays |
GB2333625A (en) * | 1998-01-21 | 1999-07-28 | Lucent Technologies Inc | Virtual logic system for reconfigurable hardware |
-
1999
- 1999-05-13 GB GB9911101A patent/GB2350456A/en not_active Withdrawn
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2286737A (en) * | 1994-02-17 | 1995-08-23 | Pilkington Germany No 2 Ltd | ASIC with multiple internal reconfiguration stores |
GB2300504A (en) * | 1995-05-02 | 1996-11-06 | Xilinx Inc | Programmable switch for logic array input/output signals |
EP0748051A2 (en) * | 1995-06-05 | 1996-12-11 | International Business Machines Corporation | System and method for dynamically reconfiguring a programmable gate array |
GB2304438A (en) * | 1995-08-17 | 1997-03-19 | Kenneth Austin | Re-configurable application specific device |
US5629637A (en) * | 1995-08-18 | 1997-05-13 | Xilinx, Inc. | Method of time multiplexing a programmable logic device |
EP0785630A2 (en) * | 1996-01-17 | 1997-07-23 | Hewlett-Packard Company | Time multiplexing in field programmable gate arrays |
GB2333625A (en) * | 1998-01-21 | 1999-07-28 | Lucent Technologies Inc | Virtual logic system for reconfigurable hardware |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1487107A2 (en) * | 2003-06-10 | 2004-12-15 | Altera Corporation | Apparatus and methods for communicating with programmable logic devices |
EP1487107A3 (en) * | 2003-06-10 | 2006-06-14 | Altera Corporation | Apparatus and methods for communicating with programmable logic devices |
US7356620B2 (en) | 2003-06-10 | 2008-04-08 | Altera Corporation | Apparatus and methods for communicating with programmable logic devices |
CN101546354A (en) * | 2003-06-10 | 2009-09-30 | 阿尔特拉公司 | Apparatus and methods for communicating with programmable logic devices |
US7650438B2 (en) | 2003-06-10 | 2010-01-19 | Altera Corporation | Apparatus and methods for communicating with programmable logic devices |
US8190787B2 (en) | 2003-06-10 | 2012-05-29 | Altera Corporation | Apparatus and methods for communicating with programmable devices |
US8554959B2 (en) | 2003-06-10 | 2013-10-08 | Altera Corporation | Apparatus and methods for communicating with programmable devices |
US8719458B2 (en) | 2003-06-10 | 2014-05-06 | Altera Corporation | Apparatus and methods for communicating with programmable devices |
US9274980B2 (en) | 2003-06-10 | 2016-03-01 | Altera Corporation | Apparatus and methods for communicating with programmable devices |
CN101546354B (en) * | 2003-06-10 | 2016-09-07 | 阿尔特拉公司 | For the apparatus and method communicated with programmable logic device |
Also Published As
Publication number | Publication date |
---|---|
GB9911101D0 (en) | 1999-07-14 |
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WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |