WO1997005697A1 - Regulation de la puissance de sortie dans les emetteurs en salves - Google Patents

Regulation de la puissance de sortie dans les emetteurs en salves Download PDF

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Publication number
WO1997005697A1
WO1997005697A1 PCT/EP1996/003313 EP9603313W WO9705697A1 WO 1997005697 A1 WO1997005697 A1 WO 1997005697A1 EP 9603313 W EP9603313 W EP 9603313W WO 9705697 A1 WO9705697 A1 WO 9705697A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
power control
output
power
pcs
Prior art date
Application number
PCT/EP1996/003313
Other languages
English (en)
Inventor
Eduardo Bonilla Menendez
Juan Antonio Yuste Hernandez
Antonio Del Pino Juarez
Original Assignee
Alcatel Standard Electrica S.A.
Alcatel N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrica S.A., Alcatel N.V. filed Critical Alcatel Standard Electrica S.A.
Priority to AU67021/96A priority Critical patent/AU6702196A/en
Publication of WO1997005697A1 publication Critical patent/WO1997005697A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
    • H03G3/3047—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers for intermittent signals, e.g. burst signals

Definitions

  • This invention concerns power transmitters for radiofrequency signals in which the signal to be transmitted consists of bursts, consequently there are many periods when this signal is zero.
  • the power control presented here permits the mean power of the output signal to be kept constant and controlled during the bursts, irrespective of the relationship between the periods of burst transmission and the periods between bursts when the signal is zero.
  • This control is normally achieved by means of a power feedback loop.
  • This loop is based on detecting the output power of the final power amplifier, obtaining a signal proportional to this output power for comparison with a stable reference in a differential amplifier, the output of which generates a power control signal which is used to modify the gain in one of the amplifier stages.
  • the output power detector is usually a directional coupler with a load resistor and a rectifier. Afterwards there is a lowpass filter with a fairly narrow bandwidth such that the value obtained at its output does not fluctuate and therefore does not introduce amplitude modulation in the output signal.
  • burst transmitters the preceding principle is not applicable as such because the reading would be in error through calculating the mean value of output power taking into consideration the zero signal periods and would be further impaired when the system permits, according to the level of occupancy of the channels, the omission of bursts in the frame formed by the burst assembly.
  • This invention is intended for overcoming the drawbacks mentioned above in burst transmitters, the latter comprising a power amplifier stage whose gain is varied in accordance with a power control signal, means for sensing the output signal, a detector that produces a DC voltage signal proportional to the level of the sensed signal and a differential amplifier to generate the power control signal in proportion to the difference between the DC voltage from the detector and a reference voltage.
  • the power control signal mentioned is sampled in a sample-and-hold circuit using the active edges of a clock signal, these occurring only at the instants when there are burst signals to be transmitted and at a time subsequent to the start of each burst greater than the duration of the transient of the DC analogue voltage signal at the output of the detector.
  • - figure 1 shows a block diagram of an output power control circuit in accordance with the state of the art
  • - figure 2 is the output power control circuit according to the invention
  • FIG. 3 shows a circuit like the previous one but in which the attenuator employed is of the digital type
  • FIG. 4 shows time domain diagrams of various signals at points in the power control feedback loop.
  • PAS power amplification stage PAS, of variable gain, which receives an input signal Is and which boosts the power of the output signal Os by a determined factor termed the power gain.
  • a small sample of this output signal Os is taken by means of an output signal sensing circuit PS, which is applied to a power detector DET which, in turn, produces a baseband signal proportional to the mean power of the output signal Os, whereby this baseband signal can be subsequently used to perform control of the power in the output signal Os by means of a feedback process.
  • the output signal from the detector DET is applied to one of the inputs of a comparator COMP which receives, through its other input, a reference voltage Vref, the output signal from this comparator COMP being proportional to the difference between the two input signals, that coming from the detector DET and the reference voltage Vref.
  • This output signal from the comparator COMP is a power control signal PCS that is applied to the power amplifier stage PAS to vary its gain such that, by means of the feedback loop so formed, an increase in the mean power of the output signal Os results in a decrease in the gain of the preceding power amplifier stage PAS and, through this, a decrease in the power of the output signal that offsets the initial increment.
  • the output signal from the detector is practically a continuous signal, thereby avoiding the amplitude modulation of the output signal from the amplifier; nevertheless, this mean value of the detected output power is not correct since it does not depend only on the mean power of the bursts, but also on the actual presence of these bursts.
  • the output of each burst is not constant but depends on the occupancy level, or number of bursts present, in the transmitted frames.
  • Figure 2 shows the solution proposed by this invention in order to make the power control independent of the level of occupancy of the frames.
  • the power amplifier stage is formed by a non ⁇ linear power amplifier PA of fixed gain, preceded by a variable attenuator VA such that the overall gain of the assembly is also variable.
  • variable attenuator VA offers an attenuation that depends on the value of the power control signal PCS, it being approximately proportional to this value.
  • This attenuator consists of a PIN type diode connected between the signal line and ground, such that it presents a resistance to ground that depends on its bias voltage. The greater the forward bias voltage, the less the resistance presented to ground is and, consequently, the greater the attenuation presented to the signal being transmitted along the line is.
  • the power sensing circuit PS is formed by a two-line microstrip directional coupler.
  • the coupling loss of this device is, for the present case, 30 dB and it is loaded with a resistance R1 of 50 ⁇ .
  • the detector DET To the other extremity is connected the detector DET; at its input this has a highpass filter C1 , R2 with a cutoff frequency below the working frequency of the amplifier. Afterwards there is a detecting diode D and a lowpass filter C2, R3, the time constant of which is about ten times less than the duration of the bursts.
  • the output signal from this detector DET is applied to the inverting input of the comparator COMP, the non-inverting input being connected to the reference voltage Vref.
  • the output signal from this comparator COMP takes a value of 5 V, or logical 1 , when the output signal of the detector is less than the reference voltage, it being 0 V, or logical 0, otherwise.
  • the output signal of the aforementioned comparator COMP is applied to a sample-and-hold circuit SHC which, in this case, is formed by a digital up/down counter UDC and a digital-to-analogue converter DAC.
  • the digital up/down counter UDC receives, as a clock signal, a control signal CS consisting of pulses, the presence of which corresponds to the appearance of transmitted bursts and the width of which is equal to one half of burst duration. Thus, the falling edge of these pulses which is considered to be the clock active edge, coincides with the centre of each burst.
  • This digital up/down counter UDC also receives the output signal from the comparator COMP at its up/down count input. In this way the count value stored in it is increased by one unit when an active clock pulse edge appears, that is, in the centre of each burst, and, in addition, the output voltage of the detector DET is greater than the reference voltage Vref; otherwise there is a decrease.
  • This up/down counter UDC are applied to the digital- to-analogue converter DAC where an output voltage is produced that is proportional to the value stored in the up/down counter UDC mentioned and which is termed the power control signal PCS, as already stated.
  • This power control signal PCS is applied to the control input of the variable attenuator VA, which offers an attenuation in the incoming signal path which becomes greater as the power control signal increases.
  • the power control loop permits true control of the mean transmitted power calculated in each burst, irrespective of the appearance or not of a given burst without this affecting the mean value mentioned.
  • This also permits the filter employed for calculating the mean value of the transmitted power to have a much faster response, as can be seen in figure 4.c, and the control to be active for a very short time.
  • the output of the comparator COMP takes the values of logical 1 and 0 alternatively, which makes the power control signal PCS oscillate between two values, as can be seen from figure 4.d, the proximity of these two values becoming greater as the number of bits employed by the digital up/down counter UDC and by the digital-to- analogue converter DAC becomes greater.
  • a very large number of bits in the digital-to-analogue converter DAC permits the power of the output signal to be kept within a very narrow range, though it implies that the initial system response is very slow; this can be improved if the initial value of the counter is pre-established in accordance with calculations made which depend on the rest of the parameters of the loop.

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  • Control Of Amplification And Gain Control (AREA)
  • Transmitters (AREA)

Abstract

Cette invention concerne la régulation de la puissance de sortie dans les émetteurs en salves qui comportent un étage d'amplification de la puissance dont le gain varie en fonction d'un signal de régulation de puissance (PCS), un circuit de détection des signaux de sortie (PS), un détecteur (DET) qui génère un signal de tension en courant continu proportionnel au niveau du signal détecté et un comparateur (COMP) qui sert à générer un signal de régulation de puissance (PCS) proportionnel à la différence entre la tension en courant continu en provenance du détecteur (DET) et une tension de référence (Vref). On échantillonne le signal de régulation de puissance (PCS) dans un circuit échantillonneur (SHC) au moyen des fronts actifs d'un signal d'horloge (CS), ceux-ci ne se produisant qu'aux moments où des salves de signaux doivent être transmises et à un instant postérieur au démarrage de chaque salve intervenant après une durée supérieure à la durée de la transitoire du signal de tension analogue en courant continu à la sortie du détecteur.
PCT/EP1996/003313 1995-07-31 1996-07-26 Regulation de la puissance de sortie dans les emetteurs en salves WO1997005697A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU67021/96A AU6702196A (en) 1995-07-31 1996-07-26 Output power control in burst transmitters

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ES9501548 1995-07-31
ESP9501548 1995-07-31

Publications (1)

Publication Number Publication Date
WO1997005697A1 true WO1997005697A1 (fr) 1997-02-13

Family

ID=8291233

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1996/003313 WO1997005697A1 (fr) 1995-07-31 1996-07-26 Regulation de la puissance de sortie dans les emetteurs en salves

Country Status (4)

Country Link
AU (1) AU6702196A (fr)
MA (1) MA23954A1 (fr)
WO (1) WO1997005697A1 (fr)
ZA (1) ZA966509B (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0859463A2 (fr) * 1997-02-18 1998-08-19 Nec Corporation Equipement radio pour système à accès multiple à répartition dans le temps et circuit d'ajustement du niveau de sortie d'un synthétiseur
US5918369A (en) * 1996-04-10 1999-07-06 The Gillette Company Shaving system and method
US6452373B2 (en) * 2000-01-07 2002-09-17 The United States Of America As Represented By The United States National Aeronautics And Space Administration Transient voltage recorder
WO2004082135A3 (fr) * 2003-03-12 2005-01-20 Analog Devices Inc Commande de puissance en boucle fermee de signaux a enveloppe non constante par echantillonnage-blocage
EP1916766A2 (fr) * 2006-10-25 2008-04-30 EADS Deutschland GmbH Circuit de réglage

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969683A (en) * 1975-04-21 1976-07-13 Bell Telephone Laboratories, Incorporated Automatic level control circuit
JPS6090408A (ja) * 1983-10-24 1985-05-21 Toshiba Corp 自動レベル制御回路
JPS61173507A (ja) * 1985-01-29 1986-08-05 Nec Corp 自動レベル制御回路
EP0509733A2 (fr) * 1991-04-16 1992-10-21 Mitsubishi Denki Kabushiki Kaisha Amplificateur de puissance pour signaux RF
EP0535669A1 (fr) * 1991-10-01 1993-04-07 Matsushita Electric Industrial Co., Ltd. Emetteur pour signaux de type "burst"
EP0632585A1 (fr) * 1993-06-30 1995-01-04 Alcatel Telspace Système de commande de la polarisation d'un amplificateur
EP0688108A2 (fr) * 1994-06-15 1995-12-20 Mitsubishi Denki Kabushiki Kaisha Dispositif pour la commande de puissance d'émission dans un système AMRT

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969683A (en) * 1975-04-21 1976-07-13 Bell Telephone Laboratories, Incorporated Automatic level control circuit
JPS6090408A (ja) * 1983-10-24 1985-05-21 Toshiba Corp 自動レベル制御回路
JPS61173507A (ja) * 1985-01-29 1986-08-05 Nec Corp 自動レベル制御回路
EP0509733A2 (fr) * 1991-04-16 1992-10-21 Mitsubishi Denki Kabushiki Kaisha Amplificateur de puissance pour signaux RF
EP0535669A1 (fr) * 1991-10-01 1993-04-07 Matsushita Electric Industrial Co., Ltd. Emetteur pour signaux de type "burst"
EP0632585A1 (fr) * 1993-06-30 1995-01-04 Alcatel Telspace Système de commande de la polarisation d'un amplificateur
EP0688108A2 (fr) * 1994-06-15 1995-12-20 Mitsubishi Denki Kabushiki Kaisha Dispositif pour la commande de puissance d'émission dans un système AMRT

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 009, no. 240 (E - 345) 26 September 1985 (1985-09-26) *
PATENT ABSTRACTS OF JAPAN vol. 010, no. 384 (E - 466) 23 December 1986 (1986-12-23) *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5918369A (en) * 1996-04-10 1999-07-06 The Gillette Company Shaving system and method
US6029354A (en) * 1996-04-10 2000-02-29 The Gillette Company Shaving system and method
EP0859463A2 (fr) * 1997-02-18 1998-08-19 Nec Corporation Equipement radio pour système à accès multiple à répartition dans le temps et circuit d'ajustement du niveau de sortie d'un synthétiseur
EP0859463A3 (fr) * 1997-02-18 2000-01-05 Nec Corporation Equipement radio pour système à accès multiple à répartition dans le temps et circuit d'ajustement du niveau de sortie d'un synthétiseur
AU735507B2 (en) * 1997-02-18 2001-07-12 Nec Corporation Time division multiple access system radio equipment and synthesizer output level adjusting circuit
US6335925B1 (en) 1997-02-18 2002-01-01 Nec Corporation Time division multiple access system radio equipment and synthesizer output level adjusting circuit
US6452373B2 (en) * 2000-01-07 2002-09-17 The United States Of America As Represented By The United States National Aeronautics And Space Administration Transient voltage recorder
WO2004082135A3 (fr) * 2003-03-12 2005-01-20 Analog Devices Inc Commande de puissance en boucle fermee de signaux a enveloppe non constante par echantillonnage-blocage
US7353006B2 (en) 2003-03-12 2008-04-01 Analog Devices, Inc. Closed loop power control of non-constant envelope waveforms using sample/hold
EP2284996A1 (fr) * 2003-03-12 2011-02-16 MediaTek Inc. Contrôle de la puissance en boucle fermée de formes d'ondes à enveloppe non constante utilisant un échantillon/maintien
EP1916766A2 (fr) * 2006-10-25 2008-04-30 EADS Deutschland GmbH Circuit de réglage
EP1916766A3 (fr) * 2006-10-25 2010-09-15 EADS Deutschland GmbH Circuit de réglage

Also Published As

Publication number Publication date
ZA966509B (en) 1997-02-19
MA23954A1 (fr) 1997-04-01
AU6702196A (en) 1997-02-26

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