WO1997004541A2 - Multipoint to multipoint processing in a network switch having data buffering queues - Google Patents
Multipoint to multipoint processing in a network switch having data buffering queues Download PDFInfo
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- WO1997004541A2 WO1997004541A2 PCT/US1996/011918 US9611918W WO9704541A2 WO 1997004541 A2 WO1997004541 A2 WO 1997004541A2 US 9611918 W US9611918 W US 9611918W WO 9704541 A2 WO9704541 A2 WO 9704541A2
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- H—ELECTRICITY
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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Definitions
- - 2 - resources in a network switch may become unencumbered in a multipoint-to-multipoint switching scenario.
- the network switch includes a switch fabric, an input processing port connected between a plurality of input links and the switch fabric and having a plurality of data buffering queues, and an output processing port connected between the switch fabric and a plurality of output links and having a plurality of data buffering queues. All of the data buffering queues have a connection identification code, and the data buffering queues in the output processing port have a data cell processing code.
- the input processing port processes a data cell received on one of the input links by appending to the data cell a link number indicating the input link where the data cell arrived, a port number indicating the input processing port, and a connection identification code associated with a data buffering queue in the input processing port where the data cell will be buffered.
- the output processing port processes a data cell processed by the input processing port and transferred to the output processing port through the switch fabric by comparing the link number to a link number of a link connected to the output processing port, the port number to a port number of the output processing port, and the connection identification code to a connection identification code associated with a data buffering queue in the output processing port.
- the data cell is then stored in the data buffering queue in the output processing port according to a matching scheme between the link numbers, the port numbers, and the connection identification codes as dictated by the value of the data cell processing code.
- the output processing port matching scheme requires that the link - 1 -
- the present invention is generally related to network switching and, more particularly, to an apparatus and a method for unencumbering valuable switching resources in a network switch involved a multipoint-to-multipoint switching scenario.
- Telecommunications networks such as asynchronous transfer mode (ATM) networks are used for the transfer of audio, video, and other data.
- ATM networks deliver data by routing data units such as ATM cells from a source to a destination through switches.
- Switches typically include multiple input/output (I/O) ports through which ATM cells are received and transmitted. The appropriate output port to which a received ATM cell is to be routed to and thereafter transmitted from is determined based upon an ATM cell header.
- ATM cells from a variety of sources are transferred from multiple input queues to multiple output queues within a switch.
- valuable switching resources become unencumbered. Accordingly, it would be desirable to devise a scheme whereby valuable switching numbers, the port numbers, and the connection identification codes match in order for the data cell to be stored in the data buffering queue in the output processing port.
- the output processing port matching scheme requires that the link numbers, the port numbers, and the connection identification codes do not match in order for the data cell to be stored in the data buffering queue in the output processing port.
- This mechanism allows each output queue to receive a unique set of ATM cells from a variety of sources, wherein the ATM cells are transferred from multiple input queues to each output queue.
- the primary object of the present invention is to provide an apparatus and a method for unencumbering valuable switching resources in a network switch involved a multipoint-to-multipoint switching scenario.
- Fig. 1 is a block diagram of a network switch
- Fig. 2 illustrates the structure of an input queue
- Fig. 3 illustrates the structure of a scheduling list
- Fig. 4 shows the standard data bus format of a data cell
- Fig. 5 shows the internal switch data cell format of a converted data cell
- Fig. 6 shows the format of an input queue descriptor
- Fig. 7 shows the format of an output queue descriptor
- Fig. 8 contains a table indicating the different echo field codes and the corresponding output port processor functions associated with those codes.
- Fig. 9 shows a "No Echo" multipoint-to-multipoint switching scenario.
- a network switch 1 comprising a Data Crossbar 10, a Bandwidth Arbiter (BA) 12, a plurality of input port processors 14, a plurality of output port processors 16, and a plurality of Multipoint Topology Controllers (MTC) 18.
- the Data Crossbar 10 which may be an N x N crosspoint switch, is used for data cell transport and, in this particular embodiment, yields N x 670 Mbps throughput.
- the BA 12 controls switch interconnections, dynamically schedules momentarily unused bandwidth, and resolves multipoint-to-point bandwidth contention.
- Each input port processor 14 schedules the transmission of data cells to the Data Crossbar 10 from multiple connections.
- Each output port processor 16 receives data cells from the Data Crossbar 10 and organizes those data cells onto output links.
- a data cell 22 In order to traverse the switch 1, a data cell 22 first enters the switch 1 on a link 24 to an input port processor 14 and is buffered in a queue 26 of input buffers. The data cell 22 is then transmitted from the queue 26 of input buffers through the Data Crossbar 10 to a queue 28 of output buffers in an output port processor 16. From the queue 28 of output buffers, the data cell 22 is transmitted onto a link 30 outside of the switch 1 to, for example, another switch.
- each input port processor 14 includes a cell buffer RAM 32 and each output port processor 16 includes a cell buffer RAM 34.
- the cell buffer RAM's 32 and 34 are organized into the respective input and output queues 26 and 28. All data cells 22 in a connection pass must through a unique input queue 26 and a unique output queue 28 for the life of the connection. The queues 26 and 28 thus preserve cell ordering. This strategy also allows quality of service (“QoS”) guarantees on a per connection basis.
- QoS quality of service
- the Probe Crossbar 42 which in this particular embodiment is an N x N crosspoint switch, is used to transmit a multiqueue number from an MTC 18 to an output port processor 16.
- Each input port processor 14 includes a plurality of scheduling lists 47, each of which is a circular list containing input queue numbers for a particular connection.
- Each multiqueue number is derived from information provided to the MTC 18 from a scheduling list 47 in an input port processor 14.
- a multiqueue number identifies one or more output queues 28 to which a data cell may be transmitted when making a connection.
- An output port processor 16 uses the multiqueue number to direct a request message probe to the appropriate output queue or queues 28 and thereby determine if there are enough output buffers available in the output queue or queues 28 for the data cell.
- the XOFF Crossbar 44 which in this particular embodiment is an N x N crosspoint switch, is used to communicate "DO NOT SEND" type feedback messages from an output port processor 16 to an input port processor 14.
- the XOFF feedback messages are asserted to halt the transmission of request message probes through the Probe Crossbar 42 from an input port processor 14 to an output port processor 16, and thus put a scheduling list 47 within the receiving input port processor 14 in an XOFF state, meaning that the scheduling list 47 cannot be used to provide a multiqueue number.
- the scheduling list 47 remains in an XOFF state until receiving an XON message from the output port processor 16, as described below.
- An input port processor 14 responds to an asserted XOFF feedback message by modifying XOFF state bits in a descriptor of the scheduling list 47.
- the XOFF state bits prevent the input port processor 14 from attempting to send a request message probe from the input port processor 14 to the output port processor 16 until notified by the output port processor 16 that output buffers are available for a corresponding connection
- the "DO NOT SEND" type feedback messages also halt the transmission of data cells from an input port processor 14 to an output port processor 16 when sufficient buffer space is not available to receive data cells in the output port processor 16. In such a case, an input port processor 14 will not transmit any data cells through the Data Crossbar 10. An idle cell, containing a complemented cyclic redundancy check (CRC) calculation, is transmitted instead.
- CRC cyclic redundancy check
- the XON Crossbar 46 which in this particular embodiment is an N x N crosspoint switch, is used to communicate "ENABLE SEND" type feedback messages from an output port processor 16 to an input port processor 16. More particularly, the XON Crossbar 46 communicates an XON feedback message from an output port processor 16 to an input port processor 14. When an XOFF feedback message has been asserted by an output port processor 16 in response to a request probe message from an input port processor 14, the output port processor 16 sets a state bit in a queue descriptor of a corresponding output queue 28. When the number of data cells in that output queue 28 drops below an XON threshold, an XON message is sent from that output port processor 16 to the input port processor 14. The XON message enables the scheduling list 47 in the input port processor 14 to be used in the sending of request probe messages, and hence data cells.
- the Probe & XOFF communication paths operate in a pipelined fashion.
- an input port processor 14 selects a scheduling list 47, and information associated with that scheduling list 47 is used to determine the output port processor 16, or the output queue 28, to which a data cell will be transmitted. More particularly, a multiqueue number. which is derived from information provided to an MTC 18 from a scheduling list 47 in an input port processor 14, is transmitted from the MTC 18 to one or more output port processors 16 using the Probe Crossbar 42.
- Each output port processor 16 tests for buffer availability and asserts a "DO NOT SEND" type feedback message through the XOFF Crossbar 44 if output buffering is not available for that connection. If output buffering is available for that connection, the input port processor 14 transmits a data cell to one or more output queues 28 through the Data Crossbar 10.
- Each input port processor 14 within the switch 1 also includes a Switch Allocation Table (SAT) 20 for mapping bandwidth allocation.
- SAT's 20 are the basic mechanism behind the scheduling of data cells.
- Each SAT 20 includes a plurality of sequentially ordered cell time slots 50 and a pointer 52 which is always directed to one of the cell time slots 50. All of the pointers 52 in the switch 1 are synchronized such that at any given point in time each of the pointers 52 is directed to the same cell time slot 50 in the respective SAT 20 with which the pointer 52 is associated, e.g., the first cell time slot. In operation, the pointers 52 are advanced in lock-step, with each cell time slot 50 being active for 32 clock cycles at 50 MHz. When a pointer 52 is directed toward a cell time slot 50, an input port processor 14 uses the corresponding entry 51 in the cell time slot 50 to obtain a data cell for launching into the Data Crossbar 10.
- each SAT entry 51 point to a scheduling list 47.
- the contents of each (non-empty) entry in a scheduling list 47 consists of an input queue number. Each input queue number points to a input queue descriptor which contains state information that is specific to a particular connection. Each input queue descriptor, in turn, points to the head and the tail of a corresponding input queue 26, which contains data cells for transmission through the Data Crossbar 10. If a SAT entry 51 does not contain a pointer to a scheduling list, i.e. the SAT entry 51 is set to zero, then the corresponding cell time slot 50 in the SAT 20 has not been allocated and that cell time slot 50 is available for dynamic bandwidth.
- a SAT entry 51 does contain a pointer to a scheduling list 47 but no input queue number is listed in scheduling list 47, then there are no data cells presently available for transmission and the corresponding cell time slot 50 is also available for dynamic bandwidth. Any bandwidth that has not been allocated is referred to as dynamic bandwidth, which is granted to certain types of connections by the BA 12 so as to increase the efficiency of the switch 1.
- the switch 1 is configured to allow connections having different quality of service attributes to be managed in such a way that there is no interference between the characteristics of any connection with any other connection.
- an input port processor 14 manages each connection with a set of data structures that are unique for each connection.
- An input queue 26 is used to manage buffers.
- An input queue 26 consists of a group of one or more buf ers organized as a FIFO and manipulated as a linked list structure using pointers.
- Incoming data cells 22 are added (enqueued) to the tail of an input queue 26. Data cells which are sent to the Data
- Crossbar 10 are removed (dequeued) from the head of an input queue 26.
- the ordering of data cells is always maintained.
- the sequence of data cells that are sent to the Data Crossbar 10 is identical to that in which they arrived at an input port processor 14, although the time interval between departing data cells may be different than the time interval between arriving data cells.
- Fig. 2 illustrates the structure of an input queue 26.
- a scheduling list 47 is used to manage bandwidth.
- a scheduling list 47 consists of one or more input queue numbers organized as a circular list. As with input queues 26, scheduling lists 47 are manipulated as a linked list structure using pointers. Input queue numbers are added to the tail of a scheduling list 47 and removed from the head of a scheduling list 47.
- An input queue number can only appear once on any given scheduling list 47.
- input queue numbers can be recirculated on a scheduling list 47 by removing the input queue number from the head of the scheduling list 47 and then adding the removed input queue number back onto the tail of the scheduling list 47. This results in round-robin servicing of input queues 26 on a particular scheduling list 47.
- Fig. 3 illustrates the structure of a scheduling list 47.
- the first action performed by the input port processor 14 is to check the header of the data cell for errors and then to check that the data cell is associated with a valid connection.
- Cell header integrity is verified by computing a Header Error Check (HEC) on bytes in the header of a received data cell and then comparing the computed HEC to the HEC field in the header of the received data cell. If the computed HEC and the HEC field do not match, then there is a header error and the data cell will be dropped.
- HEC Header Error Check
- an input port processor 14 For each incoming data cell, an input port processor 14 will use VPI/VCI fields specified in the header of the data cell as an index into a translation table in the input port processor 14.
- the translation table correlates valid connections and input queue numbers.
- the input port processor 14 first checks to see if the data cell belongs to a valid connection; i.e. one that has been set up by switch control software. If the connection is valid, then the data cell will be assigned an input queue number from the translation table. If the connection is not valid, then the data cell will either be dropped or be assigned an exception input queue number from the translation table, which results in further processing of the data cell.
- Fig. 4 shows the standard data bus format of a data cell.
- Fig. 5 shows the internal switch data cell format of a converted data cell.
- an input queue number is used to point to a queue descriptor, which is a data structure containing state information that is unique to a particular connection.
- a queue descriptor for each queue in the switch 1; i.e. for both the input queues 26 in the input port processor 14 and the output queues 28 in the output port processor 16.
- the queue descriptors are maintained by switch control software.
- Fig. 6 shows the format of an input queue descriptor.
- Fig. 7 shows the format of an output queue descriptor.
- the input port processor 14 After a data cell is assigned an input queue number, the input port processor 14 will look at the corresponding queue descriptor for further information on how to process the data cell. The input port processor 14 will first try to assign a buffer for the data cell. If a buffer is available, then the data cell buffer number is enqueued to the tail of the queue and the data cell is written out to the cell buffer RAM 32. If there is no buffer available, the data cell is dropped and a statistic is updated.
- the input port processor 14 In addition to processing and buffering incoming streams of data cells, the input port processor 14 must transfer data cells from a cell buffer to one or more output port processors 16 through the Data Crossbar 10. The transfer of the data cells is performed through the use of the Probe Crossbar 20, the XOFF Crossbar 24, and the Data Crossbar 10, as previously described. Specifically, a multiqueue number, which is derived from information provided to an MTC 18 from a scheduling list 47 in an input port processor 14, is transmitted from the MTC 18 to one or more output port processors 16 using the Probe Crossbar 42. Each output port processor 16 then tests for buffer availability and asserts a "DO NOT SEND" type feedback message through the XOFF Crossbar 44 if output buffering is not available for that connection.
- the input port processor 14 transmits a data cell to one or more output queues 28 through the Data Crossbar 10. However, before any data cells are enqueued into any output queue 28, the output port processor 16 processes each data cell based on information contained in the trailer of the converted data cell.
- connection identification (Conn ID) field 60 contains an arbitrary code that is assigned by the switch control software indicating 1 of 8 possible data flow paths upon which to perform a cell mask.
- an input port processor 14 When processing a data cell, an input port processor 14 will insert the code from the connection identification field 60 of the input queue descriptor into a similar connection identification (Conn ID) field 62 in the converted data cell (see Fig. 6) .
- the converted data cell also includes an ingress port number field 64, indicating the number of the input port processor 14 where the data cell 22 was received, and an ingress link number field 66, indicating the number of the input link 24 that the data cell 22 arrived on.
- the output queue descriptor also contains an "echo" field 68 for a 2-bit code which indicates what action that an output port processor 16 should take when processing a data cell transmitted from an input port processor 14, as will be described in detail below.
- the code in the echo field 68 is also assigned by the switch control software.
- an output port processor 16 For every data cell transmitted from an input port processor 14, an output port processor 16 processes the data cell by comparing its own port number, link number, and connection identification code to the port number, link number, and connection identification code of the converted data cell. In conjunction with the 2-bit code in the echo field 68 of the output queue descriptor, this comparison is used to decide whether or not to enqueue the data cell arriving at a corresponding output queue 28.
- Fig. 8 there is shown a table indicating the different echo field codes and the corresponding output port processor functions associated with those codes. For example, if the echo field 68 in the output queue descriptor is set to "00", the output port processor 16 will always enqueue the data cell. In contrast, if the echo field 68 in the output queue descriptor is set to "11", the output port processor 16 will never enqueue the data cell. More importantly, however, are the actions of the output port processor 16 when the echo field 68 in the output queue descriptor is set to "01" or "10". More specifically, echo processing of data cells received by an output port processor 16 conserves resources in the switch 1 in a multipoint-to- multipoint switching scenario.
- a switch 1 is often used within a network of similar switches wherein data cells are routed through the network.
- data cells from a variety of sources are transferred from multiple input queues 26 to multiple output queues 28 within a switch 1.
- Echo processing of data cells received by an output port processor 16 achieves this objective by essentially screening converted data cells according to the port number, link number, and connection identification code contained in the converted data cells.
- the output port processor 16 When the echo field 68 in the output queue descriptor is set to "01", a "No Echo” situation, the output port processor 16 will always enqueue the data cell unless the port number, the link number, and the connection identification code of the data cell match the port number, link number, and connection identification code of the output port processor 16. Alternatively, when the echo field 68 in the output queue descriptor is set to "10", an “Only Echo” situation, the output port processor 16 will enqueue the data cell only if the port number, the link number, and the connection identification code of the data cell match the port number, link number, and connection identification code of the output port processor 16.
- FIG. 9 there is shown an example of a "No Echo" multipoint-to-multipoint switching scenario, wherein a plurality of data cells (A, B, C, and D) are being transmitted from a corresponding plurality of sources (Tl, T2, T3, and SI) to a plurality of destinations (Rl, R2, R3, and S2) .
- Tl, T2, and T3 denote end station transmitters
- Rl, R2, and R3 denote end station receivers
- SI and S2 denote other switching elements within a network.
- the data cells are received by input port processors 14a and 14b, where they are processed and enqueued in input queues 26a, 26b, 26c, and 26d.
- Input port processor 14a and output port processor 16a have the same port number, and input port processor 14b and output port processor 16b have the same port number.
- Links 24a, 24c, 30a, and 30c all have the same link number, and links 24b, 24d, 30b, and 30d all have the same link number. All of the input queues 26 and output queues 28 have been assigned an arbitrary connection identification code of 6.
- the processing of the data cells includes amending the trailer in each data cell to include an arbitrary connection identification code, a link number, and a port number.
- data cell A is assigned an arbitrary connection identification code of 6, a link number of 24a, and a port number of 14a.
- data cell B has been assigned an arbitrary connection identification code of 6, a link number of 24b, and a port number of 14a
- data cell C has been assigned an arbitrary connection identification code of 6, a link number of 24c, and a port number of 14b
- data cell D has been assigned an arbitrary connection identification code of 6, a link number of 24d, and a port number of 14b.
- multiqueue numbers are transmitted simultaneously to the output port processors 16a and 16b, whereby each output port processor 16a and 16b tests for buffer availability, i.e. output port processor 16a tests output queues 28a and 28b for buffer availability, and output port processor 16b tests output queues 28c and 28d for buffer availability. If sufficient buffering is available, the data cells are then transmitted through the Data Crossbar 10 and the data cells are processed by the corresponding output port processors 16a and 16b.
- output port processors 16a and 16b will enqueue the data cells unless the port number, the link number, and the connection identification code of the data cells match the port number, link number, and connection identification code of the output port processors 16a and 16b.
- output queue 28a will enqueue data cells B, C, and D
- output queue 28b will enqueue data cells A, C, and D
- output queue 28c will enqueue data cells
- Connection identification codes provide another control to screen sources or destinations from transmitting or receiving, respectively. This augments the physical port and link number screening.
- echo processing allows each output queue 28a-d to receive data cells from a different set of sources while utilizing a single set connection resources, namely input queues 26a-d, scheduling lists 47, and output queues 28a-d. Echo processing thus allows valuable switching resources to become unencumbered in a network switch involved in a multipoint-to-multipoint switching scenario. It will be understood that various changes and modifications to the above described method and apparatus may be made without departing from the inventive concepts disclosed herein. Accordingly, the present invention is not to be viewed as limited to the embodiment described herein.
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PCT/US1996/011918 WO1997004541A2 (en) | 1995-07-19 | 1996-07-18 | Multipoint to multipoint processing in a network switch having data buffering queues |
AU65008/96A AU6500896A (en) | 1995-07-19 | 1996-07-18 | Multipoint-to-multipoint echo processing in a network switch |
JP50686497A JP2002516038A (en) | 1995-07-19 | 1996-07-18 | Multipoint-to-multipoint echo processing in a network switch |
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US149895P | 1995-07-19 | 1995-07-19 | |
US60/001,498 | 1995-07-19 | ||
PCT/US1996/011918 WO1997004541A2 (en) | 1995-07-19 | 1996-07-18 | Multipoint to multipoint processing in a network switch having data buffering queues |
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WO1997004541A2 true WO1997004541A2 (en) | 1997-02-06 |
WO1997004541A3 WO1997004541A3 (en) | 1997-03-20 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5179558A (en) * | 1989-06-22 | 1993-01-12 | Digital Equipment Corporation | Routing apparatus and method for high-speed mesh connected local area network |
US5191582A (en) * | 1991-08-14 | 1993-03-02 | Transwitch Corporation | Method and apparatus for the high speed modification of a packet address field of a transmitted packet in a frame relay system |
US5440547A (en) * | 1993-01-07 | 1995-08-08 | Kabushiki Kaisha Toshiba | Data-transfer routing management for packet-oriented digital communication system including ATM networks |
US5519690A (en) * | 1993-11-08 | 1996-05-21 | Hitachi, Ltd. | Communication control apparatus having function for limiting frame reception and switching system with the same |
US5533020A (en) * | 1994-10-31 | 1996-07-02 | International Business Machines Corporation | ATM cell scheduler |
-
1996
- 1996-07-18 WO PCT/US1996/011918 patent/WO1997004541A2/en active Application Filing
- 1996-07-18 JP JP50686497A patent/JP2002516038A/en active Pending
- 1996-07-18 AU AU65008/96A patent/AU6500896A/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5179558A (en) * | 1989-06-22 | 1993-01-12 | Digital Equipment Corporation | Routing apparatus and method for high-speed mesh connected local area network |
US5191582A (en) * | 1991-08-14 | 1993-03-02 | Transwitch Corporation | Method and apparatus for the high speed modification of a packet address field of a transmitted packet in a frame relay system |
US5440547A (en) * | 1993-01-07 | 1995-08-08 | Kabushiki Kaisha Toshiba | Data-transfer routing management for packet-oriented digital communication system including ATM networks |
US5519690A (en) * | 1993-11-08 | 1996-05-21 | Hitachi, Ltd. | Communication control apparatus having function for limiting frame reception and switching system with the same |
US5533020A (en) * | 1994-10-31 | 1996-07-02 | International Business Machines Corporation | ATM cell scheduler |
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WO1997004541A3 (en) | 1997-03-20 |
JP2002516038A (en) | 2002-05-28 |
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