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WO1997004541A3 - Multipoint to multipoint processing in a network switch having data buffering queues - Google Patents

Multipoint to multipoint processing in a network switch having data buffering queues

Info

Publication number
WO1997004541A3
WO1997004541A3 PCT/US1996/011918 US9611918W WO1997004541A3 WO 1997004541 A3 WO1997004541 A3 WO 1997004541A3 US 9611918 W US9611918 W US 9611918W WO 1997004541 A3 WO1997004541 A3 WO 1997004541A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
data
port
processing
input
cell
Prior art date
Application number
PCT/US1996/011918
Other languages
French (fr)
Other versions
WO1997004541A2 (en )
Inventor
Richard G Bubenik
Stephen A Caldara
Stephen A Hauser
Thomas A Manning
Stephen R Veit
Original Assignee
Ascom Nexion Inc
Richard G Bubenik
Stephen A Caldara
Stephen A Hauser
Thomas A Manning
Stephen R Veit
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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    • HELECTRICITY
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    • H04L47/10Flow control or congestion control
    • H04L47/18End to end
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17375One dimensional, e.g. linear array, ring
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    • H04L12/46Interconnection of networks
    • H04L12/4604LAN interconnection over a backbone network, e.g. Internet, Frame Relay
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    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5685Addressing issues
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Abstract

An apparatus and a method are disclosed for unencumbering valuable switching resources in a network switch involved in a multipoint-to-multipoint switching scenario. The network switch (1) includes an input processing port (14) connected between a plurality of input links and a switching fabric, and having a plurality of data buffering queues (26), and an output processing port (16) connected between the switch fabric and a plurality of output links and having a plurality of data buffering queues (28). The input processing port processes a data cell received on one of the input links by appending to the data cell a link number, a port number, and a connection ID associated with input side. The output processing port processes the data cell processed by the input processing port by comparing the link number, the port number, and the connection ID of the data cell with those associated with the output processing port. The data cell is then stored in the data buffering queue according to a matching scheme.
PCT/US1996/011918 1995-07-19 1996-07-18 Multipoint to multipoint processing in a network switch having data buffering queues WO1997004541A3 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US149895 true 1995-07-19 1995-07-19
US60/001,498 1995-07-19
PCT/US1996/011918 WO1997004541A3 (en) 1995-07-19 1996-07-18 Multipoint to multipoint processing in a network switch having data buffering queues

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US1996/011918 WO1997004541A3 (en) 1995-07-19 1996-07-18 Multipoint to multipoint processing in a network switch having data buffering queues
JP50686497A JP2002516038A (en) 1995-07-19 1996-07-18 Multipoint-to-Multipoint echo processing in the network switch

Publications (2)

Publication Number Publication Date
WO1997004541A2 true WO1997004541A2 (en) 1997-02-06
WO1997004541A3 true true WO1997004541A3 (en) 1997-03-20

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JP (1) JP2002516038A (en)
WO (1) WO1997004541A3 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179558A (en) * 1989-06-22 1993-01-12 Digital Equipment Corporation Routing apparatus and method for high-speed mesh connected local area network
US5191582A (en) * 1991-08-14 1993-03-02 Transwitch Corporation Method and apparatus for the high speed modification of a packet address field of a transmitted packet in a frame relay system
US5440547A (en) * 1993-01-07 1995-08-08 Kabushiki Kaisha Toshiba Data-transfer routing management for packet-oriented digital communication system including ATM networks
US5519690A (en) * 1993-11-08 1996-05-21 Hitachi, Ltd. Communication control apparatus having function for limiting frame reception and switching system with the same
US5533020A (en) * 1994-10-31 1996-07-02 International Business Machines Corporation ATM cell scheduler

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179558A (en) * 1989-06-22 1993-01-12 Digital Equipment Corporation Routing apparatus and method for high-speed mesh connected local area network
US5191582A (en) * 1991-08-14 1993-03-02 Transwitch Corporation Method and apparatus for the high speed modification of a packet address field of a transmitted packet in a frame relay system
US5440547A (en) * 1993-01-07 1995-08-08 Kabushiki Kaisha Toshiba Data-transfer routing management for packet-oriented digital communication system including ATM networks
US5519690A (en) * 1993-11-08 1996-05-21 Hitachi, Ltd. Communication control apparatus having function for limiting frame reception and switching system with the same
US5533020A (en) * 1994-10-31 1996-07-02 International Business Machines Corporation ATM cell scheduler

Also Published As

Publication number Publication date Type
JP2002516038A (en) 2002-05-28 application
WO1997004541A2 (en) 1997-02-06 application

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