WO1997004541A3 - Multipoint to multipoint processing in a network switch having data buffering queues - Google Patents

Multipoint to multipoint processing in a network switch having data buffering queues Download PDF

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Publication number
WO1997004541A3
WO1997004541A3 PCT/US1996/011918 US9611918W WO9704541A3 WO 1997004541 A3 WO1997004541 A3 WO 1997004541A3 US 9611918 W US9611918 W US 9611918W WO 9704541 A3 WO9704541 A3 WO 9704541A3
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WO
WIPO (PCT)
Prior art keywords
multipoint
data cell
processing port
input
network switch
Prior art date
Application number
PCT/US1996/011918
Other languages
French (fr)
Other versions
WO1997004541A2 (en
Inventor
Richard G Bubenik
Stephen A Caldara
Stephen A Hauser
Thomas A Manning
Stephen R Veit
Original Assignee
Ascom Nexion Inc
Richard G Bubenik
Stephen A Caldara
Stephen A Hauser
Thomas A Manning
Stephen R Veit
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascom Nexion Inc, Richard G Bubenik, Stephen A Caldara, Stephen A Hauser, Thomas A Manning, Stephen R Veit filed Critical Ascom Nexion Inc
Priority to PCT/US1996/011918 priority Critical patent/WO1997004541A2/en
Priority to JP50686497A priority patent/JP2002516038A/en
Priority to AU65008/96A priority patent/AU6500896A/en
Publication of WO1997004541A2 publication Critical patent/WO1997004541A2/en
Publication of WO1997004541A3 publication Critical patent/WO1997004541A3/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Abstract

An apparatus and a method are disclosed for unencumbering valuable switching resources in a network switch involved in a multipoint-to-multipoint switching scenario. The network switch (1) includes an input processing port (14) connected between a plurality of input links and a switching fabric, and having a plurality of data buffering queues (26), and an output processing port (16) connected between the switch fabric and a plurality of output links and having a plurality of data buffering queues (28). The input processing port processes a data cell received on one of the input links by appending to the data cell a link number, a port number, and a connection ID associated with input side. The output processing port processes the data cell processed by the input processing port by comparing the link number, the port number, and the connection ID of the data cell with those associated with the output processing port. The data cell is then stored in the data buffering queue according to a matching scheme.
PCT/US1996/011918 1995-07-19 1996-07-18 Multipoint to multipoint processing in a network switch having data buffering queues WO1997004541A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/US1996/011918 WO1997004541A2 (en) 1995-07-19 1996-07-18 Multipoint to multipoint processing in a network switch having data buffering queues
JP50686497A JP2002516038A (en) 1995-07-19 1996-07-18 Multipoint-to-multipoint echo processing in a network switch
AU65008/96A AU6500896A (en) 1995-07-19 1996-07-18 Multipoint-to-multipoint echo processing in a network switch

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US60/001,498 1995-07-19
PCT/US1996/011918 WO1997004541A2 (en) 1995-07-19 1996-07-18 Multipoint to multipoint processing in a network switch having data buffering queues

Publications (2)

Publication Number Publication Date
WO1997004541A2 WO1997004541A2 (en) 1997-02-06
WO1997004541A3 true WO1997004541A3 (en) 1997-03-20

Family

ID=38659409

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/011918 WO1997004541A2 (en) 1995-07-19 1996-07-18 Multipoint to multipoint processing in a network switch having data buffering queues

Country Status (3)

Country Link
JP (1) JP2002516038A (en)
AU (1) AU6500896A (en)
WO (1) WO1997004541A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179558A (en) * 1989-06-22 1993-01-12 Digital Equipment Corporation Routing apparatus and method for high-speed mesh connected local area network
US5191582A (en) * 1991-08-14 1993-03-02 Transwitch Corporation Method and apparatus for the high speed modification of a packet address field of a transmitted packet in a frame relay system
US5440547A (en) * 1993-01-07 1995-08-08 Kabushiki Kaisha Toshiba Data-transfer routing management for packet-oriented digital communication system including ATM networks
US5519690A (en) * 1993-11-08 1996-05-21 Hitachi, Ltd. Communication control apparatus having function for limiting frame reception and switching system with the same
US5533020A (en) * 1994-10-31 1996-07-02 International Business Machines Corporation ATM cell scheduler

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179558A (en) * 1989-06-22 1993-01-12 Digital Equipment Corporation Routing apparatus and method for high-speed mesh connected local area network
US5191582A (en) * 1991-08-14 1993-03-02 Transwitch Corporation Method and apparatus for the high speed modification of a packet address field of a transmitted packet in a frame relay system
US5440547A (en) * 1993-01-07 1995-08-08 Kabushiki Kaisha Toshiba Data-transfer routing management for packet-oriented digital communication system including ATM networks
US5519690A (en) * 1993-11-08 1996-05-21 Hitachi, Ltd. Communication control apparatus having function for limiting frame reception and switching system with the same
US5533020A (en) * 1994-10-31 1996-07-02 International Business Machines Corporation ATM cell scheduler

Also Published As

Publication number Publication date
JP2002516038A (en) 2002-05-28
AU6500896A (en) 1997-02-18
WO1997004541A2 (en) 1997-02-06

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