WO1996041373A1 - Low inductance electrical ground connection integrated circuit die package - Google Patents

Low inductance electrical ground connection integrated circuit die package Download PDF

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Publication number
WO1996041373A1
WO1996041373A1 PCT/US1996/002001 US9602001W WO9641373A1 WO 1996041373 A1 WO1996041373 A1 WO 1996041373A1 US 9602001 W US9602001 W US 9602001W WO 9641373 A1 WO9641373 A1 WO 9641373A1
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Prior art keywords
integrated circuit
lead frame
ground
pin
circuit die
Prior art date
Application number
PCT/US1996/002001
Other languages
French (fr)
Inventor
Robert A. Newman
Original Assignee
Advanced Micro Devices, Inc.
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Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1996041373A1 publication Critical patent/WO1996041373A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention is related to the following United States Patents, each of which is owned by assignee of the present invention and each of which is incorporated by reference herein: U.S. Patent No. 5,068,708 by Robert A. Newman, entitled GROUND PLANE FOR PLASTIC ENCAPSULATED INTEGRATED CIRCUIT DIE PACKAGES, issued November 26, 1991;
  • the present invention is related to plastic encapsulated integrated circuit die packages, and in particular, to a method and apparatus for providing low inductance electrical ground connections between the integrated circuit die and elements which are external to the integrated circuit die package.
  • n is all of the signals switching at a particular instant
  • L is the inductance of ground and/or power lead
  • di/dt is rate of change in current across the lead.
  • Current high speed integrated circuit packages generally employ hundreds of subsystems, each having a switching signal. Therefore, it can be seen that significant transient switching voltages may occur in the ground leads, as when all or many of the signals switch from a high to a low state simultaneously. Similarly, significant switching transients may occur across the power leads when all or many of the signals switch together from a low to a high state. Transient switching voltages may produce significant noise that adversely affects the performance of the integrated circuit die. Even a small reduction in the inductance of the ground and/or power leads can significantly reduce transient switching voltages.
  • One conventional way of reducing inductance is to dedicate several of the lead frame leads as ground and/or power leads. While this reduces switching transients, a relatively large number of leads are made unavailable for signal transmission.
  • Another conventional method of reducing inductance is to maximize the size of the ground plane, such as shown in U.S. Patent No. 4,577,214 to Schaper, entitled "LOW- INDUCTANCE POWER/GROUND DISTRIBUTION IN A PACKAGE FOR A SEMICONDUCTOR CHIP" .
  • the die package includes a lead frame having a plurality of signal, power and ground pins, and a ground plane assembly including a ground plane mounted to and electrically insulated from the lead frame. Tabs are provided on the ground plane and ground pins for electrically coupling the ground plane and ground pins to each other at two distinct locations along the ground pins.
  • the ground plane assembly is comprised of a metallic ground plane bonded to a first surface of an insulating tape. A second surface of the insulating tape opposite the first surface is bonded to the lead frame.
  • the lead frame includes a plurality of ground pins having ends electrically coupled to the integrated circuit die.
  • a ground pin includes a tab at an inner diameter of the ground pin, i.e.. at a section of the ground pin nearest the integrated circuit die. This ground pin tab is welded to the ground plane near the integrated circuit die so as to establish the first electrical coupling between the ground pin and ground plane.
  • the ground plane includes one or more tabs at an outer diameter of the ground plane, i.e.. at a section of the ground plane nearest the exterior of the integrated circuit package. A ground plane tab is welded to the ground pin near the exterior of the integrated circuit package so as to establish the second electrical coupling between a ground pin and ground plane.
  • ground pin of a lead frame is welded to the ground plane at two separate locations as described above
  • voltage from the integrated circuit die is grounded through two parallel electrical paths, a first involving only the ground pin and a second involving both the ground pin and the ground plane.
  • parallel ground paths between a ground pin and ground plane offers the advantage of reduced inductance relative to convention electrical ground circuits.
  • FIGURE l is a top view of lead frame and ground plane assembly according to the present invention.
  • FIGURE 2 is a top view of a ground plane assembly according to the present invention.
  • FIGURE 3 is a side view of the ground plane assembly shown in Fig. 2;
  • FIGURE 4 is a cross-sectional view of the present invention through line 4-4 in Fig. 1;
  • FIGURE 5 is a cross-sectional view as in Fig. 4 showing the parallel current flow paths through the electrical ground connection according to the present inve tio ;
  • FIGURE 6 is an alternative embodiment of the ground plane according to the present invention.
  • Figs. 1 through 6 which in general disclose an integrated circuit die package having reduced inductance electrical connections. While the reduced inductance electrical connections are described hereinafter with respect to the electrical ground of the die package, it is understood that the present invention may be used to lower the inductance of the die package.
  • Vcc power supply to the die package instead of or in addition to the die package electrical ground.
  • lead frame 104 may include a plurality of pins 108 around a circumference of the lead frame, each pin 108 having an inner end 110 nearest the die 102 capable of independent electrical connection to die pads (not shown) on die 102.
  • the pins 108 have an outer end 112 opposite end 110 for electrical connection to an external circuit element located for example on a printed circuit board (not shown) .
  • Inner end 110 of a lead frame pin 108 may be connected to the appropriate die pad on die 102 using conventional bond wires 114 (Fig. 4) .
  • This is usually accomplished with an automatic wire bonder such as, for example, a K&S 1482 gold wire bonder, available from Kulicke and Soffa Industries, Inc. Bond wires 114 are omitted from Fig. 1 for clarity.
  • lead frame 104 further includes ground pins 116 and power pins (not specifically labeled) for facilitating high-speed switching of the output buffers (not shown) of the die 102 connected to pins 108.
  • ground pins 116 and power pins (not specifically labeled) for facilitating high-speed switching of the output buffers (not shown) of the die 102 connected to pins 108.
  • the present invention further includes the ground plane assembly 106 (Figs.
  • ground plane assembly 106 preferably includes a ground plane 118 bonded to a tape assembly 120.
  • Ground plane 118 may comprise metals such as for example, copper, aluminum, gold, silver, or alloy materials such as alloy 42, a nickel-iron alloy.
  • Preferably ground plane 118 is comprised of copper because of its excellent electrical and thermal conductivity, as well as cost compared to precious metals.
  • Ground plane 118 may comprise a metal foil or sheet stock ranging in thickness from about 1.5 to 20 mils.
  • the thickness will range from about 7 to 12 mils to provide both the desired electrical ground properties as well as providing good heat conductivity.
  • the thickness of the ground plane 118 may be greater, such as for example up to 100 mils, to provide improved electrical ground and thermal properties.
  • Metal foil in the preferred thickness range is commercially available.
  • ground plane 118 further includes tabs 122 extending out from the corners of the ground plane for attachment to the ground pins 116.
  • a ground plane 200 may be provided having a middle section 202 having a greater thickness than a circumferencial section 204.
  • the increased thickness of the middle section 202 improves the electrical ground and thermal characteristics of ground plane 200.
  • the circumferencial section 204 is thinner so as to facilitate connection of tabs 122 to the section 204, which tabs may be welded to a lead frame pin to electrically couple the ground plane to the lead frame pin as described in greater detail below.
  • middle section 202 in Fig. 6 may be approximately 20 mils to 100 mils, and the thickness of circumferencial section 204 may be approximately 1.5 mils to 20 mils. It is understood that these dimensions may vary in alternative embodiments of the invention.
  • the ground plane 200 may be formed in a single process with the circumferencial section masked so that the circumferencial section and the middle section are integrally formed with each other as a single unit.
  • the middle section may be affixed to the circumferencial section by known methods to bond and electrically couple the two sections together.
  • Tape assembly 120 is provided for bonding the ground plane 118 to the lead frame 104, and also to electrically insulate ground plane 118 from the lead frame 104.
  • tape assembly 120 may be comprised of a polyimide film insulating layer 124 such as, for example, Kapton, which insulating layer 124 is sandwiched between two adhesive layers 126, 128. Insulating layer 124 may have a thickness of about 0.5 to 20 mils and each adhesive layer may have a thickness of about 0.5 to 1.5 mils.
  • the ground plane 118 also acts as a heat sink with heat being conducted through the tape assembly 120.
  • the insulating layer 124 may be relatively thick for embodiments where it is desired to emphasize electrical insulation over thermal conductivity through the insulating layer 124. Conversely, the insulating layer 124 may be relatively thin for embodiments where it is desired to emphasize thermal conductivity through the insulating layer 124 over electrical insulation.
  • Tape assembly 120 is commercially available for example from Tomoegawa Paper Co., Ltd., Tokyo, Japan.
  • the outer diameter of the tape assembly 120 is approximately the same size as the outer diameter of the ground plane 118, except in the area of ground plane tabs 122. However, a center portion of the tape assembly 120 is preferably punched, cut or otherwise removed so that the tape assembly lies in contact with only an outer circumference of the ground plane.
  • ground pins 116 include tab 130 at their innermost end so that the length of ground pins 116 including tabs 130 is greater than the length of pins 108.
  • ground pin tabs 130 extend toward the center of the die package 100 further than the portion of the tape assembly 120 adjacent to the ground pin tabs 130.
  • the ground pin tabs 130 may be electrically coupled to the ground plane 118 at an inner coupling location 132 (Fig. 4)
  • the ground plane tabs 122 may be electrically coupled to the ground pins 116 at an outer coupling location 134.
  • the tabs are welded by a process such as laser welding. It is understood however that other welding methods may be used, such as for example ther o-compression welding. Similarly, attaching methods other than welding may be used, such as for example soldering and through the use of known electrically conductive adhesives.
  • each weld is sufficiently large to provide good electrical and thermal coupling between the lead frame pins and the ground plane, the As shown in Fig. 5, by attaching tabs 122 and 130 to the ground pins and ground plane, respectively, a ground pin 116 and the ground plane 118 together comprise two parallel current flow paths for grounding the die 102. After the ground current flows from the die 102 to a ground pin 116 via the bond wire 114, the ground current is split into two parallel paths. A first electrical ground path flows through the ground pin 108 in the direction of the arrows A to an external ground (not shown) outside of the die package. A second electrical ground path flows in the direction of arrows B from the ground pin 116 through the inner coupling location 132 and into the ground plane 118.
  • the parallel ground paths provide electrical ground couplings from the die package having a lower inductance than conventional ground couplings which comprise single ground paths through the ground pins alone or through the ground pins and ground plane.
  • the die package as described above could be modified and still accomplish the objectives of the present invention.
  • the ground pins 116 and the tabs 122 and 130 could be provided at other locations around the periphery of the lead frame 104 and ground plane 118.
  • the ground wire bond 114 from the die 102 may be bonded directly to the ground plane 118 and still have the parallel electrical ground path as described above.
  • a die package according to the present invention may have more or less than four ground pins and tabs.
  • the tape assembly may be modified to include a buried copper foil layer, of for example 1.0 mils, forming a quiescent plane to prevent mutual inductance between the welded lead frame pins and the ground plane through the tape assembly.
  • the tape assembly includes a first adhesive layer for attaching to the lead frame, a first insulating tape attached to the first adhesive layer, a second adhesive layer attached to the first insulating tape, the layer of copper foil attached to the second adhesive layer, a third adhesive layer attached to the copper foil layer, a second insulating tape attached to the third adhesive layer, and a fourth adhesive layer attached to the second insulating tape for attaching the tape assembly to the ground plane layer 118.
  • a tape assembly is commercially available from, for example, the Chomerics company.
  • the buried copper layer acts as a shield to prevent electrical cross-talk between the lead frame pins and the ground plane through the tape assembly. The above description has thus far related primarily to dissipation of ground voltage from an integrated circuit die.
  • a power plane power includes a plurality of tabs as described above with respect to ground plane 118.
  • one or more of the power pins are provided with a tab as described above with respect to ground pins 116.
  • the tab on the power pin is electrically coupled by, for example, welding to the power plane at an inner coupling location as described above, and the tab on the power plane is electrically coupled by, for example, welding to the power pin at an outer coupling location as described above.
  • both a power plane and a ground plane may be provided by attaching, for example, the ground plane to the lead frame by an electrically insulating tape, and thereafter attaching the power plane to the ground plane by an electrically insulating tape (the order of attachment of the ground and power planes to the lead frame may of course be reversed) . Thereafter, the tabs on the ground and power planes are attached to the ground and power pins, respectively, as described above, and the tabs on the ground and power pins are attached to the ground and power planes, respectively, as described above.
  • the entire assembly may be encapsulated in plastic.
  • the encapsulant may be an epoxy novalac plastic encapsulating material (not shown) such as Sumitomo 6300H.
  • the outer coupling location 134 (Fig. 4) is located within but near the outer surface of the encapsulating plastic.
  • the inner coupling location 132 is preferably located close to the wire bond 114 connection to the lead frame 104.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A low inductance electrical ground connection for an integrated circuit die package (100) including a lead frame ground pin (116) electrically coupled to a ground plane (118) at two distinct locations along the ground pin to thereby establish two parallel electrical ground current flow paths, a first path involving only the ground pin (116) and a second path involving both the ground pin (116) and the ground plane (118).

Description

LOW INDUCTANCE ELECTRICAL GROUND CONNECTION INTEGRATED CIRCUIT DIE PACKAGE
CROSS REFERENCE TO RELATED PUBLICATIONS
The present invention is related to the following United States Patents, each of which is owned by assignee of the present invention and each of which is incorporated by reference herein: U.S. Patent No. 5,068,708 by Robert A. Newman, entitled GROUND PLANE FOR PLASTIC ENCAPSULATED INTEGRATED CIRCUIT DIE PACKAGES, issued November 26, 1991;
U.S. Patent No. 5,237,205 by Robert A. Newman, entitled GROUND PLANE FOR PLASTIC ENCAPSULATED INTEGRATED CIRCUIT DIE PACKAGES, issued August 17, 1993; and
U.S. Patent No. 5,208,188 by Robert A. Newman, entitled PROCESS FOR MAKING A MULTILAYER LEAD FRAME ASSEMBLY FOR AN INTEGRATED CIRCUIT STRUCTURE AND
MULTILAYER INTEGRATED CIRCUIT DIE PACKAGE FORMED BY
SUCH PROCESS, issued May 4, 1993.
BACKGROUND Field of the Invention
The present invention is related to plastic encapsulated integrated circuit die packages, and in particular, to a method and apparatus for providing low inductance electrical ground connections between the integrated circuit die and elements which are external to the integrated circuit die package.
Description of the Related Art In the packaging of integrated circuit structures, it is known to provide a metal layer adjacent the integrated circuit die which metal layer functions as a ground plane to reduce inductance, and thereby speed the performance of the device, as well as to provide a heat sink or dissipation means. For example, U.S. Patent No. 5,068,708 incorporated herein above discloses a multilayer ground plane assembly formed by bonding a copper sheet and a partially cured adhesive layer to opposite surfaces of a thermally conductive polyimide material insulating layer. The metal/insulator/adhesive assembly is then bonded to the lead frame by placing the adhesive layer against the lead frame and heating the ground plane assembly and lead frame to a curing temperature of the adhesive layer. An integrated circuit die is then attached to the ground plane/lead frame assembly, and the die is then electrically connected to the lead frame. The bonded together ground plane/lead frame/die assembly is then placed in a mold and encapsulated in plastic. In conventional die packages, switching a supplied voltage signal between a high (on) and low (off) state may result in undesirable transient switching voltages, especially when large numbers of signals switch to the same state simultaneously. These transient switching voltages result largely from inductance within the electrical connections between the integrated circuit die and external electrical components located on, for example, a printed circuit board. Inductance may present a significant problem where relatively large currents flow through an electrical connection, such as for example across the ground and/or power leads. With respect to a ground lead and/or power lead, the undesirable transient switching voltage may be described as the by the equation:
__ (D (di/dt)
where n is all of the signals switching at a particular instant, L is the inductance of ground and/or power lead, and di/dt is rate of change in current across the lead. Current high speed integrated circuit packages generally employ hundreds of subsystems, each having a switching signal. Therefore, it can be seen that significant transient switching voltages may occur in the ground leads, as when all or many of the signals switch from a high to a low state simultaneously. Similarly, significant switching transients may occur across the power leads when all or many of the signals switch together from a low to a high state. Transient switching voltages may produce significant noise that adversely affects the performance of the integrated circuit die. Even a small reduction in the inductance of the ground and/or power leads can significantly reduce transient switching voltages.
One conventional way of reducing inductance is to dedicate several of the lead frame leads as ground and/or power leads. While this reduces switching transients, a relatively large number of leads are made unavailable for signal transmission. Another conventional method of reducing inductance is to maximize the size of the ground plane, such as shown in U.S. Patent No. 4,577,214 to Schaper, entitled "LOW- INDUCTANCE POWER/GROUND DISTRIBUTION IN A PACKAGE FOR A SEMICONDUCTOR CHIP" .
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an integrated circuit package including electrical connections having reduced inductance.
It is a further object of the present invention to provide a system for reducing inductance within electrical connections of an integrated circuit package without a corresponding sacrifice in other system parameters such as available signal leads.
It is a further object of the present invention to provide a system for reducing inductance within electrical connections of an integrated circuit package requiring minimal redesign of conventional integrated circuit packages.
These and other objects are accomplished by the present invention which relates to a method and apparatus for providing low inductance electrical connections within an integrated circuit die package between an integrated circuit die and elements external to the die package. The die package includes a lead frame having a plurality of signal, power and ground pins, and a ground plane assembly including a ground plane mounted to and electrically insulated from the lead frame. Tabs are provided on the ground plane and ground pins for electrically coupling the ground plane and ground pins to each other at two distinct locations along the ground pins. The ground plane assembly is comprised of a metallic ground plane bonded to a first surface of an insulating tape. A second surface of the insulating tape opposite the first surface is bonded to the lead frame. As is known in the art, the lead frame includes a plurality of ground pins having ends electrically coupled to the integrated circuit die. According to the present invention, a ground pin includes a tab at an inner diameter of the ground pin, i.e.. at a section of the ground pin nearest the integrated circuit die. This ground pin tab is welded to the ground plane near the integrated circuit die so as to establish the first electrical coupling between the ground pin and ground plane. Similarly, the ground plane includes one or more tabs at an outer diameter of the ground plane, i.e.. at a section of the ground plane nearest the exterior of the integrated circuit package. A ground plane tab is welded to the ground pin near the exterior of the integrated circuit package so as to establish the second electrical coupling between a ground pin and ground plane.
Where a ground pin of a lead frame is welded to the ground plane at two separate locations as described above, voltage from the integrated circuit die is grounded through two parallel electrical paths, a first involving only the ground pin and a second involving both the ground pin and the ground plane. The provision of parallel ground paths between a ground pin and ground plane offers the advantage of reduced inductance relative to convention electrical ground circuits.
BRIEF DESCRIPTION OF THE DRAWINGS The below detailed description makes reference to the accompanying drawings, in which: FIGURE l is a top view of lead frame and ground plane assembly according to the present invention;
FIGURE 2 is a top view of a ground plane assembly according to the present invention;
FIGURE 3 is a side view of the ground plane assembly shown in Fig. 2;
FIGURE 4 is a cross-sectional view of the present invention through line 4-4 in Fig. 1;
FIGURE 5 is a cross-sectional view as in Fig. 4 showing the parallel current flow paths through the electrical ground connection according to the present inve tio ; and
FIGURE 6 is an alternative embodiment of the ground plane according to the present invention.
DETAILED DESCRIPTION
The invention will now be described with reference to Figs. 1 through 6 which in general disclose an integrated circuit die package having reduced inductance electrical connections. While the reduced inductance electrical connections are described hereinafter with respect to the electrical ground of the die package, it is understood that the present invention may be used to lower the inductance of the
Vcc power supply to the die package instead of or in addition to the die package electrical ground.
Referring now to Figs. 1 and 4, there is shown an integrated circuit die package 100 including an integrated circuit die 102, a lead frame 104, and a ground plane assembly 106. As is known in the art, lead frame 104 may include a plurality of pins 108 around a circumference of the lead frame, each pin 108 having an inner end 110 nearest the die 102 capable of independent electrical connection to die pads (not shown) on die 102. The pins 108 have an outer end 112 opposite end 110 for electrical connection to an external circuit element located for example on a printed circuit board (not shown) .
Inner end 110 of a lead frame pin 108 may be connected to the appropriate die pad on die 102 using conventional bond wires 114 (Fig. 4) . This is usually accomplished with an automatic wire bonder such as, for example, a K&S 1482 gold wire bonder, available from Kulicke and Soffa Industries, Inc. Bond wires 114 are omitted from Fig. 1 for clarity.
As is further known in the art, lead frame 104 further includes ground pins 116 and power pins (not specifically labeled) for facilitating high-speed switching of the output buffers (not shown) of the die 102 connected to pins 108. When some or all of the output buffers switch from a high to a low state in conventional die packages, voltage from the die is grounded through bond wires and ground pins on the lead frame. As indicated in the Description of the Related Art section, it is desirable to minimize the inductance of the ground pins so as to minimize the transient switching voltage that occurs during signal switching, especially when large numbers of output buffers switch to a low state simultaneously. Therefore, the present invention further includes the ground plane assembly 106 (Figs. 2-4) which, together with the ground pins 116, provide parallel ground paths for grounding the die 102. As explained in greater detail in U.S. Patent No. 5,208,188 previously incorporated herein, ground plane assembly 106 preferably includes a ground plane 118 bonded to a tape assembly 120. Ground plane 118 may comprise metals such as for example, copper, aluminum, gold, silver, or alloy materials such as alloy 42, a nickel-iron alloy. Preferably ground plane 118 is comprised of copper because of its excellent electrical and thermal conductivity, as well as cost compared to precious metals. Ground plane 118 may comprise a metal foil or sheet stock ranging in thickness from about 1.5 to 20 mils. Preferably the thickness will range from about 7 to 12 mils to provide both the desired electrical ground properties as well as providing good heat conductivity. However, in alternative embodiments of the present invention, the thickness of the ground plane 118 may be greater, such as for example up to 100 mils, to provide improved electrical ground and thermal properties. Metal foil in the preferred thickness range is commercially available. As explained in greater detail below, ground plane 118 further includes tabs 122 extending out from the corners of the ground plane for attachment to the ground pins 116.
In an alternative embodiment of the present invention shown in Fig. 6, a ground plane 200 may be provided having a middle section 202 having a greater thickness than a circumferencial section 204. The increased thickness of the middle section 202 improves the electrical ground and thermal characteristics of ground plane 200. The circumferencial section 204 is thinner so as to facilitate connection of tabs 122 to the section 204, which tabs may be welded to a lead frame pin to electrically couple the ground plane to the lead frame pin as described in greater detail below.
The thickness of middle section 202 in Fig. 6 may be approximately 20 mils to 100 mils, and the thickness of circumferencial section 204 may be approximately 1.5 mils to 20 mils. It is understood that these dimensions may vary in alternative embodiments of the invention. The ground plane 200 may be formed in a single process with the circumferencial section masked so that the circumferencial section and the middle section are integrally formed with each other as a single unit. Alternatively, the middle section may be affixed to the circumferencial section by known methods to bond and electrically couple the two sections together.
Tape assembly 120 is provided for bonding the ground plane 118 to the lead frame 104, and also to electrically insulate ground plane 118 from the lead frame 104. In one embodiment of the present invention, tape assembly 120 may be comprised of a polyimide film insulating layer 124 such as, for example, Kapton, which insulating layer 124 is sandwiched between two adhesive layers 126, 128. Insulating layer 124 may have a thickness of about 0.5 to 20 mils and each adhesive layer may have a thickness of about 0.5 to 1.5 mils. The ground plane 118 also acts as a heat sink with heat being conducted through the tape assembly 120. As will be appreciated by those skilled in the art, the insulating layer 124 may be relatively thick for embodiments where it is desired to emphasize electrical insulation over thermal conductivity through the insulating layer 124. Conversely, the insulating layer 124 may be relatively thin for embodiments where it is desired to emphasize thermal conductivity through the insulating layer 124 over electrical insulation. Tape assembly 120 is commercially available for example from Tomoegawa Paper Co., Ltd., Tokyo, Japan.
The outer diameter of the tape assembly 120 is approximately the same size as the outer diameter of the ground plane 118, except in the area of ground plane tabs 122. However, a center portion of the tape assembly 120 is preferably punched, cut or otherwise removed so that the tape assembly lies in contact with only an outer circumference of the ground plane. Once the ground plane 118 is attached to the lead frame 104 via the tape assembly 120, the center opening in the lead frame 104 defined by the inner ends 110 of the lead frame pins 108 is concentric with and slightly larger in diameter than the center opening defined by the tape assembly 120. Consequently, the pins 108 are completely insulated against direct contact with the ground plane 118.
However, ground pins 116 include tab 130 at their innermost end so that the length of ground pins 116 including tabs 130 is greater than the length of pins 108. Thus, as shown on Figs. 1 and 4, ground pin tabs 130 extend toward the center of the die package 100 further than the portion of the tape assembly 120 adjacent to the ground pin tabs 130.
After the ground plane assembly 106 has been affixed to the lead frame 104 as described above, the ground pin tabs 130 may be electrically coupled to the ground plane 118 at an inner coupling location 132 (Fig. 4) , and the ground plane tabs 122 may be electrically coupled to the ground pins 116 at an outer coupling location 134. Although any of several methods may be used to electrically couple the tabs 122 and 130 to the ground pins and ground plane, respectively, in a preferred embodiment the tabs are welded by a process such as laser welding. It is understood however that other welding methods may be used, such as for example ther o-compression welding. Similarly, attaching methods other than welding may be used, such as for example soldering and through the use of known electrically conductive adhesives. The size of each weld is sufficiently large to provide good electrical and thermal coupling between the lead frame pins and the ground plane, the As shown in Fig. 5, by attaching tabs 122 and 130 to the ground pins and ground plane, respectively, a ground pin 116 and the ground plane 118 together comprise two parallel current flow paths for grounding the die 102. After the ground current flows from the die 102 to a ground pin 116 via the bond wire 114, the ground current is split into two parallel paths. A first electrical ground path flows through the ground pin 108 in the direction of the arrows A to an external ground (not shown) outside of the die package. A second electrical ground path flows in the direction of arrows B from the ground pin 116 through the inner coupling location 132 and into the ground plane 118. From the ground plane 118, the current flows through the outer coupling location 134 back into the ground pin 116 and into the external ground. The parallel ground paths provide electrical ground couplings from the die package having a lower inductance than conventional ground couplings which comprise single ground paths through the ground pins alone or through the ground pins and ground plane.
As would be understood by those skilled in the art, the die package as described above could be modified and still accomplish the objectives of the present invention. For example, it is understood that the ground pins 116 and the tabs 122 and 130 could be provided at other locations around the periphery of the lead frame 104 and ground plane 118. Moreover, in a alternative embodiment of the present invention, the ground wire bond 114 from the die 102 may be bonded directly to the ground plane 118 and still have the parallel electrical ground path as described above. Furthermore, while the above description provides for four ground pins and four tabs 122 and 130, it is understood that a die package according to the present invention may have more or less than four ground pins and tabs. It is further contemplated that only some of the ground pins of a particular lead frame have the parallel electrical ground paths described above. In a further embodiment, the tape assembly may be modified to include a buried copper foil layer, of for example 1.0 mils, forming a quiescent plane to prevent mutual inductance between the welded lead frame pins and the ground plane through the tape assembly. In this embodiment, the tape assembly includes a first adhesive layer for attaching to the lead frame, a first insulating tape attached to the first adhesive layer, a second adhesive layer attached to the first insulating tape, the layer of copper foil attached to the second adhesive layer, a third adhesive layer attached to the copper foil layer, a second insulating tape attached to the third adhesive layer, and a fourth adhesive layer attached to the second insulating tape for attaching the tape assembly to the ground plane layer 118. Such a tape assembly is commercially available from, for example, the Chomerics company. The buried copper layer acts as a shield to prevent electrical cross-talk between the lead frame pins and the ground plane through the tape assembly. The above description has thus far related primarily to dissipation of ground voltage from an integrated circuit die. However, as previously indicated, the present invention may additionally or alternatively be used to supply the Vcc voltage to the output buffers of the die. In this embodiment, a power plane power includes a plurality of tabs as described above with respect to ground plane 118. Similarly, one or more of the power pins are provided with a tab as described above with respect to ground pins 116. The tab on the power pin is electrically coupled by, for example, welding to the power plane at an inner coupling location as described above, and the tab on the power plane is electrically coupled by, for example, welding to the power pin at an outer coupling location as described above. In this way, the power pin and power plane may provide an electrical coupling to the integrated circuit die having a lower inductance than a conventional system employing a single path electrical power coupling. As is known in the art, both a power plane and a ground plane may be provided by attaching, for example, the ground plane to the lead frame by an electrically insulating tape, and thereafter attaching the power plane to the ground plane by an electrically insulating tape (the order of attachment of the ground and power planes to the lead frame may of course be reversed) . Thereafter, the tabs on the ground and power planes are attached to the ground and power pins, respectively, as described above, and the tabs on the ground and power pins are attached to the ground and power planes, respectively, as described above.
As in known in the art, after attachment of all electrical connections, the entire assembly may be encapsulated in plastic. The encapsulant may be an epoxy novalac plastic encapsulating material (not shown) such as Sumitomo 6300H. After encapsulation, only the outer ends 112 of the lead frame pins 108, 116 extend out of the package for attachment to external circuit elements. In a preferred embodiment, the outer coupling location 134 (Fig. 4) is located within but near the outer surface of the encapsulating plastic. Similarly, the inner coupling location 132 is preferably located close to the wire bond 114 connection to the lead frame 104.
Figure imgf000016_0001
Although the invention has been desccrriibbeedd iinn ■ detail herein, it should be understood that the invention is not limited to the embodiments herein disclosed. Various changes, substitutions and modifications may be made thereto by those skilled in the art without departing from the spirit or scope of the invention as described and defined by the appended claims.

Claims

I Claim:
1. An electrical connection within an integrated circuit package, the package including an integrated circuit die and a lead frame, the lead frame including a plurality of pins for electrically connecting the integrated circuit die to elements external to the integrated circuit die, comprising: an electrically conductive plane attached to and electrically insulated from the lead frame; a first tab provided on said electrically conductive plane for attaching to a lead frame pin of the plurality of pins at a first location to electrically couple said electrically conductive plane to said lead frame pin at said first location; and a second tab provided on said lead frame pin for attaching to said electrically conductive plane at a second location distinct from said first location to electrically couple said lead frame pin to said electrically conductive plane at said second location.
2. An electrical connection within an integrated circuit package as recited in claim 1, wherein said electrically conductive plane comprises a ground plane.
3. An electrical connection within an integrated circuit package as recited in claim 2,' wherein said lead frame pin comprises a ground pin for dissipating voltage from the integrated circuit die.
4. An electrical connection within an integrated circuit package as recited in claim 1, wherein said electrically conductive plane comprises a power plane.
5. An electrical connection within an integrated circuit package as recited in claim 4, wherein said lead frame pin comprises a power pin for supplying voltage to the integrated circuit die.
6. An electrical connection within an integrated circuit package as recited in claim 1, wherein said electrically conductive plane comprises a ground plane, said ground plane including: a center section having a first thickness, and a circumferencial section located around an outer circumference of said center section, said circumferencial section having a second thickness less than said first thickness.
7. An electrical connection within an integrated circuit package as recited in claim 1, wherein said first tab is attached to said lead frame pin by welding, and wherein said second tab is attached to said electrically conductive plane by welding.
8. A method of reducing inductance in a pin on a lead frame within an integrated circuit die package, the pin transferring voltage between an integrated circuit die of the integrated circuit die package and at least one element external to the integrated die package, comprising the steps of:
(a) providing a first current flow path f om a first connection point between the integrated circuit die and lead frame to a second connection point between the lead frame and the at least one external element; (b) electrically coupling an electrical connector to the pin at a first location between the first and second connection points; and
(c) electrically coupling the electrical connector to the pin at a second location between the first and second connection points to thereby provide a second current flow path distinct from said first current flow path from said first connection point to said second connection point.
PCT/US1996/002001 1995-06-07 1996-02-15 Low inductance electrical ground connection integrated circuit die package WO1996041373A1 (en)

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JPH06310646A (en) * 1993-04-21 1994-11-04 Dainippon Printing Co Ltd Multilayer lead frame
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JPH02164056A (en) * 1988-12-19 1990-06-25 Hitachi Ltd Semiconductor device
JPH04127564A (en) * 1990-09-19 1992-04-28 Mitsui High Tec Inc Manufacture of lead frame
JPH04174549A (en) * 1990-11-07 1992-06-22 Mitsui High Tec Inc Semiconductor device
EP0534678A2 (en) * 1991-09-25 1993-03-31 AT&T Corp. Method of making electronic component packages
JPH05251624A (en) * 1992-03-05 1993-09-28 Hitachi Cable Ltd Multilayer lead frame
JPH06310646A (en) * 1993-04-21 1994-11-04 Dainippon Printing Co Ltd Multilayer lead frame
JPH0738049A (en) * 1993-07-23 1995-02-07 Sumitomo Metal Mining Co Ltd Composite lead frame

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