WO1996034410A1 - Chip cover - Google Patents

Chip cover Download PDF

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Publication number
WO1996034410A1
WO1996034410A1 PCT/DE1996/000718 DE9600718W WO9634410A1 WO 1996034410 A1 WO1996034410 A1 WO 1996034410A1 DE 9600718 W DE9600718 W DE 9600718W WO 9634410 A1 WO9634410 A1 WO 9634410A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
cover according
chip cover
pigmenting
added
Prior art date
Application number
PCT/DE1996/000718
Other languages
German (de)
French (fr)
Inventor
Alexandra Atzesdorfer
Detlef Houdeau
Peter Stampka
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1996034410A1 publication Critical patent/WO1996034410A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip.
  • Such chip covers protect the covered areas of the chip from damage caused by mechanical force and environmental influences.
  • the chip covers are transparent and therefore to a certain extent enable an optical analysis of the chip circuit. This in turn makes it possible to manipulate the chip circuit in a targeted manner.
  • the chip cards or smart cards used in the pay-TV sector may be mentioned as an example of this. If a hacker succeeds in analyzing the chip circuit opening the access to a certain TV program with regard to the position and function of individual components and / or the course of the conductor tracks within the chip, and finding possibilities by suitable ones Manipulating bridges or the like can enable him to use a paid service free of charge.
  • the present invention is therefore based on the object of developing the chip cover in accordance with the preamble of claim 1 in such a way that third-party analyzes and / or manipulations of chips can be reliably prevented.
  • a pigmenting agent is added to the cover.
  • pigmenting agents makes the cover non-transparent, so that external analyzes and manipulations of the chip can be reliably prevented.
  • the figure shows two stacked chips, the security-relevant areas of which are covered by a chip cover according to an exemplary embodiment of the invention. Although a section is shown, hatching has been omitted for reasons of clarity.
  • reference number 1 denotes a first chip without a housing in the form of a controller.
  • the Siemens SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as a controller.
  • the first chip 1 is attached to a system carrier 3 by means of an adhesive 2.
  • the system carrier 3 can be, for example, a plastic card for producing a chip card or smart card; however, it can also be a flexible printed circuit board or a so-called lead frame.
  • Conductor tracks 4 made of aluminum run on the upper surface of the first chip 1 according to the figure.
  • the conductor tracks 4 are covered by a first chip cover layer in the form of a structured Si nitride (Si3N4) layer 5.
  • This layer 5 serves to protect the chip against damage from environmental influences, in particular against damage from moisture and wetness.
  • a second chip cover layer 6 is provided over the Si3 layer 5.
  • the second chip cover layer 6 protects the underlying chip structures from mechanical damage.
  • cutouts are provided at which contact points 7 made of aluminum (Al pads) are exposed.
  • a second housing-free chip 8 is provided in the form of an ASIC component (customer-specific component).
  • the second chip 8 is glued to the previously mentioned second chip cover layer 6 by means of an adhesive 9.
  • the second chip 2 also has contact points 7 made of aluminum on its upper side according to the figure.
  • the contact points of the first chip and the contact points of the second chip are connected to one another by bonding wires 10.
  • the Globe Top 11 is preferably made of UV-curable epoxy resin and has a layer thickness of up to 500 ⁇ m.
  • the third-mentioned chip covering layer in the form of the globe top 11, which includes the entire arrangement, is the part of the chip covering to which the pigmenting agent is added according to the invention in the present exemplary embodiment.
  • the Globe Top 11 provided with pigmenting agents can also increase the operational safety of the enclosed chips.
  • the incidence of light on the housing-less chips can lead to the generation of free charge carriers, which in the worst case can make pn junctions conductive or change the potential of floating circuit points. Because the use of pigmentation agents not only blocks the view of the chips, but also the incidence of light there is prevented, these deficiencies can also be eliminated automatically.
  • the pigmenting agent is then advantageously selected in such a way that on the one hand it absorbs light in the visible wavelength range as strongly as possible, but only absorbs UV light to such a small extent that it is still complete with a reasonable amount of energy and time UV curing of the globe top is possible.
  • Organic pigments can also be used advantageously, since UV absorption can be influenced in a simple manner by an appropriate choice of the color of the pigment.
  • the security of the arrangement against external analysis and / or manipulation can also be increased by using primers (preferably silanes, metallic acid esters, thermoplastics etc.) to ensure greater adhesion between the globe top and the chips or the ones below lying
  • Cover layers are achieved so that removal of the cover layer preventing optical analysis in the form of the globe top is only possible by destroying the chip.
  • Another measure to increase security against third-party analysis and / or manipulation of chips is that the less security-relevant chip, i.e. in the present exemplary embodiment, the ASIC chip 2 exactly over a most security-relevant area of the other chip, i.e. in the present exemplary embodiment, it is arranged exactly above the most security-relevant area 12 of the controller chip 1.
  • the optical and the mechanical accessibility are additionally made more difficult in this way.
  • the exemplary embodiment described above concerned a so-called chip-on-chip-on-flex structure with chip-and-wire connection technology. It goes without saying that the invention is not limited to such a structure, but can also be used with individual chips and with any number of arbitrarily arranged and arbitrarily connected chips.
  • the pigmenting agent was added to the globe top.
  • the pigmenting agent can also be added to any other covering layer, including one not mentioned in the description of the exemplary embodiment.

Abstract

The description relates to a chip cover (6, 11) to cover completely or partially electrical, electronic, opto-electronic and/or electromechanical components of a chip (1, 8). The chip cover (6, 11) is characterized in that a pigmenting agent is added to the cover material. It is thus possible reliably to prevent unauthorised analyses and/or manipulations of the chip (1, 8).

Description

Beschreibungdescription
Chip-AbdeckungChip cover
Die vorliegende Erfindung bezieht sich auf eine Chip- Abdeckung zur vollständigen oder teilweisen Abdeckung von elektrischen, elektronischen, optoelektronischen und/oder elektromechanischen Komponenten eines Chips.The present invention relates to a chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip.
Derartige Chip-Abdeckungen schützen die abgedeckten Bereiche des Chips vor Beschädigungen durch mechanische Gewalt und Umwelteinflüsse.Such chip covers protect the covered areas of the chip from damage caused by mechanical force and environmental influences.
Bei auf Chip Cards, Smart Cards und dergleichen vorgesehenen Chips sind die Chip-Abdeckungen durchsichtig und ermöglichen mithin in gewissem Umfang eine optische Analyse der Chip- Schaltung. Dies wiederum macht es möglich, die Chip-Schaltung gezielt zu manipulieren.In the case of chips provided on chip cards, smart cards and the like, the chip covers are transparent and therefore to a certain extent enable an optical analysis of the chip circuit. This in turn makes it possible to manipulate the chip circuit in a targeted manner.
Die Möglichkeit der Durchführung derartiger Analysen und/oder Manipulationen der Chip-Schaltung ist unerwünscht, weil damit die Möglichkeit des Mißbrauchs besteht.The possibility of carrying out such analyzes and / or manipulations of the chip circuit is undesirable because there is a possibility of misuse.
Als Beispiel hierfür seien die auf dem Pay-TV-Sektor zum Ein- satz kommenden Chip Cards bzw. Smart Cards genannt. Gelingt es einem Hacker, die den Zugang zu einem bestimmten TV-Pro¬ gramm eröffnende Chip-Schaltung bezüglich der Lage und der Funktion einzelner Komponenten und/oder des Verlaufs der Leiterbahnen innerhalb des Chips zu analysieren und Möglich- keiten zu finden, diese durch geeignete Überbrückungen oder dergleichen zu manipulieren, so kann er dadurch in die Lage versetzt werden, einen kostenpflichtigen Service gratis zu benutzen.The chip cards or smart cards used in the pay-TV sector may be mentioned as an example of this. If a hacker succeeds in analyzing the chip circuit opening the access to a certain TV program with regard to the position and function of individual components and / or the course of the conductor tracks within the chip, and finding possibilities by suitable ones Manipulating bridges or the like can enable him to use a paid service free of charge.
Derartige Manipulationsmöglichkeiten sind nicht nur auf dem Pay-TV-Sektor, sondern bei allen Arten von zu Berechtigungs- kontrollen dienenden Chips von Bedeutung und eröffnen unzäh- lige Mißbrauchsmöglichkeiten, welche nicht nur finanzielle Verluste, sondern auch ein erhebliches Sicherheitsrisiko zur Folge haben können.Such manipulation options are important not only in the pay-TV sector, but also in all types of chips used for authorization checks and open up innumerable Possible misuse which can result not only in financial losses but also in a considerable security risk.
Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, die Chip-Abdeckung gemäß dem Oberbegriff des Patentanspruchs 1 derart weiterzubilden, daß Fremdanalysen und/oder Manipula¬ tionen von Chips zuverlässig verhinderbar sind.The present invention is therefore based on the object of developing the chip cover in accordance with the preamble of claim 1 in such a way that third-party analyzes and / or manipulations of chips can be reliably prevented.
Diese Aufgabe wird erfindungsgemäß durch die im kennzeichnen¬ den Teil des Patentanspruchs 1 beanspruchten Merkmale gelöst.According to the invention, this object is achieved by the features claimed in the characterizing part of patent claim 1.
Demnach ist vorgesehen, daß der Abdeckung ein Pigmentierungs- mittel zugesetzt ist.Accordingly, it is provided that a pigmenting agent is added to the cover.
Durch Zugabe von Pigmentierungsmittel wird die Abdeckung intransparent, so daß auf diese Weise Fremdanalysen und Manipulationen des Chips zuverlässig verhinderbar sind.The addition of pigmenting agents makes the cover non-transparent, so that external analyzes and manipulations of the chip can be reliably prevented.
Vorteilhafte Weiterbildungen sind Gegenstand der Unter¬ ansprüche.Advantageous further developments are the subject of the subclaims.
Die Erfindung wird nachfolgend anhand von Ausführungsbeispie¬ len unter Bezugnahme auf die Figur näher erläutert.The invention is explained in more detail below on the basis of exemplary embodiments with reference to the figure.
Die Figur zeigt zwei übereinandergesetzte Chips, deren sicherheitsrelevante Bereiche durch eine Chip-Abdeckung gemäß einem Ausführungsbeispiel der Erfindung abgedeckt sind. Es ist zwar ein Schnitt dargestellt, jedoch ist aus Gründen der Übersichtlichkeit auf eine Schraffur verzichtet worden.The figure shows two stacked chips, the security-relevant areas of which are covered by a chip cover according to an exemplary embodiment of the invention. Although a section is shown, hatching has been omitted for reasons of clarity.
In der Figur ist mit Bezugszeichen 1 ein erster gehäuseloser Chip in Form eines Controllers bezeichnet. Als Controller ist beispielsweise der Siemens-Baustein SLE 44C20 mit ROM, PROM, EEPROM und RAM einsetzbar. Der erste Chip 1 ist mittels eines Klebstoffes 2 auf einen Systemträger 3 befestigt.In the figure, reference number 1 denotes a first chip without a housing in the form of a controller. For example, the Siemens SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as a controller. The first chip 1 is attached to a system carrier 3 by means of an adhesive 2.
Der Systemträger 3 kann beispielsweise eine Kunststoffkarte zur Herstellung einer Chip Card oder Smart Card sein; es kann sich aber auch um eine flexible Leiterplatte oder um ein so¬ genanntes lead frame handeln.The system carrier 3 can be, for example, a plastic card for producing a chip card or smart card; however, it can also be a flexible printed circuit board or a so-called lead frame.
An der gemäß der Figur oberen Oberfläche des ersten Chips 1 verlaufen Leiterbahnen 4 aus Aluminium.Conductor tracks 4 made of aluminum run on the upper surface of the first chip 1 according to the figure.
Die Leiterbahnen 4 sind durch eine ersten Chip-Abdeckungs- schicht in Form einer Struktur-Si-Nitrid(Si3N4)-Schicht 5 bedeckt. Diese Schicht 5 dient dazu, den Chip vor Beschädi- gungen durch Umgebungseinflüsse, insbesondere vor Beschädi¬ gungen durch Feuchtigkeit und Nässe zu schützen.The conductor tracks 4 are covered by a first chip cover layer in the form of a structured Si nitride (Si3N4) layer 5. This layer 5 serves to protect the chip against damage from environmental influences, in particular against damage from moisture and wetness.
Über der Si3 -Schicht 5 ist eine zweite Chip-Abdeckungs- schicht 6 vorgesehen. Die zweite Chip-Abdeckungsschicht 6 schützt die darunterliegenden Chip-Strukturen vor mechani¬ schen Beschädigungen.A second chip cover layer 6 is provided over the Si3 layer 5. The second chip cover layer 6 protects the underlying chip structures from mechanical damage.
In den genannten Chip-Abdeckungsschichten 5 und 6 sind Aus¬ sparungen vorgesehen, an welchen Kontaktstellen 7 aus Alu- minium (Al-Pads) freigelegt sind.In the chip cover layers 5 and 6 mentioned, cutouts are provided at which contact points 7 made of aluminum (Al pads) are exposed.
Über dem ersten Chip 1 ist ein zweiter gehäuseloser Chip 8 in Form eines ASIC-Bausteins (kundenspezifischer Baustein) vor¬ gesehen.Above the first chip 1, a second housing-free chip 8 is provided in the form of an ASIC component (customer-specific component).
Der zweite Chip 8 ist mittels eines Klebstoffes 9 auf die zuvor bereits erwähnte zweite Chip-Abdeckungsschicht 6 aufgeklebt.The second chip 8 is glued to the previously mentioned second chip cover layer 6 by means of an adhesive 9.
Der zweite Chip 2 weist an seiner gemäß der Figur oberen Seite ebenfalls Kontaktstellen 7 aus Aluminium auf. Die Kontaktstellen des ersten Chips und die Kontaktstellen des zweiten Chips sind durch Bonddrähte 10 miteinander ver¬ bunden.The second chip 2 also has contact points 7 made of aluminum on its upper side according to the figure. The contact points of the first chip and the contact points of the second chip are connected to one another by bonding wires 10.
Die gesamte vorstehend beschriebene Anordnung ist von einer dritten Chip-Abdeckungschicht in Form eines sogenannten Globe Top 11 umgeben, welches dazu dient, die Anordnung vor Umge¬ bungseinflüssen und mechanischen Beschädigungen zu schützen. Das Globe Top 11 besteht im vorliegenden Fall vorzugsweise aus UV-härtbarem Epoxidharz und hat eine Schichtdicke von bis zu 500 um.The entire arrangement described above is surrounded by a third chip cover layer in the form of a so-called globe top 11, which serves to protect the arrangement from environmental influences and mechanical damage. In the present case, the Globe Top 11 is preferably made of UV-curable epoxy resin and has a layer thickness of up to 500 µm.
Die vorstehend beschriebene, in der Figur gezeigte Anordnung ist Teil einer Chip Card, Smart Card oder dergleichen.The arrangement described above and shown in the figure is part of a chip card, smart card or the like.
Die soeben erwähnte, die gesamte Anordnung einschließende dritte Chip-Abdeckungsschicht in Form des Globe Top 11 ist das Teil der Chip-Abdeckung, dem beim vorliegenden Ausfüh¬ rungsbeispiel erfindungsgemäß das Pigmentierungsmittel zuge- setzt ist.The third-mentioned chip covering layer in the form of the globe top 11, which includes the entire arrangement, is the part of the chip covering to which the pigmenting agent is added according to the invention in the present exemplary embodiment.
Das Zusetzen von Pigmentierungsmittel zum Globe Top macht die Chip-Abdeckung von allen Seiten intransparent. Unbefugte Dritte haben keine Chance zur optischen Analyse und/oder Manipulation der Chip-Schaltung(en) . Durch diesen Rundum- Schutz kann nicht einmal die Anzahl, die Anordnung und der Typ der abgedeckten Chips erkannt werden.The addition of pigment to the globe top makes the chip cover opaque from all sides. Unauthorized third parties have no chance of optical analysis and / or manipulation of the chip circuit (s). With this all-round protection, not even the number, the arrangement and the type of the covered chips can be recognized.
Das mit Pigmentierungsmittel versehene Globe Top 11 vermag auch die Betriebssicherheit der eingeschlossenen Chips zu er¬ höhen. Der Einfall von Licht auf die gehäuselosen Chips kann dort nämlich zur Erzeugung freier Ladungsträger führen, was im ungünstigsten Fall p-n-Übergänge leitend machen oder das Potential von floatenden Schaltungspunkten verändern kann. Da die Verwendung von Pigmentierungsmitteln nicht nur den Blick auf die Chips verwehrt, sondern auch den Lichteinfall dorthin unterbindet, sind damit automatisch auch diese Unzulänglich¬ keiten beseitigbar.The Globe Top 11 provided with pigmenting agents can also increase the operational safety of the enclosed chips. The incidence of light on the housing-less chips can lead to the generation of free charge carriers, which in the worst case can make pn junctions conductive or change the potential of floating circuit points. Because the use of pigmentation agents not only blocks the view of the chips, but also the incidence of light there is prevented, these deficiencies can also be eliminated automatically.
Die Tatsache, daß das Globe Top durch die Hinzufügung von Pigmentierungsmitteln gänzlich lichtundurchlässig werden kann, kann dazu führen, daß das Globe Top bei dessen Her¬ stellung keiner UV-Härtung mehr unterzogen werden kann. Eine Härtung durch UV-Licht ist nämlich nur dort möglich, wo UV- Licht auch hingelangen kann.The fact that the globe top can become completely opaque through the addition of pigmenting agents can lead to the fact that the globe top can no longer be subjected to UV curing when it is produced. Curing with UV light is only possible where UV light can get to.
Will man das Globe Top also bei dessen Herstellung einer UV- Härtung unterziehen, muß dies bei der Auswahl der zuzusetzen¬ den Pigmentierungsmittel besonders berücksichtigt werden.If one wants to subject the globe top to UV curing during its manufacture, this must be given special consideration when selecting the pigmenting agents to be added.
Vorteilhafter Weise erfolgt die Auswahl des Pigmentierungs- mittels dann derart, daß dieses einerseits Licht im sichtba¬ ren Wellenlängenbereich möglichst stark absorbiert, UV-Licht aber nur in einem so geringen Umfang absorbiert, daß bei einem vertretbaren Energie- und Zeitaufwand noch eine voll- ständige UV-Härtung des Globe Top möglich ist.The pigmenting agent is then advantageously selected in such a way that on the one hand it absorbs light in the visible wavelength range as strongly as possible, but only absorbs UV light to such a small extent that it is still complete with a reasonable amount of energy and time UV curing of the globe top is possible.
Entsprechende Überlegungen gelten auch für die Festlegung der Konzentration des Pigmentierungsmittels innerhalb des Globe Top.Corresponding considerations also apply to the determination of the concentration of the pigmenting agent within the globe top.
Als vorteilhaft hat es sich erwiesen, anorganische Pigmente in einer Konzentration von kleiner als 1 Gew.% beizufügen. Als Beispiel sei an dieser Stelle die Verwendung von Eisen(III)-Oxid (Fe2θj) mit 0,2 Gew.% erwähnt, wobei die Erfindung jedoch nicht auf dieses spezielle Beispiel be¬ schränkt ist.It has proven to be advantageous to add inorganic pigments in a concentration of less than 1% by weight. The use of iron (III) oxide (Fe2θ j ) with 0.2% by weight may be mentioned here as an example, but the invention is not restricted to this specific example.
Vorteilhaft einsetzbar sind auch organische Pigmente, denn hierbei ist die UV-Absorption auf einfache Weise durch eine entsprechende Wahl der Farbe des Pigments beeinflußbar. Die Sicherheit der Anordnung vor einer Fremdanalyse und/oder Manipulation kann darüber hinaus auch dadurch erhöht werden, daß durch Einsatz von Primer (vorzugsweise Silane, Metall¬ säureester, Thermoplaste usw.) eine stärkere Haftung zwischen dem Globe Top und den Chips bzw. den darunter liegendenOrganic pigments can also be used advantageously, since UV absorption can be influenced in a simple manner by an appropriate choice of the color of the pigment. The security of the arrangement against external analysis and / or manipulation can also be increased by using primers (preferably silanes, metallic acid esters, thermoplastics etc.) to ensure greater adhesion between the globe top and the chips or the ones below lying
Abdeckungsschichten erzielt wird, so daß eine Entfernung der die optische Analyse verwehrenden Abdeckungsschicht in Form des Globe Top nur unter Zerstörung des Chips möglich ist.Cover layers are achieved so that removal of the cover layer preventing optical analysis in the form of the globe top is only possible by destroying the chip.
Eine weitere Maßnahme zur Erhöhung der Sicherheit gegen Fremdanalysen und/oder Manipulationen von Chips besteht darin, daß der weniger sicherheitsrelevante Chip, d.h. im vorliegenden Ausführungsbeispiel der ASIC-Chip 2 genau über einen am meisten sicherheitsrelevanten Bereich des anderen Chips, d.h. im vorliegenden Ausführungsbeispiel genau über dem am meisten sicherheitsrelevanten Bereich 12 des Con¬ troller-Chips 1 angeordnet wird. Die optische und die mecha¬ nische Zugänglichkeit werden auf diese Weise zusätzlich er¬ schwert.Another measure to increase security against third-party analysis and / or manipulation of chips is that the less security-relevant chip, i.e. in the present exemplary embodiment, the ASIC chip 2 exactly over a most security-relevant area of the other chip, i.e. in the present exemplary embodiment, it is arranged exactly above the most security-relevant area 12 of the controller chip 1. The optical and the mechanical accessibility are additionally made more difficult in this way.
Das vorstehend beschriebene Ausführungsbeispiel betraf einen sogenannten chip-on-chip-on-flex-Aufbau mit einer chip-and- wire-Verbindungstechnologie. Es versteht sich von selbst, daß die Erfindung nicht auf einen derartigen Aufbau beschränkt ist, sondern auch bei Einzel-Chips und bei jeder beliebigen Anzahl von beliebig angeordneten und beliebig miteinander verbundenen Chips zum Einsatz kommen kann.The exemplary embodiment described above concerned a so-called chip-on-chip-on-flex structure with chip-and-wire connection technology. It goes without saying that the invention is not limited to such a structure, but can also be used with individual chips and with any number of arbitrarily arranged and arbitrarily connected chips.
Gemäß dem vorstehend geschriebenen Ausführungsbeispiel wurde das Pigmentierungsmittel dem Globe Top zugegeben. Das Pigmen¬ tierungsmittel kann stattdessen aber auch jedem beliebigen anderen, auch einer bei der Beschreibung des Ausführungsbei- spiels nicht genannten Abdeckungsschicht zugesetzt werden.According to the exemplary embodiment described above, the pigmenting agent was added to the globe top. Instead, the pigmenting agent can also be added to any other covering layer, including one not mentioned in the description of the exemplary embodiment.
Durch die beschriebene erfindungsgemäße Ausbildung der Chip- Abdeckung ist es weitgehend unabhängig von der Ausbildung der Anordnung auf einfache Weise möglich, Fremdanalysen und Mani¬ pulationen des Chips zuverlässig zu verhindern. Due to the inventive design of the chip cover, it is largely independent of the design of the Arrangement possible in a simple manner to reliably prevent third-party analyzes and manipulations of the chip.

Claims

Patentansprüche claims
1. Chip-Abdeckung zur vollständigen oder teilweisen Abdeckung von elektrischen, elektronischen und/oder elektro- mechanischen Komponenten eines Chips, d a d u r c h g e k e n n z e i c h n e t, daß der Abdeckung ein Pigmentierungsmittel zugesetzt ist.1. Chip cover for complete or partial covering of electrical, electronic and / or electromechanical components of a chip, so that a pigmentation agent is added to the cover.
2. Chip-Abdeckung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß durch die Abdeckung ein auf einer Chip Card oder einer Smart Card vorgesehener gehäuseloser Chip abdeckbar ist.2. Chip cover according to claim 1, so that a housing-less chip provided on a chip card or a smart card can be covered by the cover.
3. Chip -Abdeckung nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t, daß der Chip ein Controller- oder ein ASIC-Baustein ist.3. Chip cover according to claim 1 or 2, so that the chip is a controller or an ASIC component.
4. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e , daß die Chip-Abdeckung aus mehreren Schichten aufgebaut ist.4. Chip cover according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e that the chip cover is made up of several layers.
5. Chip -Abdeckung nach Anspruch 4, d a d u r c h g e k e n n z e i c h n e t, daß das Pigmentierungsmittel in einer äußeren Schicht vorge- sehen ist.5. Chip cover according to claim 4, so that the pigmenting agent is provided in an outer layer.
6. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß das Pigmentierungsmittel so beschaffen ist, daß es sieht- bares Licht gut absorbiert.6. Chip cover according to one of the preceding claims, d a d u r c h g e k e n e z e i c h n e t that the pigmenting agent is such that it absorbs visible light well.
7. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß das Pigmentierungsmittel so beschaffen ist, daß es UV- Licht schlecht absorbiert.7. Chip cover according to one of the preceding claims, that the pigmenting agent is such that it poorly absorbs UV light.
8. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß das Pigmentierungsmittel so beschaffen ist, daß es UV- Licht weniger absorbiert als sichtbares Licht.8. Chip cover according to one of the preceding claims, characterized in that the pigment is such that it absorbs UV light less than visible light.
9. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß als Pigmentierungsmittel anorganische oder organische Pigmente verwendet werden.9. Chip cover according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that inorganic or organic pigments are used as pigmenting agents.
10. Chip-Abdeckung nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e t, daß anorganische Pigmente in einer Konzentration von kleiner10. Chip cover according to claim 9, d a d u r c h g e k e n n z e i c h n e t that inorganic pigments in a concentration of less
1 Gew.% beigefügt werden.1% by weight can be added.
11. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß als Pigmentierungsmittel organische Farbpigmente verwen¬ det werden.11. Chip cover according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that organic color pigments are used as pigmenting agents.
12. Chip-Abdeckung nach Anspruch 11, d a d u r c h g e k e n n z e i c h n e t, daß durch eine entsprechende Auswahl der Farbe der Farbpig¬ mente die UV-Absorption eingestellt wird.12. Chip cover according to claim 11, so that the UV absorption is adjusted by an appropriate selection of the color of the color pigments.
13. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß der Abdeckung ein Primer zugesetzt ist.13. Chip cover according to one of the preceding claims, that a primer is added to the cover.
14. Chip-Abdeckung nach Anspruch 13, d a d u r c h g e k e n n z e i c h n e t, daß als Primer Silane, Metallsäureester oder Thermoplaste verwendet werden.14. Chip cover according to claim 13, d a d u r c h g e k e n n z e i c h n e t that silanes, metal acid esters or thermoplastics are used as primers.
15. Chip-Abdeckung nach einem der Ansprüche 5 bis 14, d a d u r c h g e k e n n z e i c h n e t, daß die das Pigmentierungsmittel enthaltende Schicht aus UV- härtbarem Harz besteht. 15. Chip cover according to one of claims 5 to 14, characterized in that the layer containing the pigmenting agent consists of UV-curable resin.
16. Chip -Abdeckung nach Anspruch 15, d a d u r c h g e k e n n z e i c h n e t, daß die Harzmatrix derart eingestellt ist, daß das Harz eine erhöhte Chemikalienbeständigkeit aufweist.16. Chip cover according to claim 15, so that the resin matrix is adjusted such that the resin has an increased chemical resistance.
17. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß über einem sicherheitsrelevanten Bereich des Chips ein zweiter Chip angeordnet ist. 17. Chip cover according to one of the preceding claims, that a second chip is arranged over a safety-relevant area of the chip.
PCT/DE1996/000718 1995-04-25 1996-04-24 Chip cover WO1996034410A1 (en)

Applications Claiming Priority (2)

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DE19515187.9 1995-04-25

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DE19929754C2 (en) * 1999-06-29 2001-08-16 Siemens Ag Potting an assembled component with vibration-damping casting compound
DE102004039693B4 (en) * 2004-08-16 2009-06-10 Infineon Technologies Ag Potting compound, chip module and method for producing a chip module

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EP0510433A2 (en) * 1991-04-26 1992-10-28 Hughes Aircraft Company Secure circuit structure
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