WO1996034411A1 - Chip cover - Google Patents

Chip cover Download PDF

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Publication number
WO1996034411A1
WO1996034411A1 PCT/DE1996/000719 DE9600719W WO9634411A1 WO 1996034411 A1 WO1996034411 A1 WO 1996034411A1 DE 9600719 W DE9600719 W DE 9600719W WO 9634411 A1 WO9634411 A1 WO 9634411A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
cover according
chip cover
layer
polyimide layer
Prior art date
Application number
PCT/DE1996/000719
Other languages
German (de)
French (fr)
Inventor
Alexandra Atzesdorfer
Heiner Bayer
Detlef Houdeau
Peter Stampka
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1996034411A1 publication Critical patent/WO1996034411A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806—Details of the card
    • G07F7/0813—Specific details related to card security
    • G07F7/082—Features insuring the integrity of the data on or in the card
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/01068—Erbium [Er]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip.
  • Such chip covers protect the covered areas of the chip from damage caused by mechanical force and environmental influences.
  • the chip covers are transparent and therefore to a certain extent enable an optical analysis of the chip circuit. This in turn makes it possible to manipulate the chip circuit in a targeted manner.
  • the chip cards or smart cards used in the pay-TV sector may be mentioned as an example of this. If a hacker succeeds in analyzing the chip circuit opening the access to a certain TV program with regard to the position and function of individual components and / or the course of the conductor tracks within the chip, and finding possibilities by suitable ones Manipulating bridges or the like can enable him to use a paid service free of charge.
  • the present invention is therefore based on the object of developing the chip cover in accordance with the preamble of claim 1 in such a way that third-party analyzes and / or manipulations of chips can be reliably prevented.
  • the cover has a polyimide layer with limited transparency.
  • the polyimides used according to the invention are materials which, even without the addition of pigments, can be non-transparent even with layer thicknesses of a few ⁇ m.
  • a correspondingly close arrangement of the layer on the chip can furthermore ensure that the layer, despite its small thickness, cannot be removed without destroying the chip.
  • the invention is explained in more detail below on the basis of exemplary embodiments with reference to the figure.
  • the figure shows two stacked chips, the security-relevant areas of which are covered by a chip cover according to an exemplary embodiment of the invention. Although a section is shown, hatching has been omitted for reasons of clarity.
  • reference number 1 denotes a first chip without a housing in the form of a controller.
  • the Siemens SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as a controller.
  • the first chip 1 is attached to a system carrier 3 by means of an adhesive 2.
  • the system carrier 3 can be, for example, a plastic card for producing a chip card or smart card; however, it can also be a flexible printed circuit board or a so-called lead frame.
  • Conductor tracks 4 made of aluminum run on the upper surface of the first chip 1 according to the figure.
  • the conductor tracks 4 are covered by a first chip cover layer in the form of a structured Si nitride (Si3N4) layer 5.
  • This layer 5 serves to protect the chip against damage from environmental influences, in particular against damage from moisture and wetness.
  • the thickness of this layer is 500 - 1400 nm.
  • a second chip covering layer in the form of a polyimide layer 6 is provided above the Si3N layer 5.
  • the polyimide layer 6 is impermeable even at a layer thickness of a few microns even without the addition of pigmentation substances visible, so that an optical analysis of the underlying chip structure can be reliably prevented.
  • the polyimide layer 6 also has the advantage that it protects the underlying chip or the underlying chip areas from mechanical damage.
  • polyimide is also able to relieve stresses due to temperature differences in adjacent components and / or as a result of different thermal expansion coefficients of adjacent components and / or as a result of deformations of the chip card or smart card carrying the chip, etc. to compensate by mechanically decoupling the components causing the stresses.
  • the polyimide 6 is not soluble in common solvents such as acetone, tuluol and the like, so that it is consequently not easily possible to analyze and / or manipulate the chip circuit while removing the polyimide layer.
  • cutouts are provided at which contact points 7 made of aluminum (Al pads) are exposed.
  • a second housing-free chip 8 is provided in the form of an ASIC component (customer-specific component).
  • the second chip 8 is glued to the previously mentioned polyimide layer 6 by means of an adhesive 9.
  • the second chip 2 also has contact points 7 made of aluminum on its upper side according to the figure.
  • the contact points of the first chip and the contact points of the second chip are connected to one another by bonding wires 10.
  • the Globe Top 11 is made of epoxy resin.
  • the polyimide layer is practically opaque even with a layer thickness of 3 ⁇ .
  • the currently preferred layer thickness is 7-10 ⁇ m.
  • the analysis of the chip circuit by means of long-wave light can also be prevented by changing the consistency of the polyimide used and / or by adding appropriate additives to the polyimide.
  • controller chip 1 and an ASIC chip 2 are interconnected, the safety-relevant areas of these chips are generally located on the controller chip.
  • the controller chip 1 is therefore provided with a polyimide cover.
  • Another measure to increase security against third-party analysis and / or manipulation of chips is that the less security-relevant chip, i.e. in the present exemplary embodiment, the ASIC chip 2 exactly over a most security-relevant area of the other chip, i.e. in the present exemplary embodiment, it is arranged exactly above the most security-relevant area 12 of the controller chip 1. In this way, the optical and mechanical accessibility are additionally made more difficult.
  • the exemplary embodiment described above concerned a so-called chip-on-chip-on-flex structure with chip-and-wire connection technology. It goes without saying that the invention is not limited to such a structure, but can also be used with individual chips and with any number of arbitrarily arranged and arbitrarily connected chips.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Business, Economics & Management (AREA)
  • General Engineering & Computer Science (AREA)
  • Strategic Management (AREA)
  • General Business, Economics & Management (AREA)
  • Accounting & Taxation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

The description relates to a chip cover (6) to cover completely or partially electrical, electronic, opto-electronic and/or electromechanical components of a chip (1, 8). The chip cover (6) is characterized in that is has a polyimide coating with limited transparency. It is thus possible reliably to prevent unauthorised examinations and/or manipulations of the chip.

Description

Beschreibungdescription
Chip-AbdeckungChip cover
Die vorliegende Erfindung bezieht sich auf eine Chip- Abdeckung zur vollständigen oder teilweisen Abdeckung von elektrischen, elektronischen, optoelektronischen und/oder elektromechanischen Komponenten eines Chips.The present invention relates to a chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip.
Derartige Chip-Abdeckungen schützen die abgedeckten Bereiche des Chips vor Beschädigungen durch mechanische Gewalt und Umgebungseinflüsse.Such chip covers protect the covered areas of the chip from damage caused by mechanical force and environmental influences.
Bei auf Chip Cards, Smart Cards und dergleichen vorgesehenen Chips sind die Chip-Abdeckungen durchsichtig und ermöglichen mithin in gewissem Umfang eine optische Analyse der Chip- Schaltung. Dies wiederum macht es möglich, die Chip-Schaltung gezielt zu manipulieren.In the case of chips provided on chip cards, smart cards and the like, the chip covers are transparent and therefore to a certain extent enable an optical analysis of the chip circuit. This in turn makes it possible to manipulate the chip circuit in a targeted manner.
Die Möglichkeit der Durchführung derartiger Analysen und/oder Manipulationen der Chip-Schaltung ist unerwünscht, weil damit die Möglichkeit des Mißbrauchs besteht.The possibility of carrying out such analyzes and / or manipulations of the chip circuit is undesirable because there is a possibility of misuse.
Als Beispiel hierfür seien die auf dem Pay-TV-Sektor zum Ein- satz kommenden Chip Cards bzw. Smart Cards genannt. Gelingt es einem Hacker, die den Zugang zu einem bestimmten TV-Pro¬ gramm eröffnende Chip-Schaltung bezüglich der Lage und der Funktion einzelner Komponenten und/oder des Verlaufs der Leiterbahnen innerhalb des Chips zu analysieren und Möglich- keiten zu finden, diese durch geeignete Oberbrückungen oder dergleichen zu manipulieren, so kann er dadurch in die Lage versetzt werden, einen kostenpflichtigen Service gratis zu benutzen.The chip cards or smart cards used in the pay-TV sector may be mentioned as an example of this. If a hacker succeeds in analyzing the chip circuit opening the access to a certain TV program with regard to the position and function of individual components and / or the course of the conductor tracks within the chip, and finding possibilities by suitable ones Manipulating bridges or the like can enable him to use a paid service free of charge.
Derartige Manipulationsmöglichkeiten sind nicht nur auf dem Pay-TV-Sektor, sondern bei allen Arten von zu Berechtigungs¬ kontrollen dienenden Chips von Bedeutung und eröffnen unzäh- 2 lige Mißbrauchsmöglichkeiten, welche nicht nur finanzielle Verluste, sondern auch ein erhebliches Sicherheitsrisiko zur Folge haben können.Such manipulation options are important not only in the pay-TV sector, but in all types of chips used for authorization checks and open up innumerable 2 possible abuses, which can result not only in financial losses, but also in a considerable security risk.
Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, die Chip-Abdeckung gemäß dem Oberbegriff des Patentanspruchs 1 derart weiterzubilden, daß Fremdanalysen und/oder Manipula¬ tionen von Chips zuverlässig verhinderbar sind.The present invention is therefore based on the object of developing the chip cover in accordance with the preamble of claim 1 in such a way that third-party analyzes and / or manipulations of chips can be reliably prevented.
Diese Aufgabe wird erfindungsgemäß durch die im kennzeichnen¬ den Teil des Patentanspruchs 1 beanspruchten Merkmale gelöst.According to the invention, this object is achieved by the features claimed in the characterizing part of patent claim 1.
Demnach ist vorgesehen, daß die Abdeckung eine Polyimid- Schicht mit eingeschränkter Transparenz aufweist.Accordingly, it is provided that the cover has a polyimide layer with limited transparency.
Die erfindungsge äß eingesetzten Polyimide sind Materialien, die auch ohne Zugabe von Pig entierungsstoffen schon bei Schichtdicken von wenigen μm intransparent sein können.The polyimides used according to the invention are materials which, even without the addition of pigments, can be non-transparent even with layer thicknesses of a few μm.
Die Verwendung dieses Materials nur in einer Schicht erlaubt bei entsprechender Anordnung und entsprechender flächen- und dickenmäßiger Ausdehnung einen sehr sparsamen Umgang mit dem Material.The use of this material only in one layer allows for a very economical use of the material with the appropriate arrangement and corresponding expansion in terms of area and thickness.
Durch entsprechend nahe Anordnung der Schicht am Chip kann darüber hinaus erreicht werden, daß die Schicht trotz ihrer geringen Dicke nicht entfernt werden kann, ohne den Chip zu zerstören.A correspondingly close arrangement of the layer on the chip can furthermore ensure that the layer, despite its small thickness, cannot be removed without destroying the chip.
Fremdanalysen und Manipulationen des Chips sind somit zuver¬ lässig verhinderbar.External analyzes and manipulations of the chip can thus be reliably prevented.
Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche.Advantageous developments of the invention are the subject of the dependent claims.
Die Erfindung wird nachfolgend anhand von Ausführungsbeispie- len unter Bezugnahme auf die Figur näher erläutert. Die Figur zeigt zwei übereinandergesetzte Chips, deren sicherheitsrelevante Bereiche durch eine Chip-Abdeckung gemäß einem Ausführungsbeispiel der Erfindung abgedeckt sind. Es ist zwar ein Schnitt dargestellt, jedoch ist aus Gründen der Übersichtlichkeit auf eine Schraffur verzichtet worden.The invention is explained in more detail below on the basis of exemplary embodiments with reference to the figure. The figure shows two stacked chips, the security-relevant areas of which are covered by a chip cover according to an exemplary embodiment of the invention. Although a section is shown, hatching has been omitted for reasons of clarity.
In der Figur ist mit Bezugszeichen 1 ein erster gehäuseloser Chip in Form eines Controllers bezeichnet. Als Controller ist beispielsweise der Siemens-Baustein SLE 44C20 mit ROM, PROM, EEPROM und RAM einsetzbar.In the figure, reference number 1 denotes a first chip without a housing in the form of a controller. For example, the Siemens SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as a controller.
Der erste Chip 1 ist mittels eines Klebstoffes 2 auf einen Systemträger 3 befestigt.The first chip 1 is attached to a system carrier 3 by means of an adhesive 2.
Der Systemträger 3 kann beispielsweise eine Kunststoffkarte zur Herstellung einer Chip Card oder Smart Card sein; es kann sich aber auch um eine flexible Leiterplatte oder um ein so¬ genanntes lead frame handeln.The system carrier 3 can be, for example, a plastic card for producing a chip card or smart card; however, it can also be a flexible printed circuit board or a so-called lead frame.
An der gemäß der Figur oberen Oberfläche des ersten Chips 1 verlaufen Leiterbahnen 4 aus Aluminium.Conductor tracks 4 made of aluminum run on the upper surface of the first chip 1 according to the figure.
Die Leiterbahnen 4 sind durch eine ersten Chip-Abdeckungs- schicht in Form einer Struktur-Si-Nitrid(Si3N4)-Schicht 5 bedeckt. Diese Schicht 5 dient dazu, den Chip vor Beschädi¬ gungen durch Umgebungseinflüsse, insbesondere vor Beschädi¬ gungen durch Feuchtigkeit und Nässe zu schützen. Die Dicke dieser Schicht beträgt 500 - 1400 nm.The conductor tracks 4 are covered by a first chip cover layer in the form of a structured Si nitride (Si3N4) layer 5. This layer 5 serves to protect the chip against damage from environmental influences, in particular against damage from moisture and wetness. The thickness of this layer is 500 - 1400 nm.
Ober der Si3N -Schicht 5 ist erfindungsgemäß eine zweite Chip-Abdeckungsschicht in Form einer Polyimid-Schicht 6 vor¬ gesehen.According to the invention, a second chip covering layer in the form of a polyimide layer 6 is provided above the Si3N layer 5.
Die Polyimid-Schicht 6 ist auch ohne Zugabe von Pigmentie- rungsstoffen schon bei Schichtdicken von wenigen um undurch- sichtig, so daß eine optische Analyse der darunter liegenden Chip-Struktur zuverlässig verhinderbar ist.The polyimide layer 6 is impermeable even at a layer thickness of a few microns even without the addition of pigmentation substances visible, so that an optical analysis of the underlying chip structure can be reliably prevented.
Die Polyimid-Schicht 6 weist ferner den Vorteil auf, daß sie den darunter liegenden Chip bzw. die darunter liegenden Chip- Bereiche vor mechanischen Beschädigungen schützt.The polyimide layer 6 also has the advantage that it protects the underlying chip or the underlying chip areas from mechanical damage.
Infolge seiner weichen und flexiblen Materialeigenschaften ist Polyimid auch in der Lage, Spannungen infolge von Tempe- raturunterschieden an benachbarten Komponenten und/oder in¬ folge von unterschiedlichen Temperaturausdehnungkoeffizienten benachbarter Komponenten und/oder infolge von Deformierungen der den Chip tragenden Chip Card oder Smart Card usw. auszu¬ gleichen, indem es die die Spannungen verursachenden Kompo- nenten mechanisch entkoppelt.As a result of its soft and flexible material properties, polyimide is also able to relieve stresses due to temperature differences in adjacent components and / or as a result of different thermal expansion coefficients of adjacent components and / or as a result of deformations of the chip card or smart card carrying the chip, etc. to compensate by mechanically decoupling the components causing the stresses.
Zudem ist das Polyimid 6 in gängigen Lösungsmitteln wie Ace- ton, Tuluol und dergleichen nicht löslich, so daß es folglich auch nicht ohne weiteres möglich ist, die Chip-Schaltung unter Entfernung der Polyimid-Schicht zu analysieren und/oder zu manipulieren.In addition, the polyimide 6 is not soluble in common solvents such as acetone, tuluol and the like, so that it is consequently not easily possible to analyze and / or manipulate the chip circuit while removing the polyimide layer.
In den genannten Chip-Abdeckungsschichten 5 und 6 sind Aus¬ sparungen vorgesehen, an welchen Kontaktstellen 7 aus Alu- minium (Al-Pads) freigelegt sind.In the chip cover layers 5 and 6 mentioned, cutouts are provided at which contact points 7 made of aluminum (Al pads) are exposed.
Über dem ersten Chip 1 ist ein zweiter gehäuseloser Chip 8 in Form eines ASIC-Bausteins (kundenspezifischer Baustein) vor¬ gesehen.Above the first chip 1, a second housing-free chip 8 is provided in the form of an ASIC component (customer-specific component).
Der zweite Chip 8 ist mittels eines Klebstoffes 9 auf die zuvor bereits erwähnte Polyimid-Schicht 6 aufgeklebt.The second chip 8 is glued to the previously mentioned polyimide layer 6 by means of an adhesive 9.
Der zweite Chip 2 weist an seiner gemäß der Figur oberen Seite ebenfalls Kontaktstellen 7 aus Aluminium auf. Die Kontaktstellen des ersten Chips und die Kontaktstellen des zweiten Chips sind durch Bonddrähte 10 miteinander ver¬ bunden.The second chip 2 also has contact points 7 made of aluminum on its upper side according to the figure. The contact points of the first chip and the contact points of the second chip are connected to one another by bonding wires 10.
Die gesamte vorstehend beschriebene Anordnung ist von einer dritten Chip-Abdeckungschicht in Form eines sogenannten Globe Top 11 umgeben, welches dazu dient, die Anordnung vor Umge¬ bungseinflüssen und mechanischen Beschädigungen zu schützen. Das Globe Top 11 besteht im vorliegenden Fall aus Epoxidharz.The entire arrangement described above is surrounded by a third chip cover layer in the form of a so-called globe top 11, which serves to protect the arrangement from environmental influences and mechanical damage. In the present case, the Globe Top 11 is made of epoxy resin.
Die vorstehend beschriebene, in der Figur gezeigte Anordnung ist Teil einer Chip Card, Smart Card oder dergleichen.The arrangement described above and shown in the figure is part of a chip card, smart card or the like.
Wenngleich die vorstehend beschriebene erfindungsgemäße Polyimid-Schicht schon einen sehr guten Schutz gegen Fremd¬ analysen und/oder Manipulationen der Chip-Schaltung bietet, läßt sich dieser doch durch Vorsehen der nachfolgend erläu¬ terten Maßnahmen nochmals deutlich steigern.Although the polyimide layer according to the invention described above already offers very good protection against external analysis and / or manipulation of the chip circuit, this can be significantly increased again by providing the measures explained below.
Die Polyimid-Schicht ist bereits bei einer Schichtdicke von 3 μ praktisch undurchsichtig. Um auch die Analyse der darunter liegenden Chip-Schaltung mittels langwelligerem Licht aus¬ zuschließen bzw. zumindest erheblich zu erschweren, hat es sich als günstig erwiesen, die Schichtdicke bis auf ca. 20 um zu erhöhen. Die derzeit bevorzugte Schichtdicke liegt bei 7 - 10 μm.The polyimide layer is practically opaque even with a layer thickness of 3 μ. In order to also exclude or at least considerably complicate the analysis of the underlying chip circuit by means of long-wave light, it has proven to be advantageous to increase the layer thickness to approximately 20 .mu.m. The currently preferred layer thickness is 7-10 μm.
Die Analyse der Chip-Schaltung mittels langwelligem Licht ist stattdessen oder ergänzend hierzu auch durch eine Veränderung der Konsistenz des verwendeten Polyimids und/oder durch eine Hinzufügung von entsprechenden Additiven zum Polyimid verhin¬ derbar.Instead of or in addition to this, the analysis of the chip circuit by means of long-wave light can also be prevented by changing the consistency of the polyimide used and / or by adding appropriate additives to the polyimide.
Entsprechendes gilt auch für die Verhinderung der Analyse der Chip-Schaltung mittels kurzwelliger Strahlung wie beispiels¬ weise Elektronenstrahlung; eine derartige Analyse ist eben¬ falls durch eine Veränderung der Dicke der Polyimidschicht, eine Veränderung der Konsistenz des verwendeten Polyimids und/oder eine Hinzufügung von entsprechenden Additiven zum Polyimid verhinderbar.The same also applies to the prevention of the analysis of the chip circuit by means of short-wave radiation such as electron radiation; Such an analysis is also possible by changing the thickness of the polyimide layer, a change in the consistency of the polyimide used and / or the addition of appropriate additives to the polyimide can be prevented.
Durch die Anordnung der Polyimid-Schicht direkt über dem Chip (unter Zwischenschaltung der Si3N4-Schicht) und durch Be¬ schränkung der flächenmäßigen Ausdehnung der Schicht im we¬ sentlichen auf die zu schützenden Bereiche des Chips kann ein äußerst sparsamer Umgang mit Polyimid erreicht werden.By arranging the polyimide layer directly over the chip (with the interposition of the Si3N4 layer) and by restricting the areal extent of the layer essentially to the areas of the chip to be protected, extremely economical use of polyimide can be achieved.
Wenn, wie in der Figur gezeigt ist, ein Controller-Chip 1 und ein ASIC-Chip 2 miteinander verschaltet werden, befinden sich die sicherheitsrelevanten Bereiche dieser Chips in der Regel auf dem Controller-Chip. Bei dem in der Figur gezeigten Aus- führungsbeispiel ist daher nur der Controller-Chip 1 mit einer Polyimid-Abdeckung versehen.If, as shown in the figure, a controller chip 1 and an ASIC chip 2 are interconnected, the safety-relevant areas of these chips are generally located on the controller chip. In the exemplary embodiment shown in the figure, only the controller chip 1 is therefore provided with a polyimide cover.
Wenngleich Polyimid mit steigender Schichtdicke sehr schnell intransparent wird, kann, um die vorzusehende Schichtdicke für einige Anwendungsfälle (beispielsweise zur Verringerung der Dicke des Chips oder zur einfacheren Herstellung der Polyimid-Schicht) zu verringern, vorgesehen werden, die op¬ tische Intransparenz der Polyimid-Schicht durch Beigabe von Pigmentierungs-Additiven noch weiter zu erhöhen. Um einer- seitε die vorteilhaften Eigenschaften des Polyimid zu erhal¬ ten, und um andererseits die optische Intransparenz wirkungs¬ voll zu erhöhen, ist es erforderlich, die Additive bezüglich Farbe, mechanischer Eigenschaften und Sedimentation speziell anzupassen. Als vorteilhaft hat sich die Verwendung von einem von der Firma Degussa bezogenen nicht leitenden Ruß (0,2 bis 2 Gew.%, 20 - 30 n Korngröße) erwiesen.Although polyimide becomes opaque very quickly with increasing layer thickness, in order to reduce the layer thickness to be provided for some applications (for example to reduce the thickness of the chip or to simplify the production of the polyimide layer), the optical non-transparency of the polyimide To increase the layer even further by adding pigmentation additives. In order on the one hand to maintain the advantageous properties of the polyimide and on the other hand to effectively increase the optical non-transparency, it is necessary to specifically adapt the additives with regard to color, mechanical properties and sedimentation. The use of a non-conductive carbon black (0.2 to 2% by weight, 20-30 n grain size) obtained from Degussa has proven to be advantageous.
Neben der optischen Intransparenz der Polyimid-Schicht ver¬ dienen auch dessen Adhäsionseigenschaften besondere Beach- tung. Je stärker die Polyimid-Schicht auf dem Chip haftet, desto schwieriger ist es, diese Schicht ohne Beschädigung der darunter liegenden Strukturen zu entfernen. Es hat sich gezeigt daß die Adhäsion der Polyimid-Schicht durch Primer-Additive steigerbar ist, die auf Silan-Basis aufgebaut sind (Firma Hüls, Firma OCG) und der Polyimid- Vorstufe zugesetzt werden.In addition to the optical non-transparency of the polyimide layer, its adhesion properties also deserve special attention. The more the polyimide layer adheres to the chip, the more difficult it is to remove this layer without damaging the underlying structures. It has been shown that the adhesion of the polyimide layer can be increased by means of primer additives which are based on silane (company Hüls, company OCG) and are added to the polyimide precursor.
Eine weitere Maßnahme zur Erhöhung der Sicherheit gegen Fremdanalysen und/oder Manipulationen von Chips besteht darin, daß der weniger sicherheitsrelevante Chip, d.h. im vorliegenden Ausführungsbeispiel der ASIC-Chip 2 genau über einen am meisten sicherheitsrelevanten Bereich des anderen Chips, d.h. im vorliegenden Ausführungsbeispiel genau über dem am meisten sicherheitsrelevanten Bereich 12 des Con¬ troller-Chips 1 angeordnet wird. Die optische und die mecha- nische Zugänglichkeit werden auf diese Weise zusätzlich er¬ schwert.Another measure to increase security against third-party analysis and / or manipulation of chips is that the less security-relevant chip, i.e. in the present exemplary embodiment, the ASIC chip 2 exactly over a most security-relevant area of the other chip, i.e. in the present exemplary embodiment, it is arranged exactly above the most security-relevant area 12 of the controller chip 1. In this way, the optical and mechanical accessibility are additionally made more difficult.
Das vorstehend beschriebene Ausführungsbeispiel betraf einen sogenannten chip-on-chip-on-flex-Aufbau mit einer chip-and- wire-Verbindungstechnologie. Es versteht sich von selbst, daß die Erfindung nicht auf einen derartigen Aufbau beschränkt ist, sondern auch bei Einzel-Chips und bei jeder beliebigen Anzahl von beliebig angeordneten und beliebig miteinander verbundenen Chips zum Einsatz kommen kann.The exemplary embodiment described above concerned a so-called chip-on-chip-on-flex structure with chip-and-wire connection technology. It goes without saying that the invention is not limited to such a structure, but can also be used with individual chips and with any number of arbitrarily arranged and arbitrarily connected chips.
Durch die beschriebene erfindungsgemäße Ausbildung der Chip- Abdeckung ist es weitgehend unabhängig von der Ausbildung der Anordnung auf einfache Weise möglich, Fremdanalysen und Mani¬ pulationen des Chips zuverlässig zu verhindern. Due to the described design of the chip cover according to the invention, it is largely possible, independently of the design of the arrangement, to reliably prevent external analyzes and manipulations of the chip.

Claims

Patentansprüche claims
1. Chip-Abdeckung zur vollständigen oder teilweisen Ab¬ deckung von elektrischen, elektronischen, optoelektronischen und/oder elektromechanisehen Komponenten eines Chips, d a d u r c h g e k e n n z e i c h n e t, daß die Abdeckung eine Polyimid-Schicht mit eingeschränkter Transparenz aufweist.1. Chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip, so that the cover has a polyimide layer with limited transparency.
2. Chip-Abdeckung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß durch die Abdeckung ein auf einer Chip Card oder einer2. Chip cover according to claim 1, d a d u r c h g e k e n n z e i c h n e t that through the cover one on a chip card or one
Smart Card vorgesehener gehäuseloser Chip abdeckbar ist.Smart card provided housing-less chip can be covered.
3. Chip-Abdeckung nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t, daß der Chip ein Controller- oder ein ASIC-Baustein ist.3. Chip cover according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the chip is a controller or an ASIC chip.
4. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Polyimid-Schicht direkt über dem Chip vorgesehen ist.4. Chip cover according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the polyimide layer is provided directly above the chip.
5. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Polyimid-Schicht eine flächenmäßige Ausdehnung auf¬ weist, die im wesentlichen mit dem zu schützenden Bereich des Chips zusammenfällt.5. Chip cover according to one of the preceding claims, that the polyimide layer has an areal expansion which essentially coincides with the area of the chip to be protected.
6. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Schichtdicke der Polyimid-Schicht 3 - 20 μm beträgt.6. Chip cover according to one of the preceding claims, that the layer thickness of the polyimide layer is 3-20 μm.
7. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Schichtdicke der Polyimid-Schicht vorzugsweise 7 - 10 μm beträgt. 97. Chip cover according to one of the preceding claims, characterized in that the layer thickness of the polyimide layer is preferably 7 - 10 microns. 9
8. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß der Polyimid-Schicht Pigmentierungs-Additive zugesetzt sind.8. Chip cover according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that pigment additives are added to the polyimide layer.
9. Chip-Abdeckung nach Anspruch 8, d a d u r c h g e k e n n z e i c h n e t, daß nichtleitender Ruß als Pigmentierungs-Additiv verwendet wird.9. Chip cover according to claim 8, d a d u r c h g e k e n n z e i c h n e t that non-conductive carbon black is used as a pigmentation additive.
10. Chip-Abdeckung nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e t, daß der verwendete Ruß eine Korngröße von 20 - 30 nm auf¬ weist.10. Chip cover according to claim 9, so that the soot used has a grain size of 20-30 nm.
11. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß der Polyimid-Schicht Primer-Additive zugesetzt sind.11. Chip cover according to one of the preceding claims, that the primer additives have been added to the polyimide layer.
12. Chip-Abdeckung nach Anspruch 11, d a d u r c h g e k e n n z e i c h n e t, daß die Primer-Additive auf Silan-Basis aufgebaut sind.12. Chip cover according to claim 11, d a d u r c h g e k e n n z e i c h n e t that the primer additives are based on silane.
13. Chip-Abdeckung nach einem der Ansprüche 11 und 12, d a d u r c h g e k e n n z e i c h n e t, daß die Primer-Additive der Polyimid-Vorstufe zugesetzt wer¬ den.13. Chip cover according to one of claims 11 and 12, so that the primer additives of the polyimide precursor are added.
14. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß über einem sicherheitsrelevanten Bereich des Chips ein zweiter Chip angeordnet ist.14. Chip cover according to one of the preceding claims, that a second chip is arranged over a safety-relevant area of the chip.
15. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e , daß die Chip-Abdeckung aus mehreren Schichten aufgebaut ist. 15. Chip cover according to one of the preceding claims, characterized in that the chip cover is constructed from several layers.
16. Chip -Abdeckung nach Anspruch 15, d a d u r c h g e k e n n z e i c h n e t, daß die Polyimid-Schicht eine nahe am Chip liegende Schicht ist. 16. Chip cover according to claim 15, so that the polyimide layer is a layer close to the chip.
PCT/DE1996/000719 1995-04-25 1996-04-24 Chip cover WO1996034411A1 (en)

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