WO1996027899A1 - Procede d'attaque au plasma d'une structure en oxyde/silicium polycristallin siliciure - Google Patents

Procede d'attaque au plasma d'une structure en oxyde/silicium polycristallin siliciure Download PDF

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Publication number
WO1996027899A1
WO1996027899A1 PCT/EP1996/000922 EP9600922W WO9627899A1 WO 1996027899 A1 WO1996027899 A1 WO 1996027899A1 EP 9600922 W EP9600922 W EP 9600922W WO 9627899 A1 WO9627899 A1 WO 9627899A1
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WIPO (PCT)
Prior art keywords
layer
etching
flow rate
seem
chamber
Prior art date
Application number
PCT/EP1996/000922
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English (en)
Inventor
Pascal Costaganna
François Martinet
Original Assignee
International Business Machines Corporation
Ibm France
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP95480015A external-priority patent/EP0731501A1/fr
Application filed by International Business Machines Corporation, Ibm France filed Critical International Business Machines Corporation
Priority to JP8526605A priority Critical patent/JPH09509017A/ja
Publication of WO1996027899A1 publication Critical patent/WO1996027899A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Definitions

  • the present invention relates to the manufacture of semiconductor integrated circuits and more particularly to an improved method for plasma etching an oxide/polycide structure consisting of a top silicon oxide (SiO2) layer, an intermediate refractory metal suicide layer and a bottom polycrystalline silicon (polysilicon) layer forming a stack.
  • a stack is formed onto a silicon substrate coated with a thin layer of silicon oxide, which serves as the gate dielectric of the said IGFET transistors.
  • the stack is usually referred to in the technical literature as the gate electrode stack.
  • this stack is patterned to define the gate electrode lines or more generally the gate conductor lines because they are also used as the word lines in the memory array.
  • Fig. 1 A schematically illustrates a portion of a wafer wherein the 16 Mbit DRAM chips mentioned above are fabricated.
  • a semicon ductor structure 10 essentially comprised of a silicon substrate 11 coated by a thin SiO2 layer 1 with the gate conductor stack comprised of the plurality of layers re cited above formed thereon.
  • the stack consists of a bottom 230 nm thick polysilicon layer 13, an intermediate 250 nm thick tungsten suicide layer 14 and a top 400 nm layer 15.
  • a photoresist layer 16 is formed on the stack to terminate the structure 10. All these layers, except however the photoresist layer, are formed by CVD (Chemical Vapor Deposition) techniques as standard.
  • the cap relatively thick SiO2 layer 15 is formed by low temperature PECVD (Plasma Enhanced Chemical Vapor Deposition) using Tetra Ethyl Ortho Silicate (TEOS) and oxygen for improved densification.
  • Refractory metals include titanium (Ti), molybdenum (Mo), zirconium (Zr), tungsten (W) and tantalum (Ta).
  • the photoresist layer 16 is applied by spin-on deposition technique on the wafer as standard. Once patterned, the photoresist layer 16 will be used as the etching mask for the gate conductor stack delineation.
  • the 16 Mbit DRAM chips manufactured uses APEX-M (a high speed version of APEX). This photosensitive material is a 5-mJ positive tone chemically amplified system that has demonstrated excellent image stability, possibly with the use of an overcoat.
  • the fabrication of the gate conductor lines is known to be one of the most critical processing steps of the manufacturing of such 16 Mbit DRAM chips, because of the different chemistries and etch rates that are required to selectively etch the different materials forming the stack without damaging the thin silicon oxide layer 12.
  • the fabrication of the gate conductor lines is performed in a multi-chamber reactive ion etching reactor and requires four reaction chambers to process the wafers as it will be made apparent hereafter.
  • a Magnetically Enhanced Reactive Ion Etching (MERIE) reactor such as model AME 5000 manufactured by Applied Materials, Santa Ciara, CA, USA is used for all these etching steps.
  • MERIE Magnetically Enhanced Reactive Ion Etching
  • the gate conductor stack delineation process starts with the patterning of the photoresist layer 16 to produce the etching mask illustrated in Fig. 1 B that is necessary for the subsequent etching steps.
  • the patterning process includes the standard resist expose, post-expose bake and develop steps.
  • the cap Si02 layer 15 must be etched.
  • the cap SiO2 layer is etched in a first chamber of the MERIE reactor using a CHF3 chemistry with additional 02 and Ar gases to avoid high polymerization of fluorocarbon compounds on the edges of the gate conductor lines in order to get vertical profiles.
  • the wafer that is placed on the cathode is cooled by a flow of helium at a determined pressure to reach the desired temperature.
  • the walls of the chamber and the cathode are heated as standard. Operating conditions read as follows:
  • Ar flow rate 100 seem time 180 sec gas pressure 18,7 Pa (140 mTorr) microwave power 850 W (at 13,56 MHz) backside cooling 800 Pa (6 Torr)
  • This etching step requires high energy to insure anisotropic etching of the TEOS material.
  • This first etching step is very critical because it is key to get the desired linewidth. Therefore, it is essential to have the adequate polymerization balancing which essentially depends of gas mixture ratio.
  • the resulting structure is shown in Fig. 1C.
  • the next step consists to transfer the pattern in the underlying tungsten suicide layer 15. Operating conditions now read as follows:
  • the carbon compounds of the resist layer 16 react with chlorine to produce a carbonated compound which is deposited forming sidewall buildups 17 on the patterns, as illustrated in Fig.lD.
  • these sidewall buildups 17 are very useful because they provide a passivation of the patterns preventing thereby the undesired etching of the WSi2 material during this step and the subsequent step of etching the polysilicon layer 13 that would otherwise produce undercuts.
  • this step is extremely dirty, because firstly layer 14 is not an homogeneous layer (the metal composition varies with the thickness) and secondly, due to the presence of the resist mask 16 which includes carbonated compounds.
  • the WSi2 layer 14 is the most complex layer to be etched.
  • this step is an important source of contamination and a major cause in the reactor lifetime reduction.
  • Etching the WSi2 layer 15 with a BCI3/CI2 chemistry generates different by-products such as WCI6 and SiCI4 which are volatile at high temperature forming deposits on the walls and the cathode of the cham ber that are heated.
  • BCI3 reveals to be efficient to anisotropically etch WSi2 but it has some negative effects such as degradation and undesired condensation effects in the feeding pipes.
  • the profile that is obtained is pretty vertical on the nested gate conductor lines, on the contrary, isolated gate conductor lines show slopes, and these effect is even more important at the edge of the wafer.
  • the present step is accomplished in a second chamber of the MERIE reactor.
  • Fig. 1E consists in a typical resist stripping sequence in a third chamber of the MERIE reactor using oxygen plasma, according to the following operating conditions:
  • this resist stripping step which employs an oxygen plasma, a superficial layer 18 of native SiOx oxide is created. Therefore, an additional processing step is required to remove the native oxide layer 18 as known for those skilled in the art.
  • This step which is usually referred to as the breakthrough step, is still accomplished by RIE etching in the same third chamber of the reactor according to the following operating conditions:
  • the semiconductor structure 10 is shown in Fig. 1E.
  • the polysilicon layer 13 is etched using an HCl, He-O2 and He mixture.
  • the operating conditions read as follows:
  • HCl is used because it generates less chlorine, so reducing WSi2 lateral etching.
  • the He-O2 gas mixture (ratio: 60/40) insures the desired high selectivity between the polysilicon material of layer 13 and the silicon oxide of layer 12. He is needed for diluting the oxygen in the He-O2 mixture to guarantee the optimum oxygen balancing.
  • Fig. 1F shows the semiconductor structure at the final stage of the process wherein the gate conductor line is referenced 19.
  • FIG. 2 schematically shows such a multi-chamber MERIE reactor referenced 20 wherein the chambers bear numerals 21 A to 21 D.
  • a central load/unload module 22 is disposed concentrically within the reactor 20 and a queuing station 23 is coupled to the load/unload module for transferring the wafers therein for processing and after processing from the reactor to the outside world.
  • Vacuum locks generally designated 24 are individually provided at the interface of the chambers and the load/unload module and between the interface of the latter and the queueing station.
  • the other parts of the reactor have not been shown for sake of simplicity.
  • the different travels the wafers are submitted to are clearly illustrated in Fig. 2.
  • Fig. 2 because four different plasma compositions are used in said four chambers, every time a plasma is extinct before a wafer is transferred from one chamber to another one, some by-products produced in this step are deposited onto the wafer. These by-products may be an important source of paniculate contamination because there is no cleaning step per formed in the central load/unload module 22.
  • the above described method has a number of drawbacks.
  • the WSi2 etching step is a very dirty step because the presence of the polymeric resist mask 16 which inherently is an important source of contamination.
  • the chamber dedicated to this step is cleaned every 45 hours.
  • the multiple plasma extinctions are also known to be another important source of contamination which significantly impacts the photo limited yield PLY (etch micromasking defects), which in turn, has a direct effect on the final wafer test yield.
  • PLY etch micromasking defects
  • the present invention aims to get rid of these drawbacks.
  • a method for dry (plasma) etching of an oxide/polycide structure in a preferred embodiment, a semiconductor structure consisting of a polycide layer sandwiched be tween a cap relatively thick SiO2 layer (other insulating materials such as Si3N4 may be used as well) and a thin oxide layer formed onto a silicon substrate is patterned in a two step plasma process with a resist stripping and cleaning step therebetween. The layer of thin oxide is attacked to a very small extent.
  • a typical process step sequence reads as follows.
  • the cap TEOS layer is etched as standard in a first chamber of a multi-chamber RIE reactor using a CHF3, 02 and Ar chemistry. Then, the semiconductor structure is removed from the reactor (declustering). The resist etching mask is stripped by 02 ashing in a specific tool and the wafer cleaned using DHF (100:1 ) to eliminate resist residues and particulates existing on the wafer surface. Next, the structure is introduced in a second chamber of the RIE reactor, and the metal suicide (e.g.
  • the tungsten suicide layer consists of a mixture of HCl, CI2 and N2 preferably with a few ppm of 02.
  • the said first chemistry consists of HCl, CI2 and air (80% 02/20% N2).
  • the second chemistry for etching the polysilicon layer consists of a mixture of HCl, He-O2 and He.
  • the improved method of the present invention is substantially contamination-free, in particular, no breakthrough step is required any long er.
  • the resist stripping is performed by ashing in 02 is now advantageously performed in a specific tool.
  • only two reaction chambers are now necessary to implement the said improved method instead of four with the prior art etching method.
  • the improved etching method of the present invention finds extensive application in the semiconductor industry and in particular, in the formation of the gate conductor lines in 16 Mbit DRAM chips.
  • Fig. 1A shows a semiconductor structure that includes five superposed layers forming a stack in which the gate conductor lines will be defined.
  • Figs. 1B to 1 F show the semiconductor structure of Fig. 1A at different stages of the fabrication of the gate conductor lines according to a standard process of the prior art.
  • Fig. 2 schematically shows the wafer transfers between the four chambers of the MERIE reactor when said standard process is employed.
  • Figs. 3A to 3C show the semiconductor structure of Fig. 1A at different stages of the fabrication of the gate conductor lines according to the method of the present invention
  • Fig. 4 schematically shows the wafer transfers between two chambers of the MERIE reactor when the method of the present invention is employed.
  • the semiconductor structure 10 of Fig. 1A is submitted to the same steps of patterning the resist layer 16 to produce an etching mask and then of etching the cap SiO2 layer 15. Likewise, this step of etching is performed in the first chamber 21 A of the MERIE reactor 20.
  • the initial semiconductor structure to be processed according to the method of the present invention is the structure 10 at the stage illustrated in Fig. 1C.
  • the novel improved method will be now described by reference to Figs. 3A to 3C, wherein Fig. 3A is structurally identical in all respects to Fig. 1 C and the same elements will be designated by the same references for sake of simplicity.
  • the semiconductor structure now referenced 10' is extracted from the reaction chamber 21 A to remove the resist layer 16 forming the etching mask.
  • This step is advantageously accomplished in a specific tool provided with a hot plate using ozone as standard.
  • An adequate equipment is model 200 AC II ASHER sold by FUSION SEMICONDUCTOR SYSTEMS.
  • Other advantages resulting of this processing step are more efficient stripping and higher throughput.
  • the semiconductor structure 10' is cleaned by any dry or wet cleaning technique.
  • the structure 10' is dipped in a diluted hydrofluoric acid bath (100:1) for 15 sec.
  • the resulting structure is shown in Fig. 3B.
  • This wet cleaning step during a short time has several benefits. As a matter of fact, organic and inorganic residues that result from resist ashing and from cross contamination are removed, thereby creating a cleaner surface of the WSi2 layer 14. As a consequence, the etch micromasking defects are lowered. These defects are known to be critical to the process because they may result in a number of potential failures after completion of the process, such as polysilicon shorts or extensions between two adjacent gate conductor lines.
  • the semiconductor structure 10' is introduced in an other reaction chamber, e.g. 21 B of the MERIE reactor 20.
  • the chamber is still heated, the temperatures of the cathode and of the walls are 17 ⁇ C and 45TC respectively.
  • the patterned cap Si02 layer 15 as an hard etching mask, the exposed portions of the tungsten silicide WSi2 layer 14 and of the polysilicon layer 13 are etched seriatim.
  • a mixture of HCl, CI2 and N2 is used for tungsten silicide etching according to the following parameters:
  • N2 flow rate 2 seem time 75 sec gas pressure 2,66 Pa (20 mTorr) microwave power : 450 W backside cooling : 8 Ton-
  • a HCl, He-O2 and He chemistry is used with the following operating conditions:
  • these two layers are etched in a single step, therefore without plasma extinction therebetween, significantly reducing thereby the paniculate contamination which normally results from the use of various chemistries in the different chambers of the MERIE reactor 20 and the fall of by-product particles which occurred with the prior art method at each plasma extinction when the wafer was transferred from one chamber to another one.
  • the use of the HCl based chemistries with the cap SiO2 hard mask permits an accurate control of the vertical profile, which results in reduced sidewall organic/inorganic deposition, less microloading effects at plasma extinction and reduced etch bias (by a factor of about 35%) between the two types of gate conductor lines (nested vs isolated).
  • FIG. 4 The new roadmap showing the movements of the wafer within the MERIE reactor 20 is illustrated in Fig. 4. As apparent from Fig. 4, only two reaction chambers, in this instance chambers 21 A and 21 B, are required.
  • the cap SiO2 layer is patterned in chamber 21 A and the polycide layer 13/14 is etched in chamber 21 B.
  • the two other chambers 21 C and 21 D may be used to process another lot of wafers.
  • the resist stripping and cleaning step is performed outside the MERIE reactor 20.
  • the method of the present invention can thus be clearly distinguished from the above described state of the art process. It is based on a new sequence of two etching steps, each being performed in a reaction chamber of the MERIE reactor, with a declustering therebetween for resist stripping and cleaning the wafer.
  • the resist stripping is performed in a specific tool and the standard breakthrough step is no longer required.
  • it uses the patterned cap SiO2 layer as a hard mask for the etching of both the tungsten silicide and polysilicon layers in the same chamber with adequate and compatible chemistries. As a result, the paniculate contamination is substantially eliminated.
  • the method of the present invention has some significant advantages when compared to the prior art method that will be now recited. It is a substantially contamination-free process, because first there is no plasma extinction be tween WSi2 and polysilicon etching, and second there is a cleaning step either before or after every plasma extinction. In addition, there is no longer any carbon polymer ization because the breakthrough step (which employs CF4) has been eliminated. Less contamination means 13 photo limit ed yield and final test yield improvements due to lower defect density. Gate conductor lines with a vertical profile are obtained irrespective their location, at the center or at the wafer edge, producing thereby a significant chip linewidth variation improvement for the whole wafer.
  • Resist stripping is performed in much better conditions because this step is now made in a specific tool. Only two reaction chambers are now required instead of four, offering thereby higher tool capacity by a factor of two with more flexibility and improved uptime.
  • the dry (plasma) etching method of the present invention finds extensive application in the semiconductor industry and in particular, in the formation of the gate conductor lines in 16 Mbit DRAM chips.

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  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne une structure de semi-conducteur (10') constituée d'une pile dans laquelle une couche supérieure d'oxyde SiO2 (15) est superposée sur une couche de siliciure de tungstène (14) reposant elle-même sur une couche inférieure de polysilicium (13); la pile en question est formé sur un substrat de silicium (11) revêtu d'une mince couche d'oxyde (12). On obtient les motifs de la structure selon un procédé d'attaque au plasma en deux étapes entre lesquelles s'intercalent une étape de décapage/nettoyage du résist. Après la mise en place d'un masque de résist (16) au sommet de la structure, on attaque la couche supérieure SiO2 selon la procédure classique dans la première chambre d'un réacteur à plusieurs chambres d'attaque au plasma d'ions réactifs à optimisation magnétique (MERIE) en utilisant les éléments suivants CHF3, O2 et Ar. Ensuite, la structure est extraite du réacteur. On élimine le masque de résist en utilisant un calcinateur O2 selon la procédure classique et on nettoie la plaquette en la plongeant dans un bain d'acide fluorhydrique dilué (100:1). Après quoi, la plaquette est introduite dans une deuxième chambre du réacteur de type RIE, ce qui permet d'attaquer successivement les couches de WSi2 et de polysilicium selon un procédé chimique adéquat en utilisant comme masque dur la couche de SiO2 formée. Un mélange de HCI, CI2 et N2, de préférence avec quelques ppm de O2, est indiqué pour l'attaque du siliciure de tungstène et, par ailleurs, un mélange de HCI, He et He-O2 se prête bien à l'attaque du polysilicium. Au cours de cette phase, la fine couche d'oxyde est attaquée dans des proportions très réduites. On peut alors extraire la plaquette de la chambre de réaction afin de poursuivre la traitement. Le procédé décrit dans l'invention est sensiblement exempt de toute contamination et nécessite seulement deux chambres de réaction, alors qu'il en faut quatre en ce qui concerne le processus d'attaque conventionel. Le potentiel d'application de ce procédé est important dans l'industrie des semi-conducteurs et, en particulier, dans la fabrication des piles de conducteurs de grille sur les microcircuits à mémoire RAM dynamique à 16 Mbit.
PCT/EP1996/000922 1995-03-08 1996-03-05 Procede d'attaque au plasma d'une structure en oxyde/silicium polycristallin siliciure WO1996027899A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8526605A JPH09509017A (ja) 1995-03-08 1996-03-05 酸化物／ポリサイド構造をプラズマ・エッチングするための方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP95480015.7 1995-03-08
EP95480015A EP0731501A1 (fr) 1995-03-08 1995-03-08 Procédé d'attaque par plasma d'une structure oxide/polycide
EP95480093.4 1995-07-13
EP95480093 1995-07-13

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WO1996027899A1 true WO1996027899A1 (fr) 1996-09-12

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Cited By (9)

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EP0855737A2 (fr) * 1996-12-24 1998-07-29 Mitel Corporation Procédé de gravure utilisant un masque dur
EP0856877A1 (fr) * 1997-01-31 1998-08-05 Texas Instruments Incorporated Procédé de formation de circuits intégrés utilisant une attaque par plasma comportant plusieurs étapes
EP0865074A2 (fr) * 1997-02-20 1998-09-16 Siemens Aktiengesellschaft Procédé de fabrication de couches et de structures en polysilicium et procédé de structuration de couches et de structures contenant du polysilicium
EP0932190A1 (fr) * 1997-12-30 1999-07-28 International Business Machines Corporation Procédé d'attaque par plasma d'une couche de siliciure de tungstène dans la fabrication de la grille conductrice multicouche
US6261934B1 (en) 1998-03-31 2001-07-17 Texas Instruments Incorporated Dry etch process for small-geometry metal gates over thin gate dielectric
EP1235265A1 (fr) * 2001-02-23 2002-08-28 Infineon Technologies AG Procédé de gravure d'un masque dur et d'une couche de métal
US6479373B2 (en) 1997-02-20 2002-11-12 Infineon Technologies Ag Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases
US7217652B1 (en) * 2000-09-21 2007-05-15 Spansion Llc Method of forming highly conductive semiconductor structures via plasma etch
CN104752152A (zh) * 2013-12-29 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 一种沟槽刻蚀方法及刻蚀装置

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KR100802307B1 (ko) * 2006-08-31 2008-02-11 동부일렉트로닉스 주식회사 금속막 식각 방법

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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0855737A3 (fr) * 1996-12-24 1998-12-23 Mitel Corporation Procédé de gravure utilisant un masque dur
EP0855737A2 (fr) * 1996-12-24 1998-07-29 Mitel Corporation Procédé de gravure utilisant un masque dur
US6074946A (en) * 1996-12-24 2000-06-13 Mitel Corporation Integrated processing for an etch module using a hard mask technique
EP0856877A1 (fr) * 1997-01-31 1998-08-05 Texas Instruments Incorporated Procédé de formation de circuits intégrés utilisant une attaque par plasma comportant plusieurs étapes
US6607985B1 (en) 1997-01-31 2003-08-19 Texas Instruments Incorporated Gate stack and etch process
US6479373B2 (en) 1997-02-20 2002-11-12 Infineon Technologies Ag Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases
EP0865074A2 (fr) * 1997-02-20 1998-09-16 Siemens Aktiengesellschaft Procédé de fabrication de couches et de structures en polysilicium et procédé de structuration de couches et de structures contenant du polysilicium
EP0865074A3 (fr) * 1997-02-20 2000-01-05 Siemens Aktiengesellschaft Procédé de fabrication de couches et de structures en polysilicium et procédé de structuration de couches et de structures contenant du polysilicium
US6693022B2 (en) 1997-02-20 2004-02-17 Infineon Technologies Ag CVD method of producing in situ-doped polysilicon layers and polysilicon layered structures
EP0932190A1 (fr) * 1997-12-30 1999-07-28 International Business Machines Corporation Procédé d'attaque par plasma d'une couche de siliciure de tungstène dans la fabrication de la grille conductrice multicouche
US6261934B1 (en) 1998-03-31 2001-07-17 Texas Instruments Incorporated Dry etch process for small-geometry metal gates over thin gate dielectric
US7217652B1 (en) * 2000-09-21 2007-05-15 Spansion Llc Method of forming highly conductive semiconductor structures via plasma etch
WO2002073682A1 (fr) * 2001-02-23 2002-09-19 Infineon Technologies Ag Procede de gravure d'une couche a masque dur et d'une couche metallique
EP1235265A1 (fr) * 2001-02-23 2002-08-28 Infineon Technologies AG Procédé de gravure d'un masque dur et d'une couche de métal
US6756314B2 (en) 2001-02-23 2004-06-29 Infineon Technologies Ag Method for etching a hard mask layer and a metal layer
CN104752152A (zh) * 2013-12-29 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 一种沟槽刻蚀方法及刻蚀装置

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