WO1996016439A1 - CONSTRUCTING CMOS VERTICALLY MODULATED WELLS BY CLUSTERED MeV BURIED IMPLANTED LAYER FOR LATERAL ISOLATION - Google Patents
CONSTRUCTING CMOS VERTICALLY MODULATED WELLS BY CLUSTERED MeV BURIED IMPLANTED LAYER FOR LATERAL ISOLATION Download PDFInfo
- Publication number
- WO1996016439A1 WO1996016439A1 PCT/US1995/014653 US9514653W WO9616439A1 WO 1996016439 A1 WO1996016439 A1 WO 1996016439A1 US 9514653 W US9514653 W US 9514653W WO 9616439 A1 WO9616439 A1 WO 9616439A1
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- Prior art keywords
- energy
- well
- mask
- sufficient
- retrograde
- Prior art date
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- 238000002955 isolation Methods 0.000 title claims abstract description 18
- 239000007943 implant Substances 0.000 claims description 102
- 150000002500 ions Chemical class 0.000 claims description 73
- 239000000758 substrate Substances 0.000 claims description 66
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- 238000000137 annealing Methods 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims 4
- 238000005468 ion implantation Methods 0.000 abstract description 2
- -1 and V Substances 0.000 description 54
- 229910052796 boron Inorganic materials 0.000 description 34
- 229910052698 phosphorus Inorganic materials 0.000 description 27
- 239000011574 phosphorus Substances 0.000 description 27
- 238000002513 implantation Methods 0.000 description 13
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- 230000003746 surface roughness Effects 0.000 description 1
- 108700043117 vasectrin I Proteins 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Definitions
- the present invention relates to simplification of a manufacturing process for complementary semiconductor devices, which are becoming increasingly miniaturized and increasingly complex, to a high component-density semiconductor device having enhanced resistance to CMOS latch-up, and to well formation (single, twin, triple) .
- CMOS technology in the VS I field has grown, as a result of requirements for a high noise margin and low power consumption.
- miniaturization has increased, serious problems have arisen with regard to preventing stray thyristor operation which causes the CMOS latch-up phenomenon to occur between mutually adjacent portions of an n- channel MOSFET and p-channel MOSFET, and with regard to maintaining a sufficient level of withstanding voltage between mutually adjacent elements.
- the present invention solves the following problems:
- novel features of the invention include the following: 1) clustered implants
- CMOS latch-up resistance and device scaling/shrink 2) Improved CMOS latch-up resistance and device scaling/shrink. a) reduction in lateral current gain/lateral beta (B L ) . b) reduction in vertical lcurrent gain/vertical beta (B v ) . c) reduction in well resistances (R w ) . d) reduction in substrate resistance (R s ) . e) improved n+ to p+ spacing.
- the retrograde n- well includes an upper layer 6 wherein phosphorus ions have been implanted so as to form phosphorus (n) impurity atoms with a density that is produced by 5E12cm-2] and a lower layer 7 wherein phosphorus ions have been implanted so as to form phosphorus (n) impurity atoms with a density that is produced by 3E13cm-2.
- a BILLI triple well structure may be formed by the clustered implantation indicated in Fig. 5, wherein the bottom ("buried") n-layer is formed prior to the clustered implant steps by a separate implantation of 3.0 MeV phosphorus ions at a current of 3 to 5 E13 through a separate mask, designated "M2" in Fig. 5. The remaining, clustered implantation steps are carried out through a separate mask, designated "M3" in Fig. 5, in the following sequence.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8516937A JPH10509281A (en) | 1994-11-22 | 1995-11-09 | Method of Constructing a CMOS Vertical Adjustment Well (VMW) by Implanting Clustered MEV BILLI |
EP95939891A EP0793858A4 (en) | 1994-11-22 | 1995-11-09 | CONSTRUCTING CMOS VERTICALLY MODULATED WELLS BY CLUSTERED MeV BURIED IMPLANTED LAYER FOR LATERAL ISOLATION |
KR1019970703421A KR100272394B1 (en) | 1994-11-22 | 1995-11-09 | Method of constructing cmos vertically modulatrd wells by clustered mev billi implantion |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/343,116 | 1994-11-22 | ||
US08/343,116 US5501993A (en) | 1994-11-22 | 1994-11-22 | Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996016439A1 true WO1996016439A1 (en) | 1996-05-30 |
Family
ID=23344782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1995/014653 WO1996016439A1 (en) | 1994-11-22 | 1995-11-09 | CONSTRUCTING CMOS VERTICALLY MODULATED WELLS BY CLUSTERED MeV BURIED IMPLANTED LAYER FOR LATERAL ISOLATION |
Country Status (5)
Country | Link |
---|---|
US (2) | US5501993A (en) |
EP (1) | EP0793858A4 (en) |
JP (1) | JPH10509281A (en) |
KR (1) | KR100272394B1 (en) |
WO (1) | WO1996016439A1 (en) |
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EP0794575A3 (en) * | 1987-10-08 | 1998-04-01 | Matsushita Electric Industrial Co., Ltd. | Structure and method of manufacture for CMOS semiconductor device against latch-up effect |
JPH02305468A (en) * | 1989-05-19 | 1990-12-19 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JP2965783B2 (en) * | 1991-07-17 | 1999-10-18 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP2978345B2 (en) * | 1992-11-26 | 1999-11-15 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
JP2682425B2 (en) * | 1993-12-24 | 1997-11-26 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1994
- 1994-11-22 US US08/343,116 patent/US5501993A/en not_active Expired - Fee Related
-
1995
- 1995-11-09 KR KR1019970703421A patent/KR100272394B1/en not_active IP Right Cessation
- 1995-11-09 JP JP8516937A patent/JPH10509281A/en active Pending
- 1995-11-09 WO PCT/US1995/014653 patent/WO1996016439A1/en not_active Application Discontinuation
- 1995-11-09 EP EP95939891A patent/EP0793858A4/en not_active Withdrawn
-
1996
- 1996-03-18 US US08/617,293 patent/US5814866A/en not_active Expired - Lifetime
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US4710477A (en) * | 1983-09-12 | 1987-12-01 | Hughes Aircraft Company | Method for forming latch-up immune, multiple retrograde well high density CMOS FET |
US5292671A (en) * | 1987-10-08 | 1994-03-08 | Matsushita Electric Industrial, Co., Ltd. | Method of manufacture for semiconductor device by forming deep and shallow regions |
US5384279A (en) * | 1988-09-09 | 1995-01-24 | U.S. Philips Corporation | Method of manufacturing a semiconductor device comprising a silicon body in which semiconductor regions are formed by ion implantations |
Non-Patent Citations (1)
Title |
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See also references of EP0793858A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPH10509281A (en) | 1998-09-08 |
KR980700687A (en) | 1998-03-30 |
US5814866A (en) | 1998-09-29 |
KR100272394B1 (en) | 2000-12-01 |
US5501993A (en) | 1996-03-26 |
EP0793858A4 (en) | 1998-08-19 |
EP0793858A1 (en) | 1997-09-10 |
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