KR100479814B1 - Well Forming Method of Semiconductor Device - Google Patents
Well Forming Method of Semiconductor Device Download PDFInfo
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- KR100479814B1 KR100479814B1 KR1019970010076A KR19970010076A KR100479814B1 KR 100479814 B1 KR100479814 B1 KR 100479814B1 KR 1019970010076 A KR1019970010076 A KR 1019970010076A KR 19970010076 A KR19970010076 A KR 19970010076A KR 100479814 B1 KR100479814 B1 KR 100479814B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
본 발명은 반도체소자의 웰 형성방법에 관한 것으로, 제1도전형의 반도체기판에 제2도전형의 베리드층 및 트윈-웰을 형성하는 반도체소자의 웰 형성방법에 있어서, 소자분리절연막이 형성된 반도체기판 상부에 감광막을 형성하고 상기 감광막에 불순물을 이온주입하여 밀도를 증가시킨 다음, 상기 반도체기판에 제1도전형의 제1웰을 형성하기 위한 마스크를 이용하여 감광막패턴을 형성하고 상기 반도체기판에 제2도전형의 제2웰 및 제2도전형의 제2베리드층을 형성한 다음, 상기 반도체기판에 제1도전형의 채널필드스토퍼 및 제2도전형의 제1베리드층을 형성하고 상기 감광막패턴을 마스크로 하는 이온주입공정으로 제1웰을 형성한 다음, 상기 감광막패턴을 제거하고 상기 반도체기판을 웰-어닐링하는 공정으로 트윈-웰을 형성하는 동시에 제2도전형 베리드층(buried layer)을 용이하게 형성하되, 제1도전형 웰과 그 하부의 제2도전형 베리드층이 일정간격 유지하도록 형성함으로써 접합누설전류를 감소시켜 반도체소자의 전기적 특성을 향상시키고, 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a well of a semiconductor device, and in a well forming method of a semiconductor device in which a buried layer and a twin-well of a second conductive type are formed on a semiconductor substrate of a first conductive type, a semiconductor having an element isolation insulating film formed thereon. After forming a photoresist film on the substrate and implanting impurities into the photoresist film to increase the density, a photoresist pattern is formed using a mask for forming a first well of a first conductivity type on the semiconductor substrate and then formed on the semiconductor substrate. After forming a second well layer of a second conductive type and a second buried layer of a second conductive type, a channel field stopper of a first conductive type and a first buried layer of a second conductive type are formed on the semiconductor substrate. A first well is formed by an ion implantation process using a pattern as a mask, followed by removing the photoresist pattern and well-annealing the semiconductor substrate. The lead layer may be easily formed, and the first conductive well and the second conductive buried layer below the same may be formed to maintain a predetermined interval, thereby reducing the junction leakage current, thereby improving the electrical characteristics of the semiconductor device. It is a technology that improves the characteristics and reliability of the device and thereby enables high integration of the semiconductor device.
Description
본 발명은 반도체소자의 웰 형성방법에 관한 것으로, 고에너지를 이용하여 프로파일드 웰 ( profiled well ) 을 형성하되, 공정을 단순화시키고, 엔웰 ( n-well ) 과 엔웰 하부에 형성되는 피-베리드층 ( p-buried layer ) 의 간격을 크게 하여 접합누설전류를 적게 하여 반도체소자의 특성 및 신뢰성을 향상시키는 동시에 반도체소자의 수율을 향상시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a well of a semiconductor device, and to form a profiled well using high energy, simplifying a process, and forming a p-bury layer formed under an n-well and an under well. The present invention relates to a method of improving the yield and yield of semiconductor devices by increasing the spacing of p-buried layers to reduce junction leakage current.
일반적으로, 집적회로는 보통의 플레이너 트랜지스터 ( planar transistor ) 와는 달리 반도체기판을 제외한 모든 전극을 펠렛 ( pellet ) 의 윗면으로 끌어내지 않으면 안된다.In general, integrated circuits, unlike ordinary planar transistors, must draw all electrodes except the semiconductor substrate to the top of the pellets.
이로 인하여, 소자의 직렬저항이 상승하는 단점이 있다. 그리고, 이를 해결하기 위하여, 트랜지스터나 다이오드와 같이 직렬저항이 문제가 되는 소자에서는 트랜지스터 또는 다이오드의 아래쪽 부분에 저저항의 층을 매입하여 매립층, 즉 베리드층 ( buried layer ) 을 형성한다.For this reason, there is a disadvantage that the series resistance of the device rises. In order to solve this problem, in a device having a series resistance problem such as a transistor or a diode, a low resistance layer is embedded in a lower portion of the transistor or diode to form a buried layer, that is, a buried layer.
여기서, 상기 베리드층은 피형 반도체기판에서 트랜지스터가 일으키는 PNPN스위칭 동작을 방지하는 역할을 한다.Here, the buried layer serves to prevent the PNPN switching operation caused by the transistor in the semiconductor substrate.
참고로, 반도체소자는 소자의 특성을 향상시키기 위하여, 엔형(n-type) 또는 피형(p-type)의 반도체기판에 피형 또는 엔형의 불순물을 주입하여 피웰 또는 엔웰을 형성하고, 상기 웰의 내부에 엔-모스(n-MOS) 또는 피-모스(p-MOS)를 형성하였다. 그리고, 상기 모스의 형성공정 전에 반도체기판과 웰의 중간에 베리드층을 형성하여 소자의 특성을 향상시켰다.For reference, in order to improve the characteristics of a device, a semiconductor device may form a pewell or enwell by injecting impurities of a type or en type into an n-type or p-type semiconductor substrate and forming a pwell or an enwell, and the inside of the well. N-MOS or p-MOS was formed in the substrate. In addition, the buried layer was formed between the semiconductor substrate and the well before the forming process of the MOS to improve the characteristics of the device.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 웰 형성방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a well forming method of a semiconductor device according to the prior art.
먼저, 반도체기판(41)에 소자분리절연막(43)을 형성한다. 그리고, 상기 소자분리절연막(43)의 일측에 감광막패턴(45)을 형성한다. 이때, 상기 감광막패턴(45)은 엔웰(49)을 형성하기 위한 것이다.First, a device isolation insulating film 43 is formed on the semiconductor substrate 41. A photosensitive film pattern 45 is formed on one side of the device isolation insulating film 43. In this case, the photoresist pattern 45 is for forming the enwell 49.
그리고, 더 큰 에너지로 피형 불순물을 주입하여 상기 일측, 즉 감광막패턴(45)의 하부에 피웰(55)을 형성하는 동시에 상기 타측, 즉 상기 제1베리드층(53) 하부에 제2베리드층(57)을 형성한다.In addition, by implanting the impurity with the larger energy to form the pewell 55 on the one side, that is, the lower portion of the photosensitive film pattern 45, the second buried layer (under the other side, that is, the first buried layer 53) 57).
연속적으로, 상기 반도체기판(41)에 엔-채널필드스토퍼 ( n-channel field stopper ) 을 형성하기 위하여 붕소와 같은 피형 불순물을 주입한다. 이로 인하여, 상기 감광막패턴(45)의 하부에는 엔-채널필드스토퍼(51)가 형성되며, 상기 소자분리절연막(43)의 타측은 제1베리드층(53)이 형성된다.Subsequently, an implanted impurity such as boron is implanted into the semiconductor substrate 41 to form an n-channel field stopper. Thus, an N-channel field stopper 51 is formed below the photoresist pattern 45, and a first buried layer 53 is formed on the other side of the device isolation insulating layer 43.
그 다음에, 상기 감광막패턴(45)을 마스크로 하여 상기 반도체기판(41)에 엔형 불순물(47)을 주입하여 엔웰(49)을 형성한다. (도 1a)Subsequently, an enwell 49 is formed by injecting en-type impurities 47 into the semiconductor substrate 41 using the photoresist pattern 45 as a mask. (FIG. 1A)
그 다음에, 상기 감광막패턴(45)을 제거하고, 드라이브인 ( drive-in ) 공정을 실시하여 완전한 피웰(59)과 인웰(49) 및 피-베리드층(61)을 형성한다.Next, the photoresist pattern 45 is removed and a drive-in process is performed to form a complete pewell 59, an inwell 49, and a p-bury layer 61.
그리고, 후속공정으로 상기 엔웰(49)과 피웰(55)의 상부에 각각 피-모스(65)와 엔-모스(63)를 형성한다. (도 1b)Subsequently, the P-MOS 65 and the N-MOS 63 are formed on the N-well 49 and the P-well 55 in the subsequent process. (FIG. 1B)
여기서, 종래기술은 상기 베리드층(61)이 상기 엔웰(49)의 농도와 같거나 그 이하이므로 반도체기판 내부에 함유된 불순물 및 결함의 게더링( gettering ) 효과를 기대할 수 없다. 그리고, 상기 베리드층(61)과 엔웰(49)의 간격이 적절하지 않으면 접합누설전류의 증가요인이 된다.In the related art, since the buried layer 61 is equal to or less than the concentration of the enwell 49, the gettering effect of impurities and defects contained in the semiconductor substrate cannot be expected. If the gap between the buried layer 61 and the enwell 49 is not appropriate, the leakage leakage current may increase.
상기한 바와 같이 종래기술에 따른 반도체소자의 웰 형성방법은, 웰의 불순물 농도이하로 베리드층의 불순물이 형성되어 반도체기판 내의 불순물 및 결함의 게더링을 기대할 수 없으며, 상기 웰과 베리드층의 간격이 좁아 접합누설진류를 증가시킬 수 있으므로 반도체소자의 특성 및 신뢰성을 저하시키고 반도체소자의 생산수율을 저하시키며 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the well forming method of the semiconductor device according to the related art, impurities in the buried layer may be formed below the impurity concentration of the wells, so that no gathering of impurities and defects in the semiconductor substrate may be expected. Since it is possible to increase the junction leakage current to narrow, there is a problem in that the characteristics and reliability of the semiconductor device is lowered, the production yield of the semiconductor device is lowered, thereby making it difficult to integrate the semiconductor device.
따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 큰 이온주입에너지를 이용하여 웰과 큰 간격을 갖는 베리드층을 형성함으로써 반도체소자의 접합누설전류를 감소시켜 전기적 특성을 향상시키는 동시에 공정을 단순화시켜 반도체소자의 특성, 수율 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 웰 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art, by forming a buried layer having a large gap with the well by using a large ion implantation energy to reduce the junction leakage current of the semiconductor device to improve the electrical characteristics and at the same time process The purpose of the present invention is to provide a method for forming a well of a semiconductor device by simplifying the semiconductor device, thereby improving characteristics, yield, and reliability of the semiconductor device, thereby enabling high integration of the semiconductor device.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 웰 형성방법은,In order to achieve the above object, the well-forming method of a semiconductor device according to the present invention,
제1도전형의 반도체기판에 제2도전형의 베리드층 및 트윈-웰을 형성하는 반도체소자의 웰 형성방법에 있어서,In the well-forming method of a semiconductor device to form a buried layer and a twin-well of the second conductive type on a semiconductor substrate of the first conductive type,
소자분리절연막이 형성된 반도체기판 상부에 감광막을 형성하는 공정과,Forming a photosensitive film on the semiconductor substrate on which the device isolation insulating film is formed;
상기 감광막에 불순물을 이온주입하여 밀도를 증가시키는 공정과,Increasing the density by ion implanting impurities into the photosensitive film;
상기 반도체기판에 제1도전형의 제1웰을 형성하기 위한 마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the semiconductor substrate using a mask for forming a first well of a first conductivity type;
상기 반도체기판에 제2도전형의 제2웰 및 제2도전형의 제2베리드층을 형성하는 공정과,Forming a second well of a second conductive type and a second buried layer of a second conductive type on the semiconductor substrate;
상기 반도체기판에 제1도전형 채널의 필드스토퍼 및 제2도전형의 제1베리드층을 형성하는 공정과,Forming a field stopper of a first conductive channel and a first buried layer of a second conductive type on the semiconductor substrate;
상기 감광막패턴을 마스크로 하는 이온주입공정으로 제1웰을 형성하는 공정과,Forming a first well by an ion implantation process using the photosensitive film pattern as a mask;
상기 감광막패턴을 제거하는 공정과,Removing the photoresist pattern;
상기 반도체기판을 웰-어닐링하는 공정을 포함하는 것을 특징으로 한다.And well-annealing the semiconductor substrate.
한편, 상기한 목적을 달성하기위한 본 발명의 원리는, 종래기술과 같이 소자분리공정후 웰을 형성하기 위한 감광막패턴을 형성하고, 상기 감광막패턴에 불순물을 주입하여 상기 감광막패턴의 불순물 밀도를 증가시킨 다음, 고에너지로 베리드층을 형성하여 웰과의 간격이 큰 베리드층을 형성함으로써 접합누설전류를 감소시켜 반도체소자의 전기적 특성을 향상시키고 그로 인한 반도체소자의 생산수율을 향상시키는 것이다.On the other hand, the principle of the present invention for achieving the above object, as in the prior art, to form a photoresist pattern for forming a well after the device isolation process, and implanting impurities into the photoresist pattern to increase the impurity density of the photoresist pattern Then, by forming a buried layer with a high energy to form a buried layer having a large distance from the well, to reduce the junction leakage current to improve the electrical characteristics of the semiconductor device, thereby improving the production yield of the semiconductor device.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 웰 형성방법을 도시한 단면도로서, 엔형 반도체기판에 엔형과 피형의 트윈-웰과 피-베리드층을 형성하는 것을 도시한다.2A to 2C are cross-sectional views illustrating a method of forming a well of a semiconductor device according to an exemplary embodiment of the present invention, which illustrates forming a N-type and a shaped twin-well and a p-bury layer on an N-type semiconductor substrate.
먼저, 반도체기판(11)에 소자분리절연막(13)을 형성한다. 그리고 상기 반도체기판(11)의 전체표면상부에 감광막(15)을 형성한다. 이때, 상기 감광막(15)은 1 ∼ 4㎛ 정도의 두께로 형성한다.First, a device isolation insulating film 13 is formed on the semiconductor substrate 11. Then, the photosensitive film 15 is formed on the entire surface of the semiconductor substrate 11. At this time, the photosensitive film 15 is formed to a thickness of about 1 ~ 4㎛.
그리고, 상기 감광막(15)에 아르곤(Ar), 실리콘(Si), 게르마늄(Ge) 등과 같은 Ⅷ 족 및 Ⅳ 족 불순물(17)을 이온주입하여 상기 감광막(15)의 밀도를 증가시킨다.In addition, the photosensitive layer 15 is ion-implanted with Group VIII and Group IV impurities 17 such as argon (Ar), silicon (Si), germanium (Ge), and the like to increase the density of the photosensitive layer 15.
이때, 상기 이온주입공정은, 1×1013 ∼ 1×1016 이온/㎠ 정도의 불순물 주입농도를 100 keV ∼ 2 MeV 크기의 에너지로 실시한다.At this time, the ion implantation step, the impurity implantation concentration of about 1 × 10 13 to 1 × 10 16 ions / cm 2 is performed with energy having a size of 100 keV to 2 MeV.
특히, 상기 이온주입공정은 3단계로 실시하되, 각각의 이온주입에너지를 1 ∼ 2 MeV, 300 keV ∼ 1 MeV 및 100 ∼ 300 keV 로 하여 실시하며, 이때의 불순물 주입농도는 동일하게 한다.In particular, the ion implantation process is carried out in three stages, each ion implantation energy is carried out to 1 ~ 2 MeV, 300 keV ~ 1 MeV and 100 ~ 300 keV, the impurity implantation concentration is the same.
그리고, 상기 감광막(15)은 상기 이온주입방법으로 1 ∼ 10 g/㎤ 정도의 밀도를 갖도록 한다.In addition, the photosensitive film 15 has a density of about 1 to 10 g / cm 3 by the ion implantation method.
또한, 상기 도 2a 의 공정으로 인하여 상기 고에너지의 이온주입공정시 종래보다 얕게 불순물 이온주입층이 형성된다. (도 2a)In addition, the impurity ion implantation layer is formed shallower than the prior art during the high energy ion implantation process due to the process of FIG. 2A. (FIG. 2A)
그 다음, 엔웰을 노출시키는 감광막(15)패턴을 형성한다.Next, a photosensitive film 15 pattern exposing the enwell is formed.
그리고, 1.5 ∼ 3 MeV 의 이온에너지로 피형 불순물을 이온주입하여 상기 감광막(15)패턴을 통과시킴으로써 상기 감광막(15)패턴의 하측에 피웰(25)을 형성하고 상기 감광막(15)이 없는 부분의 반도체기판에 제2베리드층(27)을 형성한다.Then, ion implantation of the dopant impurity with ion energy of 1.5 to 3 MeV passes through the photosensitive film 15 pattern to form a pwell 25 under the photosensitive film 15 pattern, and the portion of the portion where the photosensitive film 15 is absent. The second buried layer 27 is formed on the semiconductor substrate.
그 다음, 상기 반도체기판(11)에 800 keV ∼ 2.5 MeV 의 에너지로 피형 불순물을 이온주입하여 상기 감광막(15)패턴의 하부 및 소자분리절연막(13)의 하부에 엔-채널필드스토퍼(21)를 형성하고, 상기 제2베리드층(27) 상측에 제1베리드층(23)을 형성하여 상기 제2베리드층(27)을 더 깊게 형성하도록 한다.Subsequently, ion implanted impurities are implanted into the semiconductor substrate 11 at an energy of 800 keV to 2.5 MeV to form the N-channel field stopper 21 under the photosensitive film 15 pattern and under the device isolation insulating film 13. And a first buried layer 23 formed on the second buried layer 27 to deepen the second buried layer 27.
그 후에, 상기 감광막(15)을 마스크로 하여 상기 반도체기판(11)에 엔형 불순물(19)을 이온주입하여 엔웰(20)을 형성한다. (도 2b)Subsequently, the enwell 20 is formed by ion-implanting en-type impurities 19 into the semiconductor substrate 11 using the photosensitive film 15 as a mask. (FIG. 2B)
그리고, 상기 감광막(15)패턴을 제거하고, 웰-어닐링 공정을 실시하여 완전한 엔웰(20)과 피웰(29)을 형성하는 동시에 상기 엔웰(20)의 하부에 상기 엔웰(20)과 큰간격을 갖는 피-베리드층(31)을 형성한다.In addition, the photoresist layer 15 is removed, and a well-annealing process is performed to form a complete enwell 20 and a pewell 29, and a large distance from the enwell 20 to a lower portion of the enwell 20. The to-be buried layer 31 having is formed.
그 다음, 후속공정으로 상기 엔웰(20)과 피웰(29) 상부에 각각 피-모스(35)와 엔-모스(33)를 형성한다. (도 2c)Subsequently, the P-MOS 35 and the N-MOS 33 are formed on the N-well 20 and the P-well 29, respectively, in a subsequent process. (FIG. 2C)
여기서, 본 발명의 다른 실시예는 피형 반도체기판에 실시하는 것이다. 그리고, 피형 반도체기판을 사용하는 경우는 엔-베리드층을 형성할 수 있다.Here, another embodiment of the present invention is carried out on a to-be-shaped semiconductor substrate. In the case of using a semiconductor substrate, an n-bury layer can be formed.
도 3 은 반도체소자의 웰 제조공정시 발생되는 접합누설전류를 모식적으로 도시한 그래프도로서, 전압에 따른 P+/N 의 접합누설전류를 종래기술과 비교하여 도시한 것이다.FIG. 3 is a graph schematically illustrating a junction leakage current generated during a well fabrication process of a semiconductor device, and illustrates a junction leakage current of P + / N according to a voltage in comparison with the prior art.
여기서, ⓐ 는 종래기술에 따른 접합누설전류를 도시하며, ⓑ 는 본 발명에 따른 접합누설전류를 도시한다.Here, ⓐ shows the junction leakage current according to the prior art, ⓑ shows the junction leakage current according to the present invention.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 웰 형성방법은, 엔/피웰을 형성하기 위한 감광막패턴을 형성하고, 상기 감광막패턴에 불순물을 이온주입하여 상기 감광막패턴의 밀도를 증가시킨 다음, 상기 감광막패턴을 이온주입장벽으로 하여 상기 반도체기판에 피/엔웰 및 엔/피-채널필드스토퍼를 형성할 수 있는 이온주입에너지로 이온주입공정을 실시함으로써 피/엔-베리드층을 형성하고 엔/피-채널필드스토퍼 및 피/엔웰을 형성한 다음, 후속공정으로 상기 감광막패턴을 마스크로 하여 엔/피웰을 형성함으로써 트윈-웰을 용이하게 형성하는 동시에 상기 엔/피웰과 큰 간격을 갖는 피/엔-베리드층을 형성하여 소자의 전기적 특성을 향상시킴으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, in the method of forming a well of a semiconductor device according to the present invention, a photoresist pattern for forming an N / Pwell is formed, and an ion is implanted into the photoresist pattern to increase the density of the photoresist pattern. An ion implantation process is performed using an ion implantation energy capable of forming a P / enwell and an N / P-channel field stopper on the semiconductor substrate using the photoresist pattern as an ion implantation barrier to form a p / en-bury layer and a N / P layer. After forming the channel field stopper and the P / en well, the N / P well is formed by using the photoresist pattern as a mask in a subsequent process, thereby easily forming a twin-well and having a large gap with the N / P well. By forming the buried layer to improve the electrical characteristics of the device, it is possible to improve the characteristics and reliability of the semiconductor device and thereby to achieve high integration of the semiconductor device. There are advantages to.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 웰 형성방법을 도시한 단면도.1A and 1B are cross-sectional views showing a well forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 웰 형성방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a well forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 3 은 종래기술과 본 발명을 비교하여 도시한 것으로, 전압인가에 따른 접합누설전류를 도시한 그래프도.FIG. 3 is a graph illustrating a junction leakage current according to application of voltage by comparing the prior art with the present invention. FIG.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,41 : 반도체기판 13,43 : 소자분리절연막11,41 semiconductor substrate 13,43 device isolation insulating film
15 : 감광막 17 : Ⅷ 족 및 Ⅳ 족 불순물15 photosensitive film 17: Group VIII and Group IV impurities
19,47 : 엔형 불순물 20,49 : 엔웰19,47 En-type impurities 20,49 En-well
21,51 : 엔-채널필드스토퍼 23,53 : 제1베리드층21,51: N-channel field stopper 23,53: first buried layer
25,55 : 피웰 27,57 : 제2베리드층25,55: Pwell 27,57: second buried layer
29,59 : 완전한 피웰 31,61 : 피-베리드층29,59: complete pewell 31,61: blood-bury layer
33,63 : 엔-모스 ( n-MOS ) 35,65 : 피-모스 ( p-MOS )33,63: n-MOS 35,65: p-MOS
ⓐ : 종래기술에 따른 접합누설전류 분포Ⓐ: junction leakage current distribution according to the prior art
ⓑ : 본 발명에 따른 접합누설전류 분포Ⓑ: junction leakage current distribution according to the present invention
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| JPH0283966A (en) * | 1988-09-09 | 1990-03-26 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH06163844A (en) * | 1992-11-26 | 1994-06-10 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5432114A (en) * | 1994-10-24 | 1995-07-11 | Analog Devices, Inc. | Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit |
| US5501993A (en) * | 1994-11-22 | 1996-03-26 | Genus, Inc. | Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation |
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| JPH0283966A (en) * | 1988-09-09 | 1990-03-26 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH06163844A (en) * | 1992-11-26 | 1994-06-10 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5432114A (en) * | 1994-10-24 | 1995-07-11 | Analog Devices, Inc. | Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit |
| US5501993A (en) * | 1994-11-22 | 1996-03-26 | Genus, Inc. | Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation |
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