GB2365625B - Method for forming a triple well of a semiconductor device - Google Patents

Method for forming a triple well of a semiconductor device

Info

Publication number
GB2365625B
GB2365625B GB0126594A GB0126594A GB2365625B GB 2365625 B GB2365625 B GB 2365625B GB 0126594 A GB0126594 A GB 0126594A GB 0126594 A GB0126594 A GB 0126594A GB 2365625 B GB2365625 B GB 2365625B
Authority
GB
United Kingdom
Prior art keywords
forming
semiconductor device
triple well
triple
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0126594A
Other versions
GB0126594D0 (en
GB2365625A (en
Inventor
Kwang Myoung Rho
Chan Kwang Park
Yo Hwan Koh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019960076307A external-priority patent/KR100228331B1/en
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB0126594D0 publication Critical patent/GB0126594D0/en
Publication of GB2365625A publication Critical patent/GB2365625A/en
Application granted granted Critical
Publication of GB2365625B publication Critical patent/GB2365625B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
GB0126594A 1996-12-30 1997-12-24 Method for forming a triple well of a semiconductor device Expired - Fee Related GB2365625B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019960076307A KR100228331B1 (en) 1996-12-30 1996-12-30 Method for manufacturing triple well of semiconductor device
GB9727402A GB2320812B (en) 1996-12-30 1997-12-24 Method for forming a triple well of a semiconductor device

Publications (3)

Publication Number Publication Date
GB0126594D0 GB0126594D0 (en) 2002-01-02
GB2365625A GB2365625A (en) 2002-02-20
GB2365625B true GB2365625B (en) 2002-05-15

Family

ID=26312857

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0126594A Expired - Fee Related GB2365625B (en) 1996-12-30 1997-12-24 Method for forming a triple well of a semiconductor device

Country Status (1)

Country Link
GB (1) GB2365625B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5501993A (en) * 1994-11-22 1996-03-26 Genus, Inc. Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5501993A (en) * 1994-11-22 1996-03-26 Genus, Inc. Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation

Also Published As

Publication number Publication date
GB0126594D0 (en) 2002-01-02
GB2365625A (en) 2002-02-20

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20131224