WO1996015584A1 - Synthetiseur numerique ameliore - Google Patents

Synthetiseur numerique ameliore Download PDF

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Publication number
WO1996015584A1
WO1996015584A1 PCT/US1995/014953 US9514953W WO9615584A1 WO 1996015584 A1 WO1996015584 A1 WO 1996015584A1 US 9514953 W US9514953 W US 9514953W WO 9615584 A1 WO9615584 A1 WO 9615584A1
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WO
WIPO (PCT)
Prior art keywords
value
signal
phase angle
quarterwave
output
Prior art date
Application number
PCT/US1995/014953
Other languages
English (en)
Inventor
Perry Cook
Masao Shindo
Original Assignee
Media Vision, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Media Vision, Inc. filed Critical Media Vision, Inc.
Priority to AU41637/96A priority Critical patent/AU4163796A/en
Publication of WO1996015584A1 publication Critical patent/WO1996015584A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B21/00—Generation of oscillations by combining unmodulated signals of different frequencies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator
    • G06F1/0335—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator the phase increment itself being a composed function of two or more variables, e.g. frequency and phase
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C1/00—Amplitude modulation

Definitions

  • the present invention relates generally to frequency modulated signal synthesizer circuits as utilized in music synthesizers, and more particularly to an FM synthesizer circuit having self-modulation and output waveform shape selection features.
  • the present invention is an improved apparatus for digitally synthesizing a musical sound. It utilizes a phase angle generator component, a quarterwave sine logic component, a wave constructor component, and a modulation logic component .
  • the phase angle generator component is operatively connected to the quarterwave sine logic component, such that a phase angle signal value from the phase angle generator component is fed to the quarterwave sine logic component.
  • the quarterwave sine logic component receives the phase angle signal value and outputs a first quadrant sine signal value.
  • the wave constructor component is operatively connected to the quarterwave sine logic component to receive a successive plurality of first quadrant sine signal values. It constructs a pre-selected output waveform signal value from the plurality of first quadrant sine signal values.
  • the modulation logic component is operatively connected to the wave generator component and to the angle generator component.
  • the modulation logic component receives successive ones of the output waveform signal values and creates a self- modulation signal value. It then outputs the self- modulation signal value to the angle generator component for usage in creating a further phase angle signal value.
  • the circuit components are multiplexed to provide repeated signal generation steps to ultimately create an output signal. It is an advantage of the present invention that it provides an improved digital FM synthesizer circuit having rich and complex output signals to better emulate true musical instruments. It is another advantage of the present invention that it provides a digital FM synthesizer circuit having improved self-modulation signal features.
  • Fig. 1 is a schematic diagram of the FM synthesizer of the present invention
  • Fig. 2 is a detailed schematic diagram of the components comprising the FM signal generator circuit of the present invention
  • Fig. 1 is a schematic diagram of the FM synthesizer of the present invention
  • Fig. 2 is a detailed schematic diagram of the components comprising the FM signal generator circuit of the present invention
  • Fig. 1 is a schematic diagram of the FM synthesizer of the present invention
  • Fig. 2 is a detailed schematic diagram of the components comprising the FM signal generator circuit of the present invention
  • Fig. 1 is a schematic diagram of the FM synthesizer of the present invention
  • Fig. 2 is a detailed schematic diagram of the components comprising the FM signal generator circuit of the present invention
  • Fig. 1 is a schematic diagram of the FM synthesizer of the present invention
  • Fig. 2 is a detailed schematic diagram of the components comprising the FM signal generator circuit of the present invention
  • Fig. 1 is a schematic diagram of the FM synthe
  • FIG. 3 depicts the various output waveform shapes that are selectable by the program control logic of the present invention
  • Fig. 4 depicts the angle wave select logic of Fig. 2 of the present invention
  • Fig. 5 depicts the multiplexer 78 of Fig. 2 of the present invention
  • Fig. 6 depicts the combinatorial logic portion of the wave constructor of Fig. 2 of the present invention
  • Fig. 7 depicts the wave multiplexer logic of the wave constructor of Fig. 2 of the present invention
  • Fig. 8 is a schematic diagram depicting a time multiplexed series circuit utilizing the FM signal generator circuit of the present invention
  • Fig. 9 is a schematic diagram depicting a time multiplexed parallel circuit utilizing the FM signal generator circuit of the present invention.
  • FIG. 1 is a block diagram of the basic organization of a digital synthesizer 10 including a host interface 12, a register table 14, a Frequency Modulation (FM) synthesizer engine 16, and an output accumulator 18.
  • the output accumulator 18 accumulates the successive signals from the virtual FM signal generators that comprise the FM synthesizer engine 16 and sends an output signal to a digital to analog converter 22.
  • the digital to analog converter 22 converts the signal from the accumulator 18 to its analog form and directs it to a speaker system 24 (which may include a stereo amplifier system) for final output.
  • speaker system 24 which may include a stereo amplifier system
  • the host interface 12 is a bi-directional data bus that provides a means of transferring address and data information between a host computer system 20 and the synthesizer 10.
  • the data and address information received from the host system 20 via the host interface 12 is stored in the register table 14.
  • the host interface 12 also includes a set of control signals that regulates both access and data transfer activities between the host system 20 and the synthesizer's register table 14.
  • the FM synthesizer engine 16 Based on the values from the register table 14, the FM synthesizer engine 16 generates complex signals having the amplitudes, frequencies, and other parameters required to produce a desired audio output signal.
  • the functional components of the virtual FM signal generator include an angle generator 28, a sine logic device 30, an envelope generator 32, a wave constructor 34, and modulation logic 38.
  • the angle generator 28 receives the initial parameter values that specify the initial frequency and sound characteristics of a desired sound signal from the register table 14. In specific situations and at specific times (discussed hereinafter) the angle generator also receives an input signal from the modulation logic 38. The angle generator 28 then determines a phase angle value p(t) and supplies it as the input signal to the sine device 30.
  • the sine logic device 30 is a quarterwave sine logic device that calculates output values as though the phase angle input p(t) were in the first quadrant (0-90°) . For values of p(t) that are greater than 90° the sine logic device 30 is provided with a signal Q from the angle generator 28 indicating the quadrant of the value of the input angle p(t) .
  • the quadrant indicating signal Q is also output to the wave constructor 34 for use therein in the construction of the output signal o(t) .
  • the envelope generator 32 receives appropriate parameter values from the register table 14 fcr attack, decay or release rates, and calculatT ' ..• a*:rropriate amplitude or envelope parameter e *- ⁇ -.* . -larithmic value for the desired waveform. L ⁇ .-r»- -:--_ -.. ⁇ ted, the envelope parameter e(t) is forwarded tc the wave constructor 34.
  • the wave constructor 34 performs a number of functions, the first of which is to combine the logarithmic envelope parameter with the logarithmic sinusoidal output value y(t) received from the sine logic device 30.
  • a detailed description of the functions of the angle generator 28, sine logic 30 and wave constructor 34 is provided herebelow with the aid of Fig . 2 .
  • the components and complexity of o(t) 2 can be changed by merely altering either the frequency or amplitude components of o(t)j.
  • the angle generator 28 includes a basic phase logic 50, an adder 52, an accumulator register 54, rhythm phase logic 56 and a second adder 58.
  • the angle generator 28 receives the basic parameters from the register table 14, to calculate a base phase angle increment ⁇ p(t) , and it forwards this parameter ⁇ p(t) to adder 52.
  • the output of the adder 52 is then fed to an accumulator register 54 which operates in a FIFO manner.
  • the signal from the accumulator register 54 is then fed to the rhythm phase logic 56 which modifies the input phase angle data to output a phase angle signal with a rhythmic component.
  • the output phase angle signal from the rhythm phase logic 56 is fed to the adder 58 wherein it is combined at specific time increments with a signal 62 from the modulation logic 38 representative of output data from a prior output signal (in a time multiplexed manner) of the virtual signal generator.
  • the output of the adder 58 then becomes the actual phase angle input signal p(t) to the sine logic device 30.
  • the adder 58 also determines the quadrant (Q or QUAD [1:0]) of the phase angle p(t) and supplies that value Q to the sine logic 30 and the wave constructor 34.
  • the quadrant identifying signal Q is determined utilizing the two most significant bits of the added signal within the adder 58.
  • the value of the phase angle p(t) is determined as the eight least significant bits of the signal from the adder 58.
  • the digital synthesizer 10 includes an output waveform shape selection signal WS, whereby the desired waveform shape of the output signal o(t) may be selected. As depicted in Fig.
  • different waveform shapes are utilized for example when the digital synthesizer 10 emulates a drum sound and when it emulates a violin.
  • the angle wave select logic 70 utilizes the input signals WS, Q and p(t) to determine a final phase angle value (fp(t) or FINALPHASE [7 :0] ) that is output to the combinatorial logic one-quarter sine wave element 74 and to a multiplexer 78.
  • the logic construct that is utilized within the angle wave select logic 70 is set forth in the following table which is keyed to the angle wave select logic 70 depicted in Fig. 4.
  • the input signals to the multiplexer 78 are Q and fp(t) on one input line, s(t) on a second input line and WS on a third input line.
  • the signal (y(t) or P[11:0]) that is output from the multiplexer 78 is controlled by the value of WS according to the logic construct set forth in the following table which is keyed to the multiplexer 78 depicted in Fig. 5.
  • the output signal P[11:0] from the sine logic 30 is then fed to an input register 80 of the wave constructor 34.
  • a second register 82 within the wave constructor 34 holds an envelope determining signal value (e(t) or Amplitude A[8:0] ) from the envelope generator 32.
  • the signal values from registers 80 and 82 are combined in an adder 84. Because the signals from registers and 80 and 82 are logarithmic values, the addition of the signals in adder 84 is equivalent to a multiplication of the two signal values.
  • the signal output (CO,AD[8:0]) from adder 84 is fed to a combinatorial logic device 88.
  • the two least significant bits (A[2:0]) of the output signal from register 80 is also input directly to the combinatorial logic device 88.
  • the Logic Table III below sets forth the signal processing logic of the combinatorial logic device 88 as shown in Fig. 6
  • Adder 84 sums the 9 MSB's of the Sine value, P[ll:3], with the Amplitude A[8:0] to generate a nine bit output, AD[8:0] , and carry-out bit, CO.
  • Combinatorial Logic 88 performs the following:
  • MULADD[7:0] P[7:0] + A[4:0] , P[2:0]
  • the 8 LSB's of Ptll:0] are added with the 5 LSB's of A [8:0] concatenated with P[2:0]
  • a first signal value MULADD[7:0] output from the combinatorial logic device is input to the anti-log logic 92.
  • This signal MULADD[7:0] generally comprises the added logarithmic values of the logarithmic signals from registers 80 and 82, as added in the adder 84.
  • the anti- log logic 92 then converts the logarithmic signal value to a linear signal value (WFM[9:0]) and this linear signal output from the anti-log logic 92 is fed to a register 94.
  • a second output signal WCNT[3:0] from the combinatorial logic 88 is output to register 96.
  • This signal is a logarithmic value that defines the area of logarithmic space in which the waveform represented by signal MULADD[7:0] resides.
  • the creation of the two signals WCNT[3:0] and MULADD[7:0] permits the utilization of a smaller anti-log logic device than would otherwise be necessary.
  • the wave constructor 34 also includes a wave construction logic device 100, the inputs to which are the quadrant and wave selection signals Q and WS respectively.
  • the wave construction logic device 100 utilizes the selected wave shape value WS (as depicted in Fig.
  • the wave multiplexer logic 120 within the wave constructor 34 functions to create the output waveform value (o(t) or SLOTOUT[12 :0] ) , and it is further depicted in Fig. 7.
  • the output signal A[9:0] from register 94 to multiplexer 120 represents a one quarter sine wave function, in that it generally represents the sine logic signal output signal y(t) from the one-quarterwave sine logic 30 multiplied by the envelope generator signal e(t) from envelope generator 72.
  • the wave function signal values from registers 94 and 96 must be acted upon by the kill and invert signals from registers 116 and 112, in order to construct and output the various wave shapes depicted in Fig. 3.
  • the operation of the wave multiplexer logic 120 is set forth in Logic Table IV as keyed to Fig. 7.
  • A[9:0] is a linear value
  • WS[3:0] is the logarithmic value that defines the area of logarithmic space in which the waveform resides.
  • the INVERT signal inverts the result of the mapping below.
  • a full sine wave is selected as the desired output waveform shape (see Fig. 3) .
  • the first quadrant one-quarter wave output signals from register 94 and 96 are output in an unchanged manner from the multiplexer logic 120.
  • the output values from registers 94 and 96 represent the second quadrant values in that the final phase angle signal fp(t) was phase inverted in the angle wave select logic 70. These values are also output in an unchanged manner from the multiplexer logic 120.
  • registers 94 and 96 output a third set of one-quarter wave signals to represent the third quadrant of the full sine wave, and the wave multiplexer logic utilizes the invert signal from register 112 to place a negative value on the output values from the multiplexer logic 120.
  • a fourth set of one-quarterwave signals from registers 94 and 96 representing phase inverted sine logic outputs (as output in the second quadrant) is inverted with a negative value using the invert signal, such that the wave multiplexer logic output signal o(t) corresponds to the fourth quadrant of a full sine wave.
  • a rectified full sine wave is constructed from four sets of one-quart rwav- signals output from registers 94 and 96.
  • the doubled frequency one-quarterwave signal values therefore become resident in registers 94 and 96 in a time synchronized manner with the quadrant and wave select determined values for the kill and invert signals from the wave construction logic 100.
  • the output values from registers 94 and 96 for the third quadrant one-quarter wave are also equal to one (1) , however the invert signal from register 112 is utilized by the wave multiplexer logic 120 to output a minus one (-1) value in the third quadrant.
  • the output values from registers 94 and 96 for the fourth quadrant one- quarter wave signals are also equal to one (1) , and these values are then inverted by the wave multiplexer logic based upon an invert signal from register 112, such that the output becomes minus one (-1) .
  • the output signal o(t) from the wave multiplexer logic 120 is fed to the modulation logic 38 as previously indicated. Within the modulation logic 38, the signal o(t) is fed to an AND gate 130 and to a first sample register 134 of a self-modulation circuit 136.
  • the self- modulation circuit 136 also includes a second sample register 140, a third sample register 144, a subtractor 148 and a multiplier 152.
  • the output signal 60 from the self-modulation circuit 136 passes from the multiplier 152 to the adder 52 of the angle generator 28.
  • an output value o(t) is placed in sample register 134.
  • the signal stored in sample register 134 is transferred to sample register 140 and a new output signal from wave multiplexer logic 120 is stored in sample register 134.
  • the signal in sample register 140 is transferred to sample register 144 and the signal from register 134 is transferred to register 140.
  • registers 134, 140 and 144 each contain successive output signals from the wave multiplexer logic 120. Thereafter, in the next sample period the signal from register 144 is passed to the subtractor 148, and at the same time, a signal from register 134 is also passed to the subtractor 148. The difference between the two signals in subtractor 148 is then output to the multiplier 152 for multiplication by a constant K, and the output signal from the multiplier (K times the difference signal) is the signal 60 that is fed to the adder 52 of the angle generator 28.
  • the self-modulation circuit 136 provides an output signal 60 that represents the difference of two non-successive output signals from the wave multiplexer logic 120.
  • the significance of the self- modulation circuit 136 is to eliminate certain signal irregularities of the digital synthesizer when the value of the output signal o(t) approaches zero, as when the value of a sine wave function approaches zero at angles zero, 180° and 360°.
  • the output signals o(t) from the wave multiplexer logic 120 are fed to an AND gate 130 within the modulation logic 138.
  • a first output signal o(t) ' is constructed utilizing the angle generator 28, sine logic 30, envelope generator 32 and wave construction 34 elements of the generator 40 as discussed above.
  • the first output signal o(t)' is fed to the modulation circuit 38 whereupon it is fed back during the next sample period as the self-modulation signal 60.
  • the generator then incorporates the self-modulation signal 60 within the angle generator 28 to create a second output signal o(t), utilizing the angle generator 28, sine logic 30, envelope generator 32 and wave construction 34 components in the manner previously discussed.
  • the circuit 40 comprising the signal generator components has been essentially utilized four times in a time multiplexed manner to create the ultimate output signal o(t) 2 .
  • the first three circuit usages were performed to create the self-modulation signal 60; the fourth circuit usage was to create the modulation signal 62; the fifth circuit usage was to create the ultimate output signal o(t) 2 .
  • the modulation circuit 38 is not utilized in the fifth passage through the circuit components because to do so would create a signal such as 60 or 62 whereby a sixth passage through the circuit elements would be necessary to create an output signal from the wave constructor 34.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electrophonic Musical Instruments (AREA)

Abstract

Il s'agit d'un sytème amélioré de génération numérique de sons musicaux. Cet appareil se compose d'un générateur d'angle de phase (28), d'un élément logique sinusoïdal quart d'onde (30), d'un composant constructeur d'ondes (34) et d'un composant logique de modulation (38). Une valeur signal d'angle de phase est émise par le générateur d'angle de phase (28) et envoyée a l'élément logique sinusoïdal quart d'onde (30). Les éléments du circuit sont en connexion multiplex de manière à obtenir des échelons répétés de génération de signaux et à produire des sons musicaux synthétiques numériques.
PCT/US1995/014953 1994-11-14 1995-11-14 Synthetiseur numerique ameliore WO1996015584A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU41637/96A AU4163796A (en) 1994-11-14 1995-11-14 Improved digital synthesizer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34005094A 1994-11-14 1994-11-14
US340,050 1994-11-14

Publications (1)

Publication Number Publication Date
WO1996015584A1 true WO1996015584A1 (fr) 1996-05-23

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PCT/US1995/014953 WO1996015584A1 (fr) 1994-11-14 1995-11-14 Synthetiseur numerique ameliore

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AU (1) AU4163796A (fr)
WO (1) WO1996015584A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0973253A1 (fr) * 1998-07-16 2000-01-19 GRUNDIG Aktiengesellschaft Dispositif pour générer plusieurs signaux entrelacés à phase continue
WO2000018002A1 (fr) * 1998-09-23 2000-03-30 Nokia Networks Oy Appareil et procede de transmission multiporteuses

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4524326A (en) * 1982-07-22 1985-06-18 Amca International Corp. Digitally-driven sine/cosine generator and modulator
US4791377A (en) * 1987-10-20 1988-12-13 Gte Government Systems Corporation Direct frequency synthesizer
US5467294A (en) * 1994-03-09 1995-11-14 Hu; Vince High speed, low power direct digital synthesizer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4524326A (en) * 1982-07-22 1985-06-18 Amca International Corp. Digitally-driven sine/cosine generator and modulator
US4791377A (en) * 1987-10-20 1988-12-13 Gte Government Systems Corporation Direct frequency synthesizer
US5467294A (en) * 1994-03-09 1995-11-14 Hu; Vince High speed, low power direct digital synthesizer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0973253A1 (fr) * 1998-07-16 2000-01-19 GRUNDIG Aktiengesellschaft Dispositif pour générer plusieurs signaux entrelacés à phase continue
WO2000018002A1 (fr) * 1998-09-23 2000-03-30 Nokia Networks Oy Appareil et procede de transmission multiporteuses
AU755628B2 (en) * 1998-09-23 2002-12-19 Nokia Corporation Multi-carrier transmitting apparatus and method
US6810027B1 (en) 1998-09-23 2004-10-26 Nokia Corporation Multi-carrier transmitting apparatus and method

Also Published As

Publication number Publication date
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