WO1995033228A1

WO1995033228A1 - Computer reset signal debouncing circuit

Info

Publication number: WO1995033228A1
Application number: PCT/US1995/006332
Authority: WO
Inventors: Pascal Dornier
Original assignee: Elonex Technologies, Inc.
Priority date: 1994-05-27
Filing date: 1995-05-19
Publication date: 1995-12-07

Abstract

A computer reset debouncing circuit has a signature port (9) for inputting a prearranged digital signature, which alters the behavior of the debouncing circuit. Without the digital signature, as is the case on startup, a startup signal applied to the debouncing circuit starts a first counter (10), which, on reaching a preset count, provides a separate output signal (14) for startup. Under this condition, bounce in the input signal continues to reset the timer until the bounce is gone. A reset signal without the digital signature immediately resets the first counter (10). During bootup, the digital signature is provided to the debouncing circuit, and with the digital signature provided, a leading edge of an input reset signal starts a second counter (11), bounce continuing to reset the second counter (11), and the second counter (11) reaching a second preset value resets the first counter (10).

Description

Computer Reset Signal Debouncing Circuit

Field of the Invention

This invention relates generally to computers, and specifically to a circuit for debouncing a reset signal.

Background of the Invention

A typical personal computer (PC) can be reset or restarted either by software, keyboard input, or a reset signal from its reset button or its power supply. The reset line is typically called PWRGD (power good) in the art; the computer resets when PWRGD goes low.

A reset signal coming from the reset button typically exhibits considerable switch bounce or noise. Likewise, a reset signal coming from the power supply may also be noisy, because many manufacturers use less than the best available quality power supplies in some of their products.

Typically, even if there is noise or bounce, the signal still includes a clean middle portion accompanied by bouncy or noisy leading and trailing edges. In a typical PC, a bouncy signal is filtered by a Schmitt trigger (hysteresis circuit) and a large-value capacitor of perhaps lOuF. This simple analog circuit, however, cannot ensure proper debouncing for really poor signals. If a signal anomaly passes through this simple filter, it might well trigger an unintentional reset that could result in data loss.

What is needed is a reset circuit that ensures only intentional resets. Summary of the Invention

According to a preferred embodiment of the invention, a computer reset debouncing circuit is provided comprising a reset input; a first counter providing a high reset output for the computer at a preset first count value; a digital signature port; a digital signature register connected to the digital signature port for storing a digital value input at the digital signature port; a comparator circuit connected to the digital signature register and having access to a prestored digital signature for comparison with the digital value in the digital signature register; a second counter providing a second output at a preset second count value; and logic circuitry coupling the reset input, the first counter, the second counter and the comparator circuit. The logic circuitry is implemented so that, with the digital signature not stored in the digital signature register, a low-to-high transition at the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the preset first count value, provides the high reset output for the computer, and any subsequent high-to-low transition at the reset input resets the first counter to zero, including resetting the reset output to low. The logic circuitry further assures that, with the digital signature stored in the digital signature register, having been provided at the digital signature port, output from the comparator circuit causes a high-to-low transition on the reset input to start the second counter only, leaving the reset output high, any low-to-high bounce resetting the second counter, the second counter reaching the preset second count providing the second output which, through the logic circuitry, resets the first counter, causing the reset output to go low, and a subsequent low- to-high transition on the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the first count value, causes the reset output to go high. The computer reset debouncing circuit according to an embodiment of the invention is provided as an application- specific integrated circuit, and may be implemented in other ways as well. A computer utilizing the debouncing circuit as an embodiment of the invention is provided, and methods for practicing the invention using the disclosed apparatus are also provided.

The debouncing circuit of the present invention provides a single circuit that is operative to debounce an initial startup signal as well as requiring a preset time duration for a subsequent reset signal. The behavior of the debounce circuit can be changed by inputting a pre¬ arranged digital signature, which is provided to the debounce circuit during bootup, such as by the system BIOS.--

On page 3, in the section entitled "Brief Description of the Drawings", after the description of Fig. 2, add: —Fig. 3 is a block diagram of a computer with a computer reset debouncing circuit according to an embodiment of the present invention.

Brief Description of the Drawings

Fig. 1 is a circuitry diagram illustrating a reset debouncing circuit according to an embodiment of the present invention.

Fig. 2 shows time-voltage characteristics for a bouncy reset signal, a signature-invalid signal, and a signature-valid signal according to the invention.

Fig. 3 is a block diagram of a computer with a computer reset debouncing circuit according to an embodiment of the present invention.

Description Of The Preferred Embodiments

A reset signal debouncing circuit according to an embodiment of the present invention includes two counters, a signature register, a comparator, and assorted logic gates. Immediately after system powerup, one of the counters is disabled, so that the remaining counter filters a bouncy reset input signal into a clean reset output signal. At some time during initialization, the point being arbitrary, suitable firmware in the system BIOS writes a predetermined binary signature into the register. When the comparator validates the signature, it enables the first counter, which waits for a wide enough, i.e., clean, reset input signal before producing a reset output signal for the system. The second counter then delays the deactivation of the reset output signal for a predetermined time after the deactivation of the input signal. As a result, a fully debounced reset output signal is produced. Waiting for a wide enough reset input signal before producing a reset output signal for the system ensures the reliable filtering of all signal anomalies.

In accordance with a preferred embodiment of the invention as shown in Figs. 1 , 2, and 3 a reset signal debouncing circuit 8 includes counters 10 and 11, a signature register 24, a signature comparator 12, a BIOS 15 storing a reference binary signature, and assorted logic gates described below.

Immediately after system powerup, register 24 will have a random signature that has a high probability of not matching the reference signature. The reference signature in this example is assumed to be the eight-bit number 0110 1001. It could as well be any other eight-bit number, or, in other hardware embodiments, a number of more or fewer bits.

Without having the valid signature of 0110 1001 at its inputs, comparator 12, a NAND gate in this example, produces a high output on line 16, so that OR gate 17 pulls line 18 high. In this embodiment register 24 is a model 74LS75 register with dual 4-bit latches set up together for 8-bit operation. Alternatively, a 24-bit or larger signature, and a correspondingly sized register can be used to practically eliminate the chance of having a random match upon powerup. Also, alternative signatures having a mix of l's and O's can be validated by using other gates or combinations thereof, or by connecting to the signature register in a different way.

A clock input line 23 supplies a regular clock signal (not shown) to counter 10 through a NOR gate 22. The clock signals can come from any one of several clocks (not shown) that are present in a typical PC. Upon powerup, reset input line 13 is high. A 74LS74 or Schmitt inverter 19 inverts the high, so that an AND gate 20 will pull line 26 low to start counter 10.

In this embodiment, reset output line 14 will go high on the count of 128, at which time NOR gate 22, by virtue of feedback from line 14, will block additional clocks from reaching counter 10. Counter 10 will stop counting, and reset output line 14 will remain high or deactivated, so computer 28 will begin its initialization process. Counters 10 and 11 are both 74LS393's in this embodiment, each with dual 4-bit binary counters cascaded together. Alternatively, counter 10 can be set for other counting limits, or additional counter stages can be added for counting to greater numbers.

When the circuit is in this state, i.e, when the signature is invalid, the leading edge of a bouncy reset input signal 13S (Fig. 2), coming from either a reset button (not shown) or the power supply (not shown), will pass through Schmitt inverter 19 and AND gate 20 as a high to clear counter 10. The counter's outputs are zeroed when cleared, including reset output line 14. A clean leading edge of reset output signal 14A is thus produced, as shown in Fig. 2. Output 14 will now remain low until counter 10 is started and then completes its count.

Output signals 14A and 14B of Fig. 2 represent output signals on line 14 of Fig. 1 under two different sets of circumstances; 14A for an invalid signature, and 14B for a valid signature.

When reset output signal 14A is active (low), NOR gate 22 will pass the clock signals on clock line 23 to input A of counter 10. When the trailing edge of the input signal on line 13 is encountered, line 26 goes low, starting counter 10. Counter 10 counts clock pulses until the preset limit is reached, then reset output line 14 will go high to produce the clean trailing edge of reset output signal 14A, as shown in Fig. 2. The reset signal is thus fully debounced. When line 14 goes high, NOR gate 22 will block the clock signals to stop counter 10.

While counter 10 is counting, any glitch in reset input signal 13S that passes through Schmitt inverter 19 will clear counter 10 and keep reset output signal 14A active low. After the trailing edge of reset input signal 13S, or after the last glitch, counter 10 will make a full count from 0 to its limit before producing the clean trailing edge of reset output signal 14 A. As a result, the trailing edge of reset output signal 14A is delayed from the trailing edge of the input signal by a time Tl, which is equal to the amount of time counter 10 takes to make the full count, as shown in Fig. 2.

The exact value of time Tl depends on the speed of the clock signal and the count limit. Bouncy reset input signal 13S is thus fully debounced into clean reset output signal 14A.

Counter 11 is normally cleared upon powerup by a high signal on reset input line 13. After the computer begins initialization, BIOS 15 writes the valid signature to register 24 via signature port 9. Upon receiving the valid signature, comparator (NAND gate) 12 pulls line 16 low, so OR gate 17 pulls line 18 low. When the leading edge of the bouncy reset input signal 13S arrives, it passes through inverters 19 and 21 as a low to enable counter 11 to begin counting. In this condition, i.e., when the signature is valid, counter 10 is prevented from being cleared by AND gate 20 because of the low on line 18, so reset output line 14 remains high or (inactive). Counter 11 will continue to count for as long as bouncy reset input signal 13S is active or low.

Any anomaly in reset input signal 13S will reset counter 11 and repeat the counting. As long as counter 11 is counting, it will maintain a low on line 25. OR gate 17 will then keep line 18 low, AND gate 20 will maintain a low on line 26 to prevent counter 10 from clearing, and reset output 14 will remain high.

Counter 11 will only complete its counting when reset input signal 13S remains low for long enough without interruption. When its limit is reached, which is 128 in this example, counter 11 will pull line 25 high, and NOR gate 27 will block additional clock signals from counter 11 to stop it. Also, OR gate 17 will pull line 18 high, so that AND gate 20 will pass reset input signal 13S to clear counter 10, thereby producing the leading edge of a clean reset output signal 14B, as shown in Fig. 2.

The leading edge of reset output signal 14B is delayed from the last glitch on the leading edge of reset input signal 13S by a time T2, which is equal to the time counter 10 takes to count to its limit. This ensures that a reset output signal is only produced upon the receipt of a genuine reset input signal.

Counter 10 will remain cleared for as long as reset input signal 13S remains active, or if any glitch is present. At the trailing edge of reset input signal 13S, after the last glitch, line 26 will go low, so that counter 10 will begin counting. When counter 10 reaches its count limit, it will output a high on reset output line 14 as the clean trailing edge of reset output signal 14B, as shown in Fig. 2. A high on line 14 will cause NOR gate 22 to block additional clock signals from counter 10 to stop the counting. The time counter 10 takes to count up to its limit produces a time delay Tl between the trailing edges of the reset input and output signals. Accordingly the reset signal debouncing circuit will, upon validating the stored signature, only output a reset signal when a wide enough reset input signal is received. This positively ensures proper debouncing of reset signals and filtering of glitches on the input line. As a result, the circuit will prevent noise on the reset line from causing unintentional system restarts.

Although the above descriptions are specific, they should not be considered as limitations on the scope of the invention, but only as examples of the preferred embodiments. Many other ramifications and variations are possible within the spirit and scope of the invention. In addition to the alternative components already described, additional alternatives are possible. For example, different logic devices can be used for the counters, register, and for the comparator. In like manner, different interconnecting logic gates can be used in different ways for achieving the same results.

Instead of being a collection of discrete devices, the reset debouncing circuit can be built into an ASIC (Application Specific Integrated Circuit) for reduced space requirement and component cost. Therefore the scope of the invention should be determined by the appended claims and their legal equivalents, and not just by the examples given.

Claims

What is claimed is:

1. A computer reset debouncing circuit, comprising: a reset input; a first counter providing a high reset output for the computer at a preset first count value; a digital signature port; a digital signature register connected to the digital signature port for storing a digital value input at the digital signature port; a comparator circuit connected to the digital signature register and having access to a prestored digital signature for comparison with the digital value in the digital signature register; a second counter providing a second output at a preset second count value; and logic circuitry coupling the reset input, the first counter, the second counter and the comparator circuit; wherein, with the digital signature not stored in the digital signature register, a low-to-high transition at the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the preset first count value, provides the high reset output for the computer, and any subsequent high-to-low transition at the reset input resets the first counter to zero, including resetting the reset output to low; and wherein, with the digital signature stored in the digital signature register, having been provided at the digital signature port, output from the comparator circuit causes a high-to-low transition on the reset input to start the second counter only, leaving the reset output high, any low- to-high bounce resetting the second counter, the second counter reaching the preset second count providing the second output which, through the logic circuitry, resets the first counter, causing the reset output to go low, and a subsequent low-to-high transition on the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the first count value, causes the reset output to go high.

2. A computer reset debouncing circuit as in claim 1 implemented as an application-specific integrated circuit (ASIC).

3. A computer reset debouncing circuit as in claim 1 wherein the digital signature port is connectable to a communication bus of the computer.

4. A computer reset debouncing circuit as in claim 1 wherein the digital signature is supplied to the digital signature port during a bootup process.

5. An integrated circuit for providing a reset signal for a computer, the integrated circuit comprising: a reset input; a first counter providing a high reset output for the computer at a preset first count value; a digital signature port; a digital signature register connected to the digital signature port for storing a digital value input at the digital signature port; a comparator circuit connected to the digital signature register and having access to a prestored digital signature for comparison with the digital value in the digital signature register; a second counter providing a second output at a preset second count value; and logic circuitry coupling the reset input, the first counter, the second counter and the comparator circuit; wherein, with the digital signature not stored in the digital signature register, a low-to-high transition at the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the preset first count value, provides the high reset output for the computer, and any subsequent high-to-low transition at the reset input resets the first counter to zero, including resetting the reset output to low; and wherein, with the digital signature stored in the digital signature register, having been provided at the digital signature port, output from the comparator circuit causes a high-to-low transition on the reset input to start the second counter only, leaving the reset output high, any low- to-high bounce resetting the second counter, the second counter reaching the preset second count providing the second output which, through the logic circuitry, resets the first counter, causing the reset output to go low, and a subsequent low-to-high transition on the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the first count value, causes the reset output to go high.

6. An integrated circuit as in claim 5 wherein the digital signature port is connectable to a communication bus of the computer.

7. An integrated circuit as in claim 5 wherein the digital signature is supplied to the digital signature port during a bootup process.

8. A computer comprising: an input power-good (PWRGD) line; a debouncing circuit connected to the input PWRGD line; and an output PWRGD line from the debouncing circuit; the debouncing circuit comprising: a first counter providing a high output on the output PWRGD line at a preset first count value; a digital signature port; a digital signature register connected to the digital signature port for storing a digital value input at the digital signature port; a comparator circuit connected to the digital signature register and having access to a prestored digital signature for comparison with the digital value in the digital signature register; a second counter providing a second output at a preset second count value; and logic circuitry coupling the reset input, the first counter, the second counter and the comparator circuit; wherein, with the digital signature not stored in the digital signature register, a low-to-high transition at the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the preset first count value, provides the high reset output for the computer, and any subsequent high-to-low transition at the reset input resets the first counter to zero, including resetting the reset output to low; and wherein, with the digital signature stored in the digital signature register, having been provided at the digital signature port, output from the comparator circuit causes a high-to-low transition on the reset input to start the second counter only, leaving the reset output high, any low- to-high bounce resetting the second counter, the second counter reaching the preset second count providing the second output which, through the logic circuitry, resets the first counter, causing the reset output to go low, and a subsequent low-to-high transition on the reset input starts the first counter, resetting the first counter with any high-to-low bounce, and the first counter, on reaching the first count value, causes the reset output to go high.

9. A computer as in claim 8 wherein the debouncing circuit is an application-specific integrated circuit (ASIC).

10. A computer as in claim 8 wherein the digital signature is supplied to the digital signature port during a bootup process.

11. A method for debouncing startup and reset signals for a computer, comprising steps of:

(a) providing a startup signal to a reset input of a debouncing circuit;

(b) starting a first counter with the startup signal;

(c) resetting the first counter with any bounce following the startup signal;

(d) providing a PWRGD output from the timer upon reaching a preset first counter count, the PWRGD output starting a bootup process for the computer;

(e) providing a prearranged digital signature to the debouncing circuit as a part of the bootup procedure; and

(f) altering the behavior of the debounce circuit by the presence of the digital signature such that a leading edge of a reset signal on the reset input starts a second counter, not starting or resetting the first counter, bounce following the leading edge of the reset signal on the reset input resetting the second counter, the second counter reaching a preset second counter value resetting the first counter and providing thereby a leading edge of an output reset signal on the PWRGD output, a subsequent trailing edge of the reset signal on the reset input starting the first counter, bounce following the trailing edge of the reset signal on the reset input resetting the first counter, and the first counter timing out providing a trailing edge for the output reset signal on the PWRGD output.