JPH01268219A - Noise eliminating circuit - Google Patents

Abstract

PURPOSE:To eliminate noise by inputting samples of data on a data bus transmitted synchronously to clocks at clocks which are prescribed times as fast as the first-mentioned clocks and outputting the data to a signal bus by taking the majority of the samples. CONSTITUTION:For example, data on a data bus 3 or address bus are sampled by means of sampling means (8-bit latch) 1 at clocks (generated by a clock generator 4) which are prescribed times as fast as the 1st clocks (transmitting clocks) for transmitting the data. The data having the most abundant same-value data in the plural samples are extracted and established as the data of the signal by means of a signal extracting means (majority circuit) 2. Therefore, even if noises get into the data bus 3 or address bus and the value of the data transiently changes, the proper data from which the majority is taken are outputted from a noise elimination circuit 10 10 as noise-eliminated data. Thus the malfunction of an electronic apparatus can be prevented certainly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise removal circuit for signal lines connecting a plurality of digital circuits such as microcomputers that perform predetermined operations based on digital data.

[Prior Art] In electronic equipment that transmits signals using digital signals, various noises may enter the signal system inside the electronic equipment from the outside depending on the environment in which it is used, causing digital circuits such as the central processing unit (CPU) to malfunction. Sometimes I do things or go out of control.

The reason why this digital circuit malfunctions will be explained in detail.

FIG. 5 is a timing chart of a read signal showing the waveform of a general signal transmitted on the data bus and the waveform of a read signal that conveys an instruction to read this waveform signal. C.P.
Since U reads data at the rising edge of the read signal, if noise appears at that moment, the data will be misread even if there is no noise elsewhere. There's a problem.

In Figure 5, each signal line of the data bus has a bit “1°”.
A digital signal is transmitted by applying a voltage at the "H" level indicating the bit "0" or a voltage at the "'L" level indicating the bit "0°". The application time of the voltage is constant, and when transmitting digital signals in time series, a voltage corresponding to the digital bit format is applied for a certain period of time in synchronization with a predetermined cycle.

When exchanging signals between the CPU and memory, when a read signal is output from the CPU at level "L" to the memory, the memory transfers the stored multiple bit information to the CPU.
Output to U. If noise enters the data bus at this time, the voltage state applied to the data bus will change, causing the transmitted data to change from bit °゛0''° to pit 1°°, which will cause the CPU operation timing to change. Crazy C
This can lead to a problem that causes the PU to run out of control.

Therefore, it is desirable to increase the noise tolerance of these electronic devices as much as possible in order to eliminate malfunctions. Conventional noise countermeasures include installing filters as noise removal circuits in input/output circuits such as interfaces, and covering the outer periphery of the printed circuit board on which the input/output circuits are placed with a shield plate. is taken.

[Problems to be solved by the invention] However, conventional noise removal circuits using filters are limited in the frequency band of noise that can be removed, and the covering of the shield plate is not easy to process, making it impossible to completely remove noise. However, there is a need for a noise removal circuit that can remove noise more reliably.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a noise removal circuit that can remove noise more reliably.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a noise removal circuit that removes noise from a signal connected between signal lines and transmitted on the signal line. a clock generating means for generating a second clock that is a predetermined times faster than the first clock used for human output timing of the signal; A sampling means that samples the signals multiple times, and selects and outputs only the signals that match a certain number of times or more among the plurality of signals sampled multiple times by the sampling means as noise-removed signals to the output side of the signal line in synchronization with the first clock. The present invention is characterized by comprising a signal extraction means.

[Function] In electronic equipment that handles digital data, the present invention samples data on, for example, a data bus or an address bus by a sampling means with a clock that is a predetermined times faster than a first clock for transferring the data. The signal extraction means extracts the data with the most matching values from among the plurality of data thus obtained, and establishes the data as the data of that signal. As a result, even if there is noise on the data bus or address bus and the data value temporarily differs, the correct data obtained by majority vote will be output from the noise removal circuit as the data after noise removal. Malfunctions of electronic equipment can be more reliably prevented.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

In FIG. 1, the dashed-dotted line block indicates the noise removal circuit according to the present invention.

A noise removal circuit is provided on a data bus that connects each circuit of an electronic device. In this example, the data bus is 8
It is assumed that it consists of a wooden signal line and transmits 8-bit information.

In the noise removal circuit 10, 1 is a latch circuit that holds and outputs a human input signal in synchronization with the clock (second clock) generated by the clock generator 4, and a flip-flop can be used. In this example, five such latch circuits are connected in series to the input end 4 of the data bus of the noise removal circuit 10.

Such multiple latch circuits are well known as shift registers and serial-to-parallel converters.

The output of each latch circuit 1 is input to a majority circuit 2, which will be described later, and the output terminal of the majority circuit 2 is connected to the data bus output side 5 of the noise removal circuit 10.

A clock generator 4 supplies predetermined clocks to the five latch circuits 1. The period of this clock corresponds to the number of latch circuits 1, and is five times faster than the period of data transmitted on the data bus.

Next, the majority circuit 2 will be explained.

Figure 2 (A) shows the configuration of a majority circuit that outputs the majority of the values of three human input signals. In Figure 2 (A), the signal on one signal line in the data bus is For example, the output signals A, B, and C sampled by the latch circuit are pid 'o''.

When signals 0''' and 1° are inputted to the 3-input circuit 2-10, the output signal of the EXOR circuit 2-1 which inputs signals A and B becomes 0''' and the inversion of the output signal. The output signal E of the logic circuit 2-2 which ANDs the input and the signal A is 0"'. Also, the output signal of EXOR circuit 2-1 and signal C
The output signal F of the AND circuit 2-3 which manually inputs is °゛0゛°
is obtained. Therefore, the output signal of the OR circuit 2-4 which uses signals E and F manually becomes °゛0°°, and the signals A, B,
As a majority vote of C("o", "o°', "1")"
o” is obtained.

FIG. 2(B) shows a 5-input circuit using the above-mentioned three-man power majority circuit, in which each output signal A of the first to fifth latch circuits 1 is
-E shows a logic circuit that performs majority operation. This circuit is also the second
It is constructed using gate circuits similar to the three-person majority voting circuit shown in Figure (8).

Further, the majority circuit 2 of this embodiment is provided with eight such majority circuits 2-10 corresponding to each signal line of the data bus. In this embodiment, the configurations of the three-man power majority circuit 2-1O and the five-man power majority circuit 2-20 have been shown, but it goes without saying that they may be constructed using gate circuits depending on the number of latch circuits 1.

Note that when there are a large number of latch circuits 1, a read-only memory (ROM) may be used to perform majority calculation. The majority vote result of each bit value of this address is stored in advance in correspondence with the value of the address of the ROM.

For example, the memory area for the 5-bit address "00001" has a majority value of 0' as the value of each bit of this address.
By inputting the output signals A to D of the latch circuits as address signals, the output of the ROM becomes the result of the majority operation. Further, the output of the majority circuit 2 is output in synchronization with the transmission lock (first clock) of the data bus using a flip-flop or the like.

FIG. 3 shows an example of a system configuration of an electronic device using the noise removal circuit IO shown in FIG.

In FIG. 3, the noise removal circuit 10 is arranged on a data bus between a CPU 40 and a human output device 20, 30 such as an interface. Note that when the human power device 20 and the output device 30 are connected to the CPU 40 by a common bus, a noise removal circuit that removes noise in the human power signal to the CPU 40 according to the read and write timings of the CPU and the output signal from the CPU 40 are connected. What is necessary is to switch and connect the noise removal circuits that remove the noise on the common bus.

From the device 50 to be controlled by the CPU 40 to the human powered device 2
Even if noise partially intrudes into the data output through the CPU 40 as shown in FIG. ) The data on the data bus input end DB is sampled in time series at the timing of the sampling clock shown in The output of the cancellation circuit will represent the correct data.

In this embodiment, the noise removal circuit 10 is installed on the data bus at a position close to the input end of the CPU 40 or the input side of the output device, but the noise removal circuit is installed at any position on the data bus where noise is induced. You can. Particularly when the data bus is long, it is preferable to install them at multiple positions on the data bus. As a result, it is possible to remove noise induced in the data bus on the way from the signal transmitting side to the signal receiving side and transfer correct data.

In addition, in this embodiment, the present invention is provided between the CPU 40 and the human output device 20.30, but the present invention can also be applied to equipment that handles digital signals transmitted in synchronization with a clock, such as memory 2 counters, registers, etc. Can be applied.

[Effects of the Invention] As explained above, according to the present invention, data on a data bus that is transmitted in synchronization with a clock is manually sampled using a clock that is a predetermined times faster than this clock, and the majority decision of this sampled data is performed manually. By outputting data onto the signal bus by taking the signal, even if noise enters the signal bus, the data in the noise portion is ignored, so the noise can be removed.

Furthermore, since the present invention establishes the transfer data by a majority vote of the sampled data, the transfer signal waveform is not deformed unlike the conventional filter type noise removal circuit. Furthermore, compared to conventional shield-type noise prevention devices, the present invention has the advantage that it is easy to manufacture circuits for electronic equipment because it is only necessary to install the noise removal circuit on the data bus.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention. FIGS. 3 is a block diagram showing the arrangement of the noise removal circuit 10 according to the embodiment of the present invention, FIG. 4 is a timing chart showing the operation timing of the noise removal circuit 10 shown in FIG. 1, and FIG. 5 is the noise influence in the conventional example. 2 is a timing chart for explaining. DESCRIPTION OF SYMBOLS 1...Latch circuit, 2...Majority circuit, 3...Data bus manual operation, 4...Sampling clock generator, 5...Data bus output, 10...Noise removal circuit, 20... - Human power device, 30... Output device, 40... CPU. 50...Controlled data bus.

Claims (1)

[Claims] In a noise removal circuit that removes noise from a signal connected between signal lines and transmitted on the signal line, a second clock that is a predetermined times faster than a first clock used for input/output timing of the signal on the signal line is provided. a clock generating means for generating a clock; a sampling means for sampling a signal on the signal line a plurality of times within a cycle of the first clock using the second clock generated from the clock generating means; and signal extracting means for selectively outputting only signals that match a certain number of times or more out of a plurality of signals sampled twice as noise-removed signals on the output side of the signal line in synchronization with the first clock. Features a noise removal circuit.