WO1995026570A1

WO1995026570A1 - Ferroelectric memory device

Info

Publication number: WO1995026570A1
Application number: PCT/JP1995/000533
Authority: WO
Inventors: Hiroshi Nakano; Masayoshi Ohmura
Original assignee: Olympus Optical Co., Ltd.; Symetrix Corporation
Priority date: 1994-03-29
Filing date: 1995-03-23
Publication date: 1995-10-05

Abstract

A ferroelectrique capacitor used in a memory cell section of a ferroelectric memory device comprises a polarization P1 region having a film thickness (d) and an area S1, and a polarization P2 region which is a component in the P1 direction of oblique polarization P2 having only one electrode section and an area S2. The combined hysteresis characteristics of the polarizations P1 and P2 include a twisted hysteresis characteristic. When the memory state of the twisted hysteresis characteristic is '0' and '1', nondestructive readout is possible due to a back switching phenomenon. A ferroelectric memory device of another mode of this invention comprises a ferroelectric capacitor (11) which has a multiplex hysteresis characteristic having at least three stable polarization values attributed to the twisted hysteresis characteristic and is formed by sandwiching a ferroelectric material which stores multilevel voltages resulting from the multiplex hysteresis characteristic as information between electrode materials, dielectric capacitor (12) connected in series to the capacitor (11), and voltage-current converting element (16) which reads out the multilevel information stored in the capacitor (11).

Description

Description Ferroelectric memory device Technical field

The present invention relates to a ferroelectric memory device using a ferroelectric material for an information recording medium, and in particular, to a ferroelectric memory device for performing non-destructive readout using a twisted- ♦ hysteresis characteristic. Also, the present invention relates to a ferroelectric memory device using a ferroelectric for a recording medium, and more particularly to a ferroelectric memory device capable of reducing a stable polarization value by at least 3 using a twisted-hysteresis characteristic. The present invention relates to a ferroelectric memory device using a ferroelectric memory element exhibiting multiple hysteresis characteristics having more than one device. Background art

In general, it is known that ferroelectric materials have hysteresis characteristics and can store information as a non-volatile memory using this characteristic. Conventionally, the reading method of these ferroelectric memories has been performed by destructive reading using a domain-inverted current that requires rewriting of a selected cell.

On the other hand, in Japanese Patent Application No. 5-68890 filed by the present applicant, and in USP 5,514,154, and Japanese Patent Application Laid-Open No. 5-198,194 filed by other applicants, A ferroelectric memory based on a non-destructive readout method using a capacitance difference governed by the polarization state is proposed. Is being planned.

However, the conventional ferroelectric memory described above has the following disadvantages.

First, ferroelectric memory by the destructive readout method is characterized by the fact that polarization reversal is repeated and ferroelectricity deteriorates, so that the remanent polarization is reduced. It is not only difficult to prolong the service life due to problems such as the problem of rewriting, but also it is necessary to rewrite with a complicated circuit.

In addition, in the ferroelectric by the non-destructive read method of the present applicant and other applicants, non-destructive information is read in a read electric field smaller than the coercive electric field by utilizing a capacitance difference controlled by a polarization state. Reading is being performed. However, in such a ferroelectric memory, when non-destructive reading is actually performed, the difference in capacitance between recorded and unrecorded states is small, so that the S / N ratio is deteriorated and the cell integration is reduced. with, since the signal level is Naru rather small, may not be able to distinguish between data and Noi's, densification hardly Kashii _£ other hand, a thin film was formed tiger Njisuta ferroelectric bulk in the conventional nonvolatile Semiconductor memory devices have been proposed. In recent years, a prototype device (MFIS device or MFMIS) in which a strong dielectric thin film is formed on a gate of a field effect transistor (FET) has been manufactured. These MFIS elements or MFMIS elements are effective as nondestructive readable memory elements, and are currently attracting attention.

This conventional MFMIS type device will be described below.

Figure 22A shows an example of a conventional MFMIS-type device, — ♦ This is an equivalent circuit composed of a combination of a tower (Sawyer Tower) circuit and a field-effect transistor. A ferroelectric capacitor (C _FE) 20 1 and the dielectric Capacity evening (CL) 2 02 terminal 204 of Soiya-Tawa circuits connected in series, each capacitor voltage across when applying a sinusoidal voltage, FIG. It shows hysteresis characteristics as shown in 22B. After that, when the terminal 204 is grounded, it becomes stable at the point of M _Q or M j shown in FIG. 22B.

For example, the in V in this respect is a positive value, in the voltage V _eT to M _Q point is a negative value. The voltage information stored in the dielectric capacitor ( _CL ) 2 is read out by the field-effect transistor 203. Here, the field-effect transistor 203 is an n-type MOSFET, so that at a point, the field-effect transistor 203 is in a conducting state, at a point, a non-conducting state, and The difference in voltage at point _Q can be read. Note that the voltage v _ei; (= —

If V _FE ) is maintained, reading can be performed nondestructively.

Further, as another example, a memory element having a configuration shown in FIG. 23A has been devised as a memory element capable of nondestructive operation to prevent the deterioration of the strong dielectric thin film.

This memory element includes a ferroelectric capacitor 206, a dielectric capacitor 207 connected in series to the ferroelectric capacitor 206, and a resistance element 208 connected in parallel to the dielectric capacitor 207. Consists of Also, this memory The element is provided with a field-effect transistor 209 as a switch element for reading.

In this memory element, when the charge accompanying the polarization reversal of the ferroelectric capacitor 206 is stored in the dielectric capacitor 207, a part of the charge is discharged by the resistance element 208. Therefore, when the memory is held, the voltage generated by the ferroelectric capacitor 206 in the ferroelectric capacitor 206 is prevented from being canceled by the electric charge accumulated in the dielectric capacitor 207, and the holding time is maintained. Is to lengthen. FIG. 23B shows a hysteresis characteristic in a circuit in which the resistive element 208 is connected in parallel with the dielectric capacitor 207. As a result, when a positive voltage is applied to the ferroelectric capacitor ₂₀₆ , the result is that the ferroelectric capacitor ₂₀₆ is stabilized at the point _Μρι , and the voltage V _FE of the ferroelectric capacitor ₂₀₆ at that point is accurate. It can be seen that the memory voltage in the same direction as the applied electric field is remembered. Conversely, when a negative electric field is applied, the voltage becomes stable at the point of M _pQ , and the voltage V _pr at that point becomes negative.

With such a configuration of the memory _element , the storage voltages Μ _ρϋ , Μ _ρι have two polarizations P 0, P j of the ferroelectric capacitor ₂₀₆ and electric fields in the directions of the polarizations. Is obtained. When reading this memory element, the current flowing between the terminal 205 and the ground via the field effect transistor 209 which is ON-OFF controlled by the voltage of the dielectric capacitor 207 Can be detected.

As the readout transistors in the two conventional examples described above, In practice, the polarity of the stored information is detected as the direction of the read current by using a switch element that is actually turned on by a positive voltage and a conductive switch element that is turned on by a negative voltage. A storage element is used for an arithmetic unit or the like. As the readout switch element, an element composed of an n-type MOS transistor and a p-type MOS transistor formed on a silicon (Si) substrate is known. It is.

Also, when creating a resistor on a silicon (Si) device, use the channel resistance of the MOS transistor or use a doped polysilicon. It is known.

Memory devices manufactured by arranging a plurality of the above-mentioned ferroelectric memory elements have already been manufactured by Lamtron, Krisalis, and others in the United States. Also, a vector multiplier using binary information (1,0) using SRAM as a storage element is in a prototype stage ₍ however, the ferroelectric memory constituting the conventional memory device described above). serial billion can be information on the device, two stable polarization with a ferroelectric, is based on Ρ, Ρ () → Ρ _{young properly is P i -! * polarization inversion at the time of transition to the P ₀ The charge information associated with this, that is, ordinary ferroelectrics have only two stable polarization states, so the information that can be stored is binary (binary memory).

In general, a large number of memory elements are arranged, and each memory element is marked with 1 or 0, and a sequence of these two numerical values is used as stored information.

Therefore, as the amount of information to be stored increases, As the number of memory elements required for this purpose increases, the size of the memory device increases, and this also entails problems such as an increase in power consumption and heat dissipation. Furthermore, the control circuits that control these storage devices also become larger, which slows down the processing time and complicates the control. Disclosure of the invention

Therefore, the present invention has been made in view of the above-described points, and can perform non-destructive readout by using the twisted-hysteresis characteristic, has a long life, and is ferroelectric suitable for integration. It is intended to provide a body memory device.

Further, the present invention provides a ferroelectric memory device using a ferroelectric memory element having a multiple hysteresis characteristic having at least three or more stable polarization values by utilizing the twisted hysteresis characteristic. The purpose is to provide.

According to a first aspect of the present invention, in order to achieve the above object, a first electrode formed of a conductive film formed on a substrate, and a ferroelectric formed on the first electrode and on which information is written And a plurality of second electrodes made of a conductor film formed on the ferroelectric film, wherein a formation arrangement relationship between the first electrode and the second electrode or an area of an electrode area opposed to each other is provided. A ferroelectric memory device is provided which differs in at least one of the sizes.

According to a second aspect of the present invention, a lower electrode film formed on an insulator, a ferroelectric film formed on the lower electrode film, and an upper electrode formed on the ferroelectric film Unit consisting of membrane A plurality of first capacitor units formed by ferroelectric capacitors are formed on the insulator, and a plurality of first capacitor units having different coercive electric fields from the first capacitor unit on the insulator. The second capacitor unit is formed with a lower electrode newly formed on the insulator, a ferroelectric film formed on the lower electrode, and a ferroelectric film formed on the lower electrode. And at least one or more of the first and second capacitor units are electrically connected to each other. A ferroelectric memory device is provided.

Furthermore, according to the third aspect of the present invention, the multi-hysteresis characteristic having at least three or more stable electrode values is provided, and the multi-valued voltage accompanying the multi-hysteresis characteristic is used as information. A ferroelectric capacitor formed by sandwiching a ferroelectric between electrode materials; a dielectric capacitor connected in series to the ferroelectric capacitor; and the multiple hysteresis stored in the ferroelectric capacitor. Provided is a ferroelectric memory device including a voltage-current conversion element for reading out multi-valued voltage information accompanying the lysis characteristic.

In the ferroelectric memory device according to the first aspect as described above, when an electric field is applied to the ferroelectric capacitor, the electric field strength of the second electrode area is smaller than the electric field strength of the first electrode area. It becomes smaller, and has the same effect as if a ferroelectric capacitor with a different coercive electric field (or film thickness) and area were connected in parallel, and a twisted hysteresis characteristic was obtained. The memory state "0" and memory state "1" of this twisted hysteresis characteristic In these two values, the information stored by the back-switching phenomenon is read non-destructively.

Further, the ferroelectric memory device according to the second embodiment is such that a first ferroelectric capacitor (unit) is sandwiched between electrodes made of a conductor on both sides of a ferroelectric substance on a substrate or an insulator. And a second ferroelectric capacitor (unit) having a different coercive electric field or a different film thickness is formed in parallel or in a stacked configuration. A cis characteristic is obtained.

Further, the ferroelectric memory device having the configuration according to the third aspect includes a ferroelectric capacitor having multiple hysteresis characteristics having at least three or more stable polarization values and a serial connection with the ferroelectric capacitor. A ferroelectric memory element consisting of a connected dielectric capacitor and a multi-valued voltage information written using the multiple hysteresis characteristic is read out by a voltage-to-current conversion element. Three or more pieces of voltage information can be obtained when the polarization state changes with a stable polarization value. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a combined hysteresis characteristic in a ferroelectric memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a configuration of a ferroelectric capacitor in the ferroelectric memory device of the first embodiment;

FIG. 3 is a block diagram showing a configuration in which the ferroelectric capacitors shown in FIG. 2 are arranged as a memory cell and peripheral circuits are connected; FIG. 4 is a diagram showing a configuration example of the ferroelectric memory device according to the second embodiment of the present invention in which the shape of the upper electrode of the ferroelectric capacitor is different;

FIG. 5 is a view showing a configuration example of a ferroelectric memory device according to a third embodiment of the present invention in which ferroelectric capacitors having different coercive electric fields having the structure shown in FIG. 2 or FIG. 4 are connected in parallel. ;

FIG. 6 is a diagram showing a configuration in which ferroelectric capacitors formed of different ferroelectric materials and having different coercive electric fields are connected in parallel in a ferroelectric memory device according to a fourth embodiment of the present invention;

7A and 7B show a ferroelectric capacitor showing a symmetric hysteresis characteristic and a ferroelectric capacitor showing an asymmetric hysteresis characteristic in a ferroelectric memory device according to a fifth embodiment of the present invention. Diagram showing a configuration example connected in parallel and its combined hysteresis characteristics;

8A to 8E are diagrams showing an example of a laminated structure of a ferroelectric capacitor having an asymmetric hysteresis characteristic in a ferroelectric memory device according to a sixth embodiment of the present invention and the characteristics thereof;

9A and 9B are diagrams showing another structural example and characteristics of a ferroelectric capacitor having asymmetric hysteresis characteristics in a ferroelectric memory device according to a seventh embodiment of the present invention;

FIG. 10 is a diagram showing an example of a laminated structure of ferroelectric capacitors formed in parallel on a substrate in a ferroelectric memory device according to an eighth embodiment of the present invention;

FIG. 11 shows a ferroelectric memory device formed in parallel on a substrate in a ferroelectric memory device according to a ninth embodiment of the present invention. View showing another example of the laminated structure;

FIG. 12 is a diagram showing an example of a laminated structure of ferroelectric capacitors formed by being laminated on a substrate in a ferroelectric memory device according to a tenth embodiment of the present invention;

FIGS. 13A, 13B and 13C show the multiple hysteresis characteristics of the ferroelectric memory element used in the ferroelectric memory device according to the eleventh embodiment of the present invention. A diagram showing the configuration of the dielectric memory device and the current-voltage characteristics of the ferroelectric memory device;

FIGS. 14A to 14H show the multi-hysteresis characteristics and spontaneous polarization of the ferroelectric memory device shown in FIG. 13B; FIGS. 15A and 15B show the first and second embodiments of the present invention, respectively. FIG. 1 is a diagram showing a configuration of a ferroelectric memory device used in a ferroelectric memory device as an example and a current-voltage characteristic of the ferroelectric memory device;

FIGS. 16A to 16C show the configuration of a ferroelectric memory device used in a ferroelectric memory device according to a thirteenth embodiment of the present invention, and multiple hysteresis of the ferroelectric memory device. A diagram showing characteristics and current-voltage characteristics of the ferroelectric memory element;

FIG. 17 is a diagram showing a configuration of a ferroelectric memory device as a 14th embodiment according to the present invention;

FIGS. 18A to 18C show the structure and configuration of a ferroelectric memory device according to a fifteenth embodiment of the present invention, respectively;

FIGS. 19A and 19B are diagrams showing the structure of a ferroelectric memory element used in a ferroelectric memory device as a 16th embodiment according to the present invention;

FIGS. 20A and B show a 17th embodiment according to the present invention, respectively. Figure showing the configuration of the ferroelectric memory element (unit memory cell) used in the ferroelectric memory device of the present invention and the circuit configuration of the entire ferroelectric memory device:

FIGS. 21A and 21B are diagrams each showing an application example to a matrix calculator for multiply-accumulate operation by a ferroelectric memory device according to an eighteenth embodiment of the present invention;

FIGS. 22A and 22B show a circuit example of a conventional MIS element and a hysteresis characteristic of the MIS element, respectively;

Figures 23A and B are diagrams showing a configuration example of a conventional non-destructive storage element and a hysteresis characteristic of the storage element, respectively;

BEST MODE FOR CARRYING OUT THE INVENTION

First, first to tenth embodiments included in the first to second embodiments according to the present invention will be described with reference to FIGS. 1 to 12. FIG. 1 shows a first embodiment according to the present invention. 2 shows a composite hysteresis characteristic of the ferroelectric memory device of FIG. Figure 2 shows the configuration of the ferroelectric capacitor.

The composite hysteresis characteristic shown in FIG. 1 is such that at least one of the areas of the areas facing the formation and arrangement of the first and second electrodes of the strong dielectric capacitor differs as will be described later. This is the combined hysteresis (hereinafter, referred to as twisted hysteresis) characteristic obtained when the above is obtained.

This twisted hysteresis characteristic is due to the Thickness) and ferroelectric capacitors having different areas can be obtained in parallel, and the US patent application USSN 328,110, filed by the present applicant and Japanese Patent Application No. Hei 5-5-2, filed by the present applicant. It is described in detail in No. 6 916, and the explanation is omitted here o

Next, as shown in FIG. 2, the ferroelectric capacitor 1 is provided with a lower electrode 3 made of a conductor below the ferroelectric 2 and an upper electrode 4 having a smaller electrode area than the lower electrode 3. Is provided above the ferroelectric 2.

The thickness d of the ferroelectric material 2 used for the unit memory cell unit arranged in the memory cell array unit of the ferroelectric memory device described later is defined as the area S i of the electrode of the upper electrode 4. Assuming that the diagonal polarization P ₂ is generated in the vertical direction P ₂ , the diagonal polarization P ₂ is generated in the area S ₂ of the dipole P i generated in the area S ₂ having only the lower electrode without the upper electrode 4 and having only one side electrode part. Direction), it becomes P ₂ '. Therefore, it is assumed that the polarization of the memory cell portion is composed of the P i component and the P ₂ ′ component. Figure 1 shows the combined hysteresis characteristics of the polarizations P i and Ρ ₂ '.

That is, when applying an electric field to the ferroelectric capacitor 1 of FIG. 2, the electric field intensity of the area s ₂ parts Nari rather small compared to the field strength of the area S portion, though the coercive field (or thickness) and the area to each other This has the same effect as connecting two different ferroelectric capacitors in parallel, and draws the twisted hysteresis characteristics as shown in Fig.1. Generally, there is a phenomenon called back-switching in the hysteresis characteristic of ferroelectrics. This is, for example, when an electric field larger than the coercive electric field is applied, the polarization is saturated, the array is arranged in the direction of the electric field, and then the intensity of the electric field is returned to zero. When the voltage is applied and returned to zero, it returns to the initial polarization state. A ferroelectric capacitor as shown in Fig. 2 is considered to be the same as connecting two ferroelectric capacitors with different coercive electric fields in parallel, so the medium of the high-speed hysteresis characteristics as shown in Fig. 1 is obtained. Non-destructive reading by the back switching phenomenon becomes possible in two values of the memory state "0" and the memory state "1". However, state "2" in Fig. 1 is not used as information recording.

In FIG. 3, the ferroelectric capacitor 1 is also arranged as a memory cell array as a unit memory cell, and its peripheral circuits are a write circuit 6, a read circuit 7, a switching circuit 8, and a row switching control. FIG. 2 is a block diagram showing a circuit configuration of the entire ferroelectric memory device to which a unit 9 and a column switching control unit 10 are connected.

As shown in FIG. 3, let us consider a matrix memory 5 in which each memory cell has the hysteresis characteristics shown in FIG. First, the writing circuit 6, the row switching control unit 9, and the column switching control unit 10 apply a coercive electric field e _c to each cell of the matrix memory 5 or a writing voltage e larger than e. _{_{_{w [e c '> e m}}} > e £ ( Note re state _{"1"), e ro>} e e' ( Note re state "CT)] polarization direction of the information written to each cell by applying a is It is done. Next, after completing the information writing, the switching circuit 8 is set so that the reading circuit 7 operates. Row et al of the column switching with a control circuit 9, 1 0, large voltage e information of the selected cell Ri by anti electric field e _e. (e _c '>e.> e _c ) and read.

In the combined hysteresis characteristics used in the present invention, the differential dielectric constant (slope of the hysteresis) is significantly different from the applied read voltage at "0" and "1", so that the output current has a large difference. Then, it is possible to determine the state of "1" and "0" and read out the information in a non-destructive manner.

Therefore, not only does a complicated circuit for rewriting lost information by the conventional destructive read-out be required, but also there is little performance degradation due to use, and a long life and a long life. Ru can and child provides performance ferroelectric Note re device _£ Further, the ferroelectric Note Li apparatus similar back-Sui Tutsi in g phenomenon Ri by the on and Mochiiruko binary or more multi It can also be applied to value memory.

Then, the electric field strength of the strong in ferroelectric memory device creation method twisty Dohisuteri cis characteristics utilizing slant polarization as shown in FIG. 2 and c above to describe an area s ₂ portions of the second embodiment, upper electrode It is thought that it decreases rapidly as the distance from Extreme 4 increases. Therefore, it is limited area conditions that can realize the fast hysteresis characteristic.

As an improvement method, the ferroelectric memory device of the second embodiment is as follows. The use of a ferroelectric capacitor formed with the upper electrode as a strip-shaped upper electrode 11 as shown in Fig. 4 adds a portion to which an oblique electric field is applied, resulting in good twisted hysteresis characteristics. I try to make it easier.

Next, a ferroelectric memory device according to a third embodiment will be described. The ferroelectric memory device according to this embodiment has the same dielectric constant ε1, thickness dl, d2, and area SI, S2. Fig. 5 shows a ferroelectric capacitor 1 having a high steered hysteresis characteristic as shown in Fig. 1 and having a different coercive electric field of the structure shown in Fig. 2 or Fig. 4. This is a configuration where they are connected in parallel.

In this configuration, a large difference is generated in the output current by making use of the difference in the differential permittivity during the back switching phenomenon in the memory states “0” and “1” of the high-speed hysteresis characteristic.

, "1" can be extracted nondestructively.

Then, the ferroelectric Note Re device _t this embodiment will be described ferroelectric Note Re device of the fourth embodiment, as shown in FIG. 6, the dielectric constant £ 1, epsilon 2 and area SI, Since S2 is made of a different ferroelectric material, ferroelectric capacitors having different coercive electric fields are connected in parallel. The difference in the differential permittivity during the back switching phenomenon in the memory states "0" and "1" of the twisted hysteresis characteristics as shown in Fig. 1 obtained from such a structure can be used to increase the output current. A difference is created, and the state of "0" and "1" can be read nondestructively. Next, a ferroelectric memory device according to a fifth embodiment will be described. The ferroelectric memory device according to the fifth embodiment includes a ferroelectric capacitor A having symmetric hysteresis characteristics and an asymmetric hysteresis as shown in FIG. 7B. A ferroelectric capacitor B exhibiting cis characteristics is connected in parallel as shown in Fig. 7A. With this configuration, a composite hysteresis characteristic of AZZB can be obtained as shown in FIG. 7B.

As shown in FIG. 7B, in the “0” state, the amount of change in the polarization P at the time of pack switching is larger than that in the “1” state, so that a large output current difference can be generated. "0", "1" state can be read out without blasting.

Then, the ferroelectric Note Re device _t this embodiment will be described ferroelectric Note Re device of the sixth embodiment of the MFMIS having an asymmetric hysteresis characteristic of the laminated structure as shown in FIG. 8A A ferroelectric capacitor is used.

In this ferroelectric capacitor, as shown in FIG. 8A, an insulator film 22, a conductor film 23, a ferroelectric film 24, and a conductor film 25 are sequentially laminated on an n-type semiconductor substrate 21. . The depletion layer of the MIS type capacitor (21, 22, 23) composed of the lower three layers is controlled by the direction of polarization of the ferroelectric 24. With this effect, an asymmetric hysteresis characteristic as shown in FIG. 8B is obtained.

FIG. 8C shows that the MIS type capacitor composed of the conductor film 23, the insulator film 22, and the semiconductor substrate 21 is a dielectric film 23, a ferroelectric film. Shows that with different sizes of C _G, C j by the depolarization of "1" - the body layer 24, a conductor film 2 5 ferroelectric Kiyapashi evening polarization state P = "◦" and P I have. Since the MIS type capacitor having this different value is connected in series with the ferroelectric capacitor 'as shown in Fig. 8D, when P = "0", it shows an equivalently large capacitance. Thus, when P = "1", the capacitance is small. Therefore, an asymmetric hysteresis characteristic as shown in FIG. 8B can be obtained.

Next, a ferroelectric memory device according to a seventh embodiment will be described. The ferroelectric memory device according to the seventh embodiment has a MFMIS-type ferroelectric memory having an asymmetric hysteresis characteristic of a laminated structure as shown in FIG. 9A. A body capacitor is used.

In this ferroelectric capacitor, an insulator thin film 27 (Sio), a ferroelectric film 28, and an upper electrode 29 are sequentially formed on an n-type semiconductor substrate 26. Here, the thickness of the depletion layer on the surface of the n-type semiconductor substrate 26 is controlled by the direction of polarization of the ferroelectric film 28. Because I Ri insulator film 2 7 thickness thereto is changed equivalently, the asymmetric hysteresis characteristic shown in FIG. 9 B obtained _£ Then, ferroelectric Note Re apparatus of the eighth embodiment ferroelectric memory device of _c explaining this embodiment uses a ferroelectric capacitor formed in parallel form laterally stacked structure as shown in FIG. 1 0. In these ferroelectric capacitors, an n-type well region 39 is formed on a P-type semiconductor (Si) substrate 31 and an insulating film 32, a lower electrode 33, a ferroelectric film 34, A unit A having a plurality of asymmetric capacitors formed by an upper electrode 35, a lower electrode 33, a ferroelectric film 38 and an upper electrode 35 on the P-type semiconductor substrate 31. A unit B having a plurality of capacitors having symmetrical hysteresis characteristics is formed.

Here, it is assumed that the ferroelectric film 34 included in the unit A has a coercive electric field different from that of the ferroelectric film 38 of the unit B. By arbitrarily connecting these units and unit B by using the wiring electrode 37, a ferroelectric capacitor having desired desired hysteresis characteristics can be obtained.

Then, the ferroelectric Note Re apparatus of the ninth embodiment of the ferroelectric Note for Li apparatus illustrating _£ this embodiment is formed in parallel form laterally stacked structure as shown in FIG. 1 1 Use a ferroelectric capacitor.

In these ferroelectric capacitors, as shown in FIG. 11, an insulating film 42 is formed on a semiconductor substrate 41, and a lower electrode 43 is further formed. Thereafter, a desired portion of the lower electrode 43 is etched to form a thin portion.

A ferroelectric film 44 is formed on the lower electrode so as to have a flat surface by using the Spin On technology, and an upper electrode 46 is further formed. Here, the lower electrode 43 is formed on the thick part. Although the description has been given based on the first to tenth embodiments, the invention according to the first and second aspects of the present invention includes the following ferroelectric memory device. And

(1) A first electrode formed of a conductive film formed on a substrate, a ferroelectric film formed on the first electrode to which information is written, and a conductive film formed on the ferroelectric film A ferroelectric capacitor comprising a plurality of second electrodes comprising a first electrode and a second electrode, wherein at least one of the formation arrangement of the first electrode and the second electrode is different from the size of the facing electrode area. Ferroelectric memory device.

Therefore, according to the ferroelectric memory device of (1), the first electrode and the second electrode of the ferroelectric capacitor can be formed by changing the arrangement relationship or the size of the opposing electrode area. Since the twisted hysteresis characteristic is obtained, information can be read nondestructively using the twisted hysteresis characteristic.

(2) The ferroelectric memory device according to (1), wherein the shape of at least one of the first electrode and the second electrode is changed. apparatus.

Therefore, according to the ferroelectric capacitor of (2), at least one of the first and second electrodes is changed in shape to increase the area of the portion to which the oblique electric field is applied. As a result, good twisted hysteresis characteristics can be easily obtained.

(3) In the ferroelectric memory device described in (1) or (2) and a plurality of ferroelectric capacitors connected in parallel, 1 9

The plurality of capacitor units A thus formed have a smaller coercive electric field because the ferroelectric film 44 has a smaller film thickness than the plurality of capacitor units B formed in the portion where the lower electrode 43 is thin.

In this way, the capacitor units A and B having different coercive electric fields are arbitrarily connected using the wiring electrode 47, and a ferroelectric capacitor having a desired twisted-state hysteresis characteristic is obtained.o

Next, the ferroelectric memory device of the tenth embodiment will be described.

The ferroelectric memory device of the present embodiment uses a ferroelectric capacitor formed in a vertically-parallel manner with a laminated structure as shown in FIG.

In this ferroelectric capacitor, as shown in FIG. 12, an insulating film 52 is formed on a semiconductor substrate 51, and three layers of a lower electrode 53, a ferroelectric film 54, and an upper electrode 55 are further formed. A unit B composed of a plurality of capacitors having a structure, and an interlayer insulating film 56 formed on the unit B, a lower electrode 57, a ferroelectric 58, and an upper electrode 5 9 and a unit A composed of a plurality of capacitors composed of nine capacitors.

In these Units A and B, two ferroelectric capacitors whose coercive fields are more than three times different from each other are formed by using different materials or changing the film thickness with the same material. can do. The capacitors of unit A and unit B are arbitrarily connected using wiring electrode 60, and a ferroelectric capacitor having desired characteristics can be obtained. Are characterized in that the values of the coercive electric fields are different from each other, and the capacitance of the ferroelectric capacitor at the time of back switching in several polarization states of the twisted hysteresis. A ferroelectric memory device characterized in that the polarization state is read out nondestructively by using a method.

Therefore, according to the ferroelectric memory device of (3), the plurality of ferroelectric capacitors have different values of the coercive electric field of the ferroelectrics, and can be obtained with respect to those ferroelectric capacitors. The polarization state can be read out nondestructively by utilizing the capacitance difference at the time of back switching in some polarization states of the distant hysteresis characteristics.

(4) In the above (3), when back-switching in several polarization states of the switched hysteresis obtained in a memory element in which ferroelectric capacitors having different relative dielectric constants are connected in parallel. A ferroelectric memory device characterized by a non-destructive readout method utilizing a capacitance difference between the two.

Therefore, according to the ferroelectric memory device of (4), the ferroelectric capacitors having different coercive fields are formed by connecting materials having different relative dielectric constants in parallel to each other, thereby obtaining a high-speed hysteresis. A memory device with characteristics is configured, and the polarization state can be read out nondestructively by utilizing the capacitance difference during back-switching of some polarization states of the twisted hysteresis characteristics.o

(5) In the above (3) or (4), at least one or more ferroelectric capacitors among the plurality of ferroelectric capacitors connected in parallel. A ferroelectric memory device, wherein the electric capacitor has an asymmetric hysteresis.

Therefore, according to the ferroelectric memory device of (5), at least one of the plurality of ferroelectric capacitors connected in parallel has asymmetric hysteresis characteristics, The polarization state can be read nondestructively by utilizing the capacitance difference at the time of switching of the twisted hysteresis characteristics.

Therefore, according to the ferroelectric memory device having the configuration of (1) to (5), the memory state can be read nondestructively by applying the read drive voltage under an electric field larger than the coercive electric field. In addition, high density is possible due to large SZN.

(6) The ferroelectric capacitor having an asymmetric hysteresis according to the above (5), wherein the ferroelectric memory device has a multilayer structure of a conductor, a ferroelectric, an insulator, and a semiconductor. Therefore, according to the ferroelectric memory device of (6), the ferroelectric capacitor having the asymmetric hysteresis characteristic described in (5) is a multilayer film structure of a conductor, a ferroelectric, an insulator, and a semiconductor. It consists of.

(7) The ferroelectric capacitor having asymmetric hysteresis according to (5), wherein the ferroelectric memory device has a multilayer structure of a conductor, a ferroelectric, a conductor, an insulator, and a semiconductor. . Therefore, according to the ferroelectric memory device of (7), the ferroelectric capacitor having the asymmetric hysteresis characteristic described in (5) can be a conductor, a ferroelectric, a conductor, an insulator, It has a multi-layer structure of semiconductor.

Therefore, according to the ferroelectric memory device having the above constitutions (6) and (7), the twisted hysteresis characteristic for realizing the non-destructive read ferroelectric memory having a large SZN can be easily obtained. Will be obtained.

(8) A unit ferroelectric capacitor comprising a lower electrode film formed on an insulator, a ferroelectric film formed on the lower electrode film, and an upper electrode film formed on the ferroelectric film A plurality of first capacitor units are formed on the insulator, and a plurality of second capacitor units having different coercive electric fields from the first capacity unit are formed on the insulator. Forming a capacitor unit; a second capacitor unit having a lower electrode newly formed on the insulator, a ferroelectric film formed on the lower electrode, and a lower electrode formed on the ferroelectric film; And a unit ferroelectric capacitor having an upper electrode having a shape different from that of the first and second capacitor units, wherein at least one of the first and second capacitor units is electrically connected. Dielectric memory device.

Therefore, according to the ferroelectric memory device of (8), when an electric field is applied to the ferroelectric capacitor, the electric field strength of the second electrode area becomes smaller than that of the first electrode area. The ferroelectric capacitor has a smaller area and a different coercive field (or film thickness) and area. This has the same effect as connecting a capacitor in parallel, and a twisted hysteresis characteristic is obtained. The binary state of the memory state "0" and the memory state -1 of this twisted hysteresis characteristic is obtained. In, information stored by the back switching phenomenon can be read out nondestructively.

(9) The ferroelectric material according to (8), wherein the ferroelectric materials of the plurality of first ferroelectric capacitor units and the plurality of second ferroelectric capacitor units are different. Therefore, according to the ferroelectric memory device of (9), the ferroelectric material of the first ferroelectric capacitor unit is different from that of the second ferroelectric capacitor unit. Thus, a ferroelectric capacitor having a different coercive electric field and a twisted hysteresis characteristic is formed, and by utilizing the capacitance difference at the time of back switching in several polarization states of the twisted hysteresis characteristic, The polarization state can be read out nondestructively.

(10) The ferroelectric memory device according to (8), wherein the thicknesses of the ferroelectrics of the plurality of ferroelectric capacitor units A and the plurality of ferroelectric capacitor units B are different.

Therefore, according to the (10) ferroelectric memory device, the coercive electric field is different due to the different ferroelectric thicknesses of the plurality of first and second ferroelectric capacitor units, and the twisty field is different. A ferroelectric capacitor having a dehysteresis characteristic is formed.

(11) In the above (8), the plurality of ferroelectric capacitor units A having different coercive electric fields from the plurality of ferroelectric capacitor units A A ferroelectric memory device characterized by stacking B to form a three-dimensional structure.

Therefore, according to the ferroelectric memory device of (11), the first ferroelectric capacitor unit and the second ferroelectric capacitor unit having different coercive electric fields are laminated and formed three-dimensionally. It is composed.

Therefore, the ferroelectric memory device of (11) is capable of electrically connecting a plurality of ferroelectric capacitor units having different coercive electric fields to provide a ferroelectric device having a desired twisted hysteresis characteristic. Capacitors can be obtained.

(12) A first unit formed by arranging a plurality of first unit ferroelectric capacitors each having a laminated structure of a lower electrode film, a ferroelectric film, and an upper electrode film sequentially formed on an insulator. Capacitor unit and

A second capacitor unit having the same laminated structure as the first unit ferroelectric capacitor and having a plurality of second unit ferroelectric capacitors having different coercive electric fields arranged on the insulator; (1) A ferroelectric device characterized in that at least one unit ferroelectric capacitor in each of the capacitor unit and at least one unit ferroelectric capacitor in the second capacitor unit has a storage medium electrically connected in series or in parallel. Body memory device.

As described in detail above, according to the first to tenth embodiments of the present invention, the stored information can be read out nondestructively, and the ferroelectric memory having a long life and suitable for integration is provided. Providing equipment Can be.

Further, according to these embodiments, it is possible to form a ferroelectric capacitor having a twisted hysteresis characteristic for realizing the non-destructive read ferroelectric memory device having a large SZN. By electrically connecting a plurality of ferroelectric capacitor units having different coercive electric fields, a ferroelectric capacitor having desired twisted hysteresis characteristics can be formed.

Therefore, according to the first and second aspects of the present invention, not only a complicated circuit for rewriting the information lost by the burst reading as in the related art is unnecessary, but also It is possible to provide a long-life, high-performance ferroelectric memory device with little performance deterioration due to use during use. The ferroelectric memory devices of the first and second embodiments can be applied to multi-valued memory of two or more values by using the same back switching phenomenon in two or more values. .

Next, the eleventh to eighteenth embodiments included in the third aspect of the present invention will be described with reference to FIGS. 13A, B, and C to FIGS. 21A and 21B.

With reference to FIGS. 13A, 13B and 13C, the multi-hysteresis characteristic of the ferroelectric memory element used in the ferroelectric memory device according to the first embodiment of the present invention will be described.

Figure 13A shows the twisted hysteresis characteristic of the ferroelectric used in the ferroelectric memory device, that is, the multiple hysteresis characteristic. Inflection points are shown, and two inflection points are shown for a negative electric field. An example of this ferroelectric memory element will be described below.

14A to 14H are diagrams showing the multi-hysteresis characteristic and the spontaneous polarization. Ferroelectric having multiple hysteresis characteristics Equivalently, considered parallel connection of C _FE L OW showing the C _FE H IgH and low coercive field characteristics showing a high coercive electric field characteristics.

Here, in the state of each shown in FIG. 14 A to 14 H, state 1. CH ih, C _FE L OW both spontaneous polarization P _h in the same direction, with P _L (FIG. 14 A, B).

State 2. C _FE High shows the same P _h as in State 1, and only C _FE L OW is in a state of P _L due to polarization inversion. The whole, just when the IP _h I = IP _L I, the spontaneous polarization is zero (FIG. 14 C, D).

State 3. It has a spontaneous polarization of 1 P _h and 1 P _L , which is the exact opposite of state 1 (Figs. 14E, F).

State 4. There are spontaneous polarizations P _H and PL opposite to State 2, but they are all 0 as in State 2 (Fig. 14G, H). Here, the strong point having the multiple hysteresis characteristic is obtained. Consider a memory element having the configuration shown in Fig. 13B using a dielectric.

In general, a circuit configuration in which a ferroelectric capacitor is directly connected to a dielectric capacitor is used to measure the amount of charge associated with the polarization reversal of the ferroelectric (Soyer-tower method). In other words, the soy tower method uses the dielectric capacity to transfer the charge associated with the polarization reversal. This is a method of transferring the data to a computer for observation. At this time, the electric charge stored in the ferroelectric capacitor and the dielectric capacitor is free, and due to the leakage resistance, the charge gradually decreases to zero regardless of the presence or absence of spontaneous polarization of the ferroelectric.

In Fig. 13B, the state of ferroelectric capacitor ( _CF ) 11 is assumed to be at the position of Pi (state 1) shown in Fig. 14A. However, electric charge is stored in the capacitor. Shall not be. With terminal 15 grounded, apply a voltage from terminal 14 to invert only spontaneous polarization PL, and then ground terminal 14. Inversion charge QL generated upon reversing the spontaneous polarization P _T gar PL are accumulated in the dielectric capacitor _{(C) 1 2, V L} = Q L / C becomes generates potential (spontaneous at this The polarization is in the P _Qp state 2).

Further, from this state, after the P _h from the terminal 1 4 is applied a voltage which can be reversed, to ground the terminal 1 4 again. Here, P _h

P _h and the spontaneous polarization is P. (State 3). It is clear that the charge Q associated with this inversion is the same size as QL.

_{_{Therefore, V H = (Q L +}} Q H) ZC becomes, V _H = 2 V, is.

These _P}, at P ₀ p _f in state P _2, the dielectric Canon Bruno. The potentials of the capacitor (C) 12 are 0 (V), _VL (V), and 2 _VL (v), respectively, indicating that three values are stored for the capacitor (C) 12. . Is the above dielectric Capacity evening material _{_{_{P b y S r} _ y}}} (T i x Z r j_ x) 0 3 or _{_{_{P b y C ai. Y (}}} T i χ Z τ _ τ) 0 3 or P by B a ^ y (T i x Z r 1 _ Σ) high dielectric material having a 0 ₃ chemical group Narushiki are preferred.

In this chemical composition formula, X represents a composition ratio and ranges from 0.2 to 1.0, and y represents a composition ratio and ranges from 0.85 to 1.0.

Next, data reading from such a ferroelectric memory device will be described. 1 3 voltage-current conversion element 1 3 shown in B is has a good UNA characteristic of FIG. 1 3 C, 0. 7 when the (m A), when the _{2 V L 1. 4 (m A} ) Is shown. Here, when the terminal 17 in FIG. 13B is grounded, a voltage is applied between the terminal 17 and the terminal 18. At this time, current flowing from the power source upon application of a predetermined voltage (V _RE _AD) to the terminals 1 6 to the terminal 1 6 each P j, P _0p, to _{P 2, 0 (A),} 0. 7 ( m A), 1.4 (m A). Therefore, the ternary state can be determined by detecting these currents.

When erasing the memory of the ferroelectric memory element, apply a negative voltage large enough to invert PH and _-PL from terminal 14 with terminal 15 grounded, Change state back to P i. After that, the terminals 14 and 18 are grounded to discharge the free charges, and the accumulated charges in the ferroelectric capacitors 11 and 12 are set to 0.

Next, a ferroelectric memory element included in a ferroelectric memory device according to a 12th embodiment of the present invention will be described. This ferroelectric memory element is configured as shown in FIG. 15A using the multi-hysteresis ferroelectric capacitor described above. Here, in order to facilitate understanding of this embodiment, FIG. Referring to A and B, we clarify the relationship between spontaneous polarization and memory voltage.

Uni ferroelectric Note Li element by shown in FIG. 23 A is strongly dielectric key Yapashita (C _FE) 206, and Soiya Tower circuit consisting of series connection of the dielectric capacitor) 20 7, a ferroelectric capacitor (C _FE ) Charge-effect transistor (n Type MO SFET) 209 controlled by charge stored in dielectric capacitor (CL) 207 according to polarization change of 206, and dielectric capacitor (C j ^) 207 and a resistance element 208 connected in parallel.

Here, in the memory element shown in FIG. 22A including a normal soy tower and a field-effect transistor (n type MOS FET) 209, a voltage signal is input from the input terminal 204, and the memory is input. Write operation to.

At this time, the voltage applied to the ferroelectric capacitor (C _Fr ) 201 is applied to the V _F dielectric capacitor (C,) 202 by polarization of the ferroelectric capacitor (C _FE ) 201. the pressure V _e, and to those graphed is a hysteresis Li cis characteristics shown in FIG. 22 B.

It is obvious that when the write operation is completed and the input terminal 204 is set to 0 V, that is, the values of V _FE and V in the memory holding state indicate M j and M ₀ , respectively. In this state, paying attention to M _} , this is the result of polarization by applying a positive voltage to the ferroelectric C _FE . In the state of, the negative voltage opposite to the applied positive voltage is c _FE It shows that it is held where the voltage is applied to both ends of.

This is the same as the fact that the ferroelectric substance has its own polarization canceled out by the excess charge generated when the polarization is reversed, and apparently reverses the polarization.

Therefore, in FIG. 23A, by providing the resistive element 208, the above-described excess charge is removed, and the holding state is the same as the direction of the voltage applied during polarization, as shown in the hysteresis characteristic shown in FIG. 23B. Has been obtained.

By the way, the second embodiment has the configuration shown in FIG. 15A, and the ferroelectric capacitor (C _FE ) 206 of FIG. 23 A is changed to a multi-hysteresis ferroelectric capacitor (C _FE ) 31. It is the structure which did. The multi-hysteresis ferroelectric capacitor ( _cFE ) used here

Since 31 has the hysteresis characteristics shown in FIGS. 14A to 14H, the state 1 (P ₁ ) shown in FIGS. 14A and 14B and the state shown in FIGS. A voltage signal V _M (V), 0 (V), as shown in FIG. 15B corresponding to the state 2 or 4 (P ₀ ) shown in H and the state 3 (P ₂ ) shown in FIGS. + v _M (V).

Since the voltage-to-current converter 24 of FIG. 15A shows the voltage-to-current conversion characteristics shown in FIG. 15B, the retained information is O mA, 1.5 mA, and 3 mA, respectively. Determine the current flowing through 24 Can be detected.

Next, a ferroelectric memory element constituting a ferroelectric memory device according to a thirteenth embodiment of the present invention will be described with reference to FIGS. 16A, 16B and 16C.

First, in a state where the grounding terminal 3 8 shown in FIG. 1 6 A, the amplitude V _p _p = 2 V. from terminal 3 7 Figure 16B shows the relationship between the voltage V _FE across the ferroelectric capacitor (C _FE ) 31 and the voltage V across the dielectric capacitor (CL) ₃₂ when a sinusoidal voltage is applied.

This ferroelectric memory element is in the memorized state when the terminal 37 is grounded after the above-mentioned sine wave voltage is applied, and in the state of spontaneous polarization P, v _MP1 (V _pP =-v _CL ) , in the state of P _h, V

^{00 for} MP2 (one V FE ⁼ V CL)

In addition, in the state of ^V MP2, when a voltage that decreases to −37 is applied to terminal 37, when terminal 37 is grounded, or in the state of V _{MP I} , the voltage rises to Vi at terminal 37. after application of a voltage, when the ground terminal 3 7, and each _{_{V MP o (V FE = V}} CL = 0).

In this way, in between the terminals 3 8, 3 7 shown in FIG. _{1 6 A,, V MP I} , V MPO by applying ± v ₂ becomes the magnitude of the sinusoidal voltage (or pulse), 3 V _MP2 Remember two states a [

The characteristics of the voltage-current conversion elements 33 and 34 used for reading are as shown in Fig. 16C with respect to the voltage between terminals 40 and 35 or the voltage between terminals 39 and 35. Is shown. Reading in the ferroelectric memory element of this embodiment is performed by connecting the terminals 37 and 38 to ground, connecting the terminal 39 to a positive power supply, and connecting the terminal 40 to a negative power supply. In this case, the voltage-current conversion element 33 is a p-type MOS transistor, and the voltage-current conversion element 34 is an n-type MOS transistor.

Here, the read element composed of the voltage-current conversion element 33 and the voltage-current conversion element 34 has a terminal 39 connected to the positive power supply and a terminal 40 connected to the negative power supply. It is assumed that the relationship between the current I flowing from the terminal 36 and the potential V of 35 is set as shown in FIG. 16C.

Then, with the ground terminal 3 8 in FIG. 1 6 A, the C _Fr 3 1, C _L 3 2 each raw sly voltage waveforms when applying the terminal 3 7 good Ri sinusoidal voltage, FIG 6 As shown in B.

When the terminal ₃₇ becomes 0 (V), that is, in the holding state in the memory, three values of V _MpQ , V _Mpi , and V _Mp2 are obtained. In ^{^{^{here, V MPG 'V MP1' V}}} MP2 C L 3 2 voltage across V _CL of which corresponds to each _{0 (V), - V M} (V), a + v _M (V).

From this, it is clear that the potential of the terminal 35 in FIG. 16A is + V ,,, 0, —v _M depending on the storage state.

In addition, since the characteristics of the voltage-current conversion elements 33 and 34 in the readout section are as shown in FIG. 16C, +1 _M for + V _M , O mA for 0 V, and + V for 1 V _M Since a current of 1 mA flows from terminal 36, if this is detected with an appropriate configuration, it will be stored. The contents can be read.

For example, if a resistor is connected in series with the output terminal 36, the potential difference between both ends of this resistor must be measured according to the Ohm's law of V = I * R (V: potential difference, I: current, R: resistance). It is possible to easily convert current to voltage and read it out.

For example, if the resistor is lk Ω and the storage state is + V _M , a current of -1 mA flows from the output terminal 36, so that the potential difference of --IV can be detected and At v _M , the potential difference is + IV. When the storage state is 0, a potential difference of 0 V can be detected.

Next, a ferroelectric memory device as a fourteenth embodiment of the present invention will be described with reference to FIG.

The ferroelectric memory device according to this embodiment includes a ferroelectric capacitor 41 having a multi-history characteristic, a dielectric capacitor 42 arranged in series with the ferroelectric capacitor 41, and a dielectric capacitor 42. And a reading circuit including voltage-to-current conversion elements 44 and 45. The multi-hysteresis characteristics of this ferroelectric capacitor are assumed to be the same as the characteristics shown in FIGS. 14A to 14H.

With the terminal 47 shown in FIG. 17 grounded, a positive voltage is applied from the terminal 46 to obtain the state 3 (spontaneous polarization P ₂ ) shown in FIGS. 14E and F. Thereafter, when the ground terminal 4 6, multiple hysteresis ferroelectric capacitor (C _F r) 4 1, ferroelectric capacitor (C _L) 4 2, resistance (R) 4 3 becomes equivalently connected in parallel, A voltage V _p2 corresponding to the polarization P 2 is held between the terminals _{47 and 50} . The voltage V _p2 is such that the terminal ₅₀ appears as a negative potential with respect to the terminal 47 and has an electric field in the same direction as the polarization P ₂ . Therefore, one V _p as long as P ₂ is held and retained.

Similarly, the voltage between the terminals 46 and 47 is controlled to be in the state 1 (polarization Pi) shown in FIGS. 14A and 14B. Then, the voltage v _P1 is held as a voltage of the opposite polarity to the voltage v _p2 . The power supply for writing has both positive and negative polarities, and the magnitude is arbitrarily controlled. In addition, in the cases corresponding to the states 2 and 4 shown in Figs. 14C and D and 14G and H, since ρ = p, v _pQP = V p _0h = 0 and the potential state is distinguished. Can not. '

As described above, this memory element can obtain V _pi , 0, V p ₂ (= −V _ρι ) as a storage voltage according to the polarization state. In the read circuit composed of the voltage-current elements 44 and 45, a positive power supply is connected to the terminal 4S, a negative power supply is connected to the terminal 49, and the potential of the terminal 50 changes from negative to positive with respect to the ground. Then, the characteristics shown in FIG. 16C are shown.

Here, assuming that the storage voltage V _p2 = — V _M , V _pi = V _M (FIG. 16B), since the voltage V _P1 is stored in the polarization P i, one milliamperes from the output terminal 51. current flows in a current of 1 m a flows when the polarization P _2, when the polarization 0, 0 m a than the current, can be read to determine them.

Next, referring to FIGS. 18A, B and C, the fifteenth embodiment according to the present invention will be described. An example of a ferroelectric memory device will be described.

The ferroelectric memory device of this embodiment includes a ferroelectric capacitor 61, a dielectric capacitor 62, a resistor 63, a p-type MOS, and a n-type MOS formed on a silicon (Si) substrate. Voltage-to-current conversion elements 64 and 65 each formed of a MOS transistor.

In FIG. 18C, 66 is an input terminal, 67 is an output terminal, 68 is a positive power supply terminal, and 69 is a negative power supply terminal.

As described above, in the p-type MOS transistor, when a negative voltage is applied to the gate (G), the source (S) and the drain (D) become conductive. In addition, in the n-type MOS transistor, when a positive potential is applied to the gate (G), a conduction state is established between the source (S) and the drain (D). '

Therefore, the voltage-current conversion characteristics as shown in FIG. 16C can be realized by performing the electrical wiring shown in FIG. 18C using the p-M0S, n-MOS transistor.

In addition, the M0S type transistor is a field-effect type transistor, in which 0 N and 0 FF control of the transistor is performed by an electric field, and current injection is required as in a bipolar type transistor. do not do.

Therefore, when a potential corresponding to the charge stored in the dielectric capacitor 62 is replaced with a current and detected, the detection can be performed without reducing the charge, and a long-term storage is possible.

Next, a ferroelectric memory element used in a ferroelectric memory device according to a sixteenth embodiment of the present invention will be described with reference to FIGS. 19A and 19B. A parasitic capacitance called Ces is generated between the terminal ₇₂ and the terminal 71 shown in FIG. 19A. This is a parasitic capacitance formed between the PO 1 y Si gate electrode and the P + diffusion layer (source) by using the gate oxide film Si 0 ₂ as a dielectric. It depends on the thickness d of the oxide film and the overlapped area S of the P o 1 y Si gate electrode and the P + diffusion layer (source). In other words,

C = ε * £ 0 * S / d (ε: relative permittivity, ε ϋ: permittivity, S area, d: thickness) is becoming more important.

Therefore, if the overlap area S is increased, the capacitance value is increased. Also, if the thickness d is reduced, the capacitance value also increases.

Therefore, it is possible to provide an arbitrary capacitance ratio to a ferroelectric having multiple hysteresis characteristics connected in series to the gate electrode by controlling the area and the thickness.

In this embodiment, the ferroelectric material having a multi-hysteresis characteristic

A device was created by controlling only the overlap area so as to have a value 10 times the capacitance value near the V bias.

Also, in the device created this time, a resistor element is made by separately providing a resistor made of Po1ySi between terminal 71 and terminal 72.

Note that the ^memory element according to the present invention ^{accesses the memory for} 10 to ⁸ sec, and the capacitance of the charge holding capacitor is set to lxl CT ¹³ (F). The resistance created by was set to 5 × 10 ⁴ Ω.

Next, referring to FIG. 2 OA and B, a 17th embodiment according to the present invention will be described. A ferroelectric memory device as an example and a ferroelectric memory element used in the ferroelectric memory device will be described.

FIG. 2OA shows the configuration of a ferroelectric memory element (unit memory cell) used in the ferroelectric memory device of this embodiment. FIG. 20B shows a ferroelectric memory device configured using this ferroelectric memory element.

In this embodiment, two unit memory cells are used for ease of explanation. However, the present invention is not limited to this, and a matrix structure in which many memory cells are arranged is used. Of course, it is preferable.

The ferroelectric memory element (unit memory cell) shown in FIG. 20A is the same as the ferroelectric memory element shown in FIG. 13B, and detailed description is omitted here. .

The ferroelectric memory device shown in FIG. 20B has two ferroelectric memory elements 81, 1 (hereinafter, referred to as cells 1 and 2) and a write-in device for selecting a cell into which data is to be written. Address decoder 101, bipolar write power supply for writing multi-valued polarization during writing (voltage magnitude varies according to information to be written) 103, read for selecting cell from which data is read It comprises an address decoder 1-2, a read current detection circuit 106 for detecting read current and discriminating information, and a read / write (RZW) control circuit 105.

In such a configuration, when data is written to the cell 1 or 2, the transistor 84 (W—SW 1) or 94 becomes conductive by the write address decoder 101, A bipolar write power supply 103 is connected. The transistor 85 (W-SW2) or 95 is controlled by the RZW control circuit 105 so that the transistor 85 (W-SW2) or 95 is always conducted except when reading and is grounded. Therefore, at the time of writing, one of the cell sides is grounded. Here, a voltage pulse having a magnitude and polarity corresponding to the information to be written is applied from the bipolar write power supply 103, and then grounded.

When writing is not being performed, the transistor switch 82 (SW1) or 92 is always connected to the cell transistor 84 (W-SW1) or 94 via the inverter 83 or 92. The grounded part is grounded (when storing and reading out the memory).

Next, reading in the ferroelectric memory device thus configured will be described.

First, the read address decoder 102 turns on the transistor 86 (R-SW2) or 96, and the cell is connected to the read power supply 104. At the same time, the transistor 85 (W-SW2) or 95 is turned off (off) by the RZW control circuit 105.

Therefore, the current flowing from the read power supply 104 to the cell 1 or 2 has a value determined by the polarization state of the cell, and this current flows into the read current detection circuit 106. Here, the characteristics of the voltage-to-current conversion element of the cell are the characteristics shown in FIG. 15B, and the multiple hysteresis characteristics are those shown in FIGS. 14A to 14H. Figure 14 A, shown in B, memory voltage polarization state P j of the polarization state of the state 1 is the V _M in FIG. 1 5 B, the polarization state P ₂ in the state 3 shown FIG. 14 E, the F the Note Li voltage at the time of FIG. 1 5 B - a V _M. In addition, it shows 0 V in a state equivalent to states 2 and 4 shown in Figs. 14C and 14D and Figs. 14G and 14H.

Therefore, the read current detection circuit 106 detects 3 mA for polarization P i, O mA for P _2, and 1.5 mA for 0 V (P = 0). , Judge and output.

Next, an application example of the ferroelectric memory device according to the eighteenth embodiment of the present invention to a matrix calculator for sum-of-products calculation will be described.

Here, the memory cells M11 to M33 shown in FIG. 21A correspond to the ferroelectric memory element shown in FIG. 17 of the fourteenth embodiment described above. Further, in this embodiment, the arrangement of three rows and three columns is adopted in order to make the explanation easy to understand, but the present invention is not limited to this.

In the matrix calculator for multiply-accumulate operation, memory cells M11 to M33 are arranged in a matrix, and switches S1 to S3 are provided for each row.

With reference to FIG. 21B, the input / output characteristics of the memory element used in the cells M11 to M33 will be described.

First, when the nonvolatile memory voltage 0 V is stored in the dielectric capacitor 42 (see FIG. 17), the current output from the memory element is 0 A. Next, when the nonvolatile memory voltage 0.8 V is stored in the dielectric capacitor 42, If the current of 500 / iA and 10.8 V are stored, the current of 500 A is output from the output terminal 51 (see FIG. 17).

As described above, the outputs from the respective memory elements of Ml1 to M33 are shown in FIGS.

The sum of each column is collected by 3 and detected by the ammeters 1 1 1 2 and 1 1 3.

Now consider the following matrix operation

1 0-1

(1, 0, 1) 0 1 1 0 = (0, 1 1 2)

One one

(1) The above calculation is actually performed by the calculation units shown in Figs.

First, the information of (1.0.1) is given to the switches SI, S2, and S3 as ON, OFF, and ON.

Then, 1 0 — 1

0-1 0

One 1 one one 1

Of the cell Ml 1 to M 33 as shown below.

0 8 V 0 V-0.8 V

0 V-0.8 V 0 V

-0.8 V 0.8 V-0.8 V

And give it.

At this time, the output value of each of the ammeters 1 and 2 Becomes OA, 50011A, -mA. Dividing this value by the absolute value of the output current from the unit memory cell, 500 A, gives (0, 1, -2), which matches the right side of equation (1).

By expanding this to n dimensions, an n-dimensional matrix operation circuit can be constructed. In addition, as can be seen from such an operation, since it is a parallel operation unit, a very high-speed product-sum operation unit can be realized.

In the ferroelectric memory devices according to the eleventh to eighteenth embodiments of the present invention, various effects can be obtained by the configurations described below.

(1) A ferroelectric material that has multi-hysteresis characteristics with at least three or more stable polarization values and stores multi-valued voltages associated with the multi-hysteresis characteristics as information A ferroelectric capacitor formed between materials,

A dielectric capacitor connected in series to the ferroelectric capacitor;

A voltage-current conversion element for reading multi-valued voltage information associated with the multiple hysteresis characteristics stored in the ferroelectric capacitor;

Ferroelectric memory device composed of

Since the ferroelectric memory device of (1) has three or more stable polarization values, three or more pieces of voltage information stored when the polarization state changes can be obtained.

As a result, the information that can be stored in a normal ferroelectric memory device is binary, but the ferroelectric memory device of the present invention has a multi-layered structure. By using a ferroelectric material having a steeresis characteristic, three or more values can be stored. Also, by using a voltage-to-current conversion element instead of an ON-OFF switch as the readout element, multi-valued storage and multi-valued read-out are possible.

(2) A ferroelectric capacitor having multiple hysteresis characteristics having at least three or more stable polarization values,

A dielectric capacitor connected in series with the ferroelectric capacitor;

A ferroelectric element capable of multi-value storage, comprising: a resistance element connected in parallel to the ferroelectric capacitor; Body memory device.

(3) The voltage-current conversion element according to (2) is connected to a continuous portion between the ferroelectric capacitor and the dielectric capacitor.

Since the ferroelectric memory devices of (2) and (3) have three or more stable polarization values, three or more pieces of voltage information corresponding to the polarization state can be obtained. Since voltage information can be directly stored, long-term memory is possible, and multi-value storage of three or more values is possible.

(4) In the ferroelectric memory device described in (1) or (2) above, the voltage-current conversion element for reading multi-valued voltage information is an element whose current is controlled with respect to a positive voltage. And an element whose current is controlled with respect to a negative voltage.

Conventionally, depending on the stored information, a positive or negative current Although it is a ferroelectric memory element that outputs current, it can handle only a small number of stored information. The ferroelectric memory device according to the present invention of (4) is a storage element capable of storing and reading out multi-valued information of three or more values. Since conversion is possible, voltage information corresponding to the polarization state can be stored for a long period of time in both polarities, and multi-value reading of the information voltage is possible.

(5) The voltage-current conversion element described in the above (3) or (4) is constituted by a MOS type transistor.

The ferroelectric memory device according to the present invention of (5) is realized as a conventional multi-valued memory S i device (not realized by a device). A ferroelectric memory device can be created in monolithic on a substrate.

(6) above (2), (4), wherein the dielectric capacitor, a gate capacitance of M 0 ST _r, the resistance element is made of polycrystalline silicon.

The ferroelectric memory device according to the present invention (6) uses a resistive element technology using a top-down silicon to provide an unprecedented multi-value storage memory element. The structure for realizing such a ferroelectric memory device is simplified, and a separate dielectric capacitor is manufactured by using the gate capacitance of the MOS transistor as a dielectric capacitor. There is no need to use a resistor, and the resistive element is made of polysilicon, which is usually used in the Si process, to prevent the process from becoming complicated. (7) In the ferroelectric memory device described in (1) or (2) above, a plurality of ferroelectric memory elements are arranged, a desired memory element is selected, and writing / reading is performed. Have means to do.

Such a ferroelectric memory device of (7) has characteristics of multi-value storage and nonvolatile storage by selecting a desired ferroelectric memory element and performing writing and reading. This is a ferroelectric memory device capable of non-destructive and multi-value storage.

(8) A plurality of output terminals of the memory element described in (3) or (4) above are shared, and the vector information input from the input terminal and the vector information stored in the memory element in advance are used. The matrix operation with the torque information is processed in parallel, and the multiplication result is output from the output terminal.

Conventionally, a matrix calculator that handles (1,0) information has been devised. However, when the matrix operation is actually performed, the storage capacity to be handled is small if only the (1,0) information is used. Therefore, the analog quantity is replaced with (1,0) information, the calculation is performed after AZD conversion, etc., but the matrix can be smaller if the analog quantity is handled as it is. Such a ferroelectric memory device of (8) can perform a vector operation of information having three or more values and performs a high-speed matrix operation.

Further, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications and applications are possible without departing from the gist of the invention.

Therefore, as described in detail above, according to the eleventh to eighteenth embodiments of the present invention, a ferroelectric memory element having a multiple hysteresis characteristic having at least three or more stable polarization values is provided. Ferroelectric used A memory device can be provided.

Since the conventional ferroelectric has only two stable polarization states, the information that can be stored is binary, but the ferroelectric memory device of the present invention has a ferroelectric memory having multiple hysteresis characteristics in the storage medium. by using the body, rests may multilevel storage of three or more values at least ₀

Further, in the present invention, by using a voltage-current converter instead of an ON-OFF switch as a read element, multi-value storage and multi-value read are possible. Industrial applicability

The ferroelectric memory device according to the present invention as described above can be widely used as a nonvolatile memory.

Claims

The scope of the claims

1. a first electrode made of a conductive film formed on a substrate; a ferroelectric film formed on the first electrode and on which information is written;

A plurality of second electrodes made of a conductive film formed on the ferroelectric film,

A ferroelectric memory device characterized in that at least one of the formation arrangement relationship between the first electrode and the second electrode or the size of the facing electrode is different.

2. The ferroelectric memory device according to claim 1, wherein the shape of at least one of the first electrode and the second electrode is changed. .

3. The ferroelectric memory device according to claim 1, wherein the plurality of ferroelectric capacitors have different values of coercive electric field from each other, and the ferroelectric capacitors are connected in parallel. A ferroelectric memory device characterized in that the polarization state is read out non-destructively by utilizing the capacitance at the time of back switching in several polarization states of the obtained hysteresis hysteresis.

4. The ferroelectric memory device according to claim 3, wherein the ferroelectric capacitors having different relative dielectric constants are connected in parallel during back-switching in several polarized states of twisted hysteresis. A ferroelectric memory device characterized by a non-destructive readout method utilizing a capacitance difference.

5. The ferroelectric memory device according to claim 3 or 4 3. The ferroelectric memory device according to claim 1, wherein at least one or more ferroelectric capacitors among the plurality of ferroelectric capacitors connected in parallel have asymmetric hysteresis.

6. The ferroelectric memory device according to claim 5, wherein the ferroelectric capacitor having the asymmetric hysteresis has a multilayer structure of a conductor, a ferroelectric, an insulator, and a semiconductor. Characteristic ferroelectric memory device.

7. The ferroelectric memory device according to claim 5, wherein the ferroelectric capacitor having asymmetric hysteresis has a multilayer structure of a conductor, a ferroelectric, an insulator, and a semiconductor. Ferroelectric memory device.

8. A first lower electrode film formed on the insulator, a first ferroelectric film formed on the first lower electrode film, and a first ferroelectric film formed on the first ferroelectric film A plurality of first capacitor units formed by a unit ferroelectric capacitor including the first upper electrode film;

A first capacitor unit formed on the insulator and a plurality of second capacitor units having different coercive electric fields,

The second capacitor unit has a second lower electrode formed on the insulator, a second ferroelectric film formed on the second lower electrode, and a second ferroelectric film formed on the second ferroelectric film. A unit ferroelectric capacitor having a second upper electrode formed and having a second upper electrode having a shape different from that of the second lower electrode;

H'J BC At least in the first and second capacity units A ferroelectric memory device, wherein at least one device is electrically connected.

9. The ferroelectric memory device according to claim 8, wherein the ferroelectric materials of the plurality of first ferroelectric capacitor units and the plurality of second ferroelectric capacitor units are mutually different. A ferroelectric memory device characterized in that:

10. The ferroelectric memory device according to claim 8, wherein the plurality of first ferroelectric capacitor units and the plurality of second ferroelectric capacitor units have different thicknesses of ferroelectric material. A ferroelectric memory device characterized in that:

1 1. In the ferroelectric memory device according to claim 8, the plurality of second ferroelectric capacitors having different coercive electric fields from the plurality of first ferroelectric capacitor units described above are provided. A ferroelectric memory device characterized by being stacked to form a three-dimensional structure.

1 2. A first unit formed by arranging a plurality of first unit ferroelectric capacitors each having a laminated structure of a lower electrode film, a ferroelectric film, and an upper electrode film sequentially formed on an insulator. A capacitor unit and a second capacitor unit having the same laminated structure as the first unit ferroelectric capacitor and having a plurality of second unit capacitor capacitors having different coercive electric fields arranged on the insulator. When,

The first capacitor unit and a storage medium in which at least one unit capacitor in each of the second capacitor units is electrically connected in series or in parallel. Ferroelectric memory device.

13. A ferroelectric material that has multi-hysteresis characteristics with at least three or more stable polarization values and that stores multi-valued voltage associated with the multi-hysteresis characteristics as information is sandwiched between electrode materials. To form a ferroelectric capacitor,

A dielectric capacitor connected in series with the ferroelectric capacitor;

A ferroelectric memory device characterized by comprising:

14. The dielectric calibration Pasi data _{is, P b γ S r j_ y} (T i .. Ζ r j_ x) 0 one (X in the formula represents a composition ratio, 0.2 to 1.0 of the range Wherein Y represents a composition ratio and is in the range of 0.85 to 1.0). apparatus.

15. The above dielectric capacitor is expressed as PbγCa1 _-γ (Ti — Ζr1 _-χ ) 0, where X represents the composition ratio and is in the range of 0.2 to 1.0. 13. The ferroelectric memory device according to claim 13, wherein the ferroelectric memory device has a high-dielectric substance defined by a chemical composition of (1) and (2) represents a composition ratio and ranges from 0.85 to 1.0. .

16. The dielectric Capacity _{_{polygonal, P b y B a j_ y}} (! T ij Z r _ x) 03 (X in the formula represents a composition ratio, 0. 2: be a range of L. 0 13. The ferroelectric memory device according to claim 13, wherein the ferroelectric memory device has a high-dielectric substance defined by a chemical composition represented by the following formula: wherein Y represents a composition ratio and ranges from 0.85 to 1.0.

1 7. A dielectric capacitor with multiple hysteresis characteristics with at least three stable polarization values,

A dielectric capacitor connected in series to the dielectric capacitor;

A ferroelectric memory capable of multi-value storage, comprising: a resistance element connected in parallel to the dielectric capacitor; and a voltage-to-current conversion element for reading multi-value voltage information accompanying multiple hysteresis characteristics of the dielectric capacitor. apparatus.

18. The ferroelectric memory device according to claim 2, wherein the voltage-current conversion element is connected to a connection between the ferroelectric capacitor and the dielectric capacitor. .

1 9. The voltage-current conversion element for reading the multi-valued voltage information includes an element whose current is controlled for a positive voltage and an element whose current is controlled for a negative voltage. The ferroelectric memory device according to claim 13 or 17, wherein:

20. The ferroelectric memory device according to claim 17, wherein the dielectric capacitor is a gate capacitance of a MOS transistor and the resistive element is made of polysilicon. .