JP2960956B2 - Analog readout type memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an analog device that stores a plurality of bits of digital data in a plurality of memory elements and reads out the stored digital data as an analog current amount or an analog voltage amount. The present invention relates to a read-type memory device.

[Prior art] In recent years, as part of a control system embedded in equipment,
The memory is used for performing sequential control according to the contents of the memory, updating (learning) the contents of the memory according to a feedback signal from the control result, and performing control according to the contents. There is a demand for a memory device that outputs the contents as an analog quantity of the magnitude of the current or the magnitude of the voltage.

Such a memory device has a structure in which, for example, a D / A converter having a configuration as shown in FIG. 7 is added to a nonvolatile memory such as an EEPROM.

On the other hand, there has been known a memory element using a storage holding unit (medium) made of a ferroelectric material, which has a characteristic that the holding time of stored data is infinite in principle. In order to configure this memory element, a switch unit for controlling reading / writing of data is required in addition to the storage unit. In recent years, a MIM switch having a MIM structure of a conductive film (metal M), an insulating film (I), and a conductive film (metal M) has been developed as the switch unit.

Even if a memory device that stores a plurality of bits of digital data using a memory device including such a MIM switch and a storage holding unit made of a ferroelectric material is configured, the memory device becomes a digital input digital output type memory device. In order to obtain an analog output, it is necessary to use a D / A converter as in the above-mentioned EEPROM and the like.

That is, the memory device having the above-described configuration includes a digital input / digital output type memory unit and a D / A conversion unit that converts a digital signal into an analog signal.
In order to obtain an analog signal corresponding to the contents of the memory, it is necessary to address the memory, read out the contents of the memory as a digital signal, and then input the signal to a D / A converter.

[Problems to be Solved by the Invention] However, in the above configuration, the time required for extracting the memory contents as an analog signal is as follows:
(Memory read time) + (D / A conversion time) + (data transfer time), and considering the high-speed operation, the above-mentioned respective times become constraints.

Therefore, an object of the present invention is to provide an analog readout memory device that can output an analog signal only in a memory readout time.

[Means for Solving the Problems] According to the analog readout memory device of the present invention, a gate electrode provided via an insulating film formed on a semiconductor substrate and current paths formed on both sides of the gate electrode An output means comprising an electrode; a polarization charge storage means comprising a ferroelectric film or a dielectric film formed on a gate electrode of the output means; and a polarization charge storage means comprising a ferroelectric film or a dielectric film formed of the polarization charge storage means. A plurality of memory cells each having a first conductive film to be formed, an insulating tunnel film, and an input means formed of a non-linear conductivity element having an MIM structure of a second conductive film are combined by a plurality of memory cells. A plurality of bits of digital data are stored, and the stored digital data is converted into an analog current amount or an analog voltage amount by calculating an output current from each memory cell. And so as to output Te.

[Operation] According to the analog readout memory device of the present invention, the output current from the memory cell composed of a plurality of units storing the digital data of a plurality of bits is calculated, that is, added, to obtain the digital data of a plurality of bits. A corresponding analog current is obtained. According to the present invention, a D / A converter is not required, and thus a D / A conversion time and a data transfer time are not required. That is, it is possible to output an analog signal only in the memory read time.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

Before describing an embodiment of the analog readout memory device of the present invention, a gate detection type memory cell used for constructing the analog readout memory device according to the present invention will be described.

2 (a) to 2 (c) show a circuit configuration of the memory cell, and FIGS. 3 (a) and 3 (b) show a laminated structure of the memory cell.

That is, the circuit configuration of the memory cell shown in FIG.
The MIM switch 20 is configured to be connected in series with a gate of a normally-on type MOSFET 22 via a ferroelectric capacitor 21. The other of the MIM switches 20 is connected to one of the plurality of write lines Wx.

The current path of the MOSFET 22 has one end connected to a write line or a read line (Wy, Ry), and the other end connected to one read line Rx.

FIG. 2B shows a configuration of an equivalent circuit of the MIM switch 20. That is, since the MIM switch 20 is a nonlinear conductivity element and has a structure in which an insulating tunnel film is sandwiched between metal films from both sides, a diode 20a arranged so that current flows in both directions and a capacitor 20 It can be considered that they are connected in parallel.

FIG. 2C shows a configuration of an equivalent circuit of the ferroelectric capacitor 21.

As shown in the figure, this ferroelectric capacitor 21 can be regarded as a capacitor 21b connected in parallel to a non-linear capacitor 21a polarized in one direction.

In the memory cell having such a configuration, charge is stored in the ferroelectric capacitor 21 through the insulating tunnel film, and whether or not the charge is stored depends on the current between the source and the drain of the MOSFET 22 directly or indirectly connected to the capacitor 21. Is read as presence or absence.

In the structure of such a memory cell, a gate oxide film 25 is first formed on a semiconductor substrate 24 as shown in FIG. Further, a floating gate electrode 26 is formed on the gate oxide film 25. A ferroelectric film 27 of, for example, polyimide or the like is formed so as to cover the floating gate electrode 26.
Is formed.

Further, a first MIM switch is formed on the ferroelectric film 27.
The conductive film 28, the tunnel insulating film 29, and the second conductive film 30 are laminated.

In the structure shown in FIG. 3B, a gate oxide film 25 is formed on a semiconductor substrate 24, and a ferroelectric film 27 is formed thereon.
Is formed. Further, a tunnel insulating film 29 of LB (Langmuir-Blodgett) film and a second conductor film 30 are formed on the ferroelectric film 27 by lamination.

This is a method of connecting the MIM switch 20 to the gate of the MOSFET 22 via the ferroelectric capacitor 21 either directly as shown in FIG. 3 (b) or indirectly as shown in FIG. 3 (a). This is a case where a ferroelectric film is provided on an oxide film.

In both the structures of FIGS. 3A and 3B, there is no need to provide wiring for connecting the stacked layers,
Leaks can also be kept very small.

Therefore, the written polarization charge is maintained as it is,
In FIG. 2 (a), the effect of neutralization by the charges accumulated in the parallel capacitance indicated by C0 can be neglected.

Therefore, in the configuration shown in FIG.
It is possible to directly read by applying to the gate of ET23.

The reason why a normally-on MOSFET is used for the MOSFET 23 is that a normally-off MOSFET has, for example, an n-channel type.
This is because, when a negative signal is input, a short circuit may occur between the semiconductor substrate 24 and the channel due to the gate voltage.

An n-bit D / A converter with memory (parallel operation type) is configured by using a plurality of gate detection type memory cells having the above-described structure. By combining two-dimensionally or three-dimensionally, an analog readout type memory device (multi-value output type 2 ^n- value output) can be realized. Here, the n-bit D / A converter with memory alone can be considered as a memory that can output one digital signal value stored in n bits into an analog signal.

Next, the n-bit D / A converter with memory will be described.

FIG. 4 is a diagram showing a circuit configuration of a 4-bit D / A converter with memory as an example of the n-bit D / A converter with memory. This D / A converter includes a gate detection type memory cell 31 composed of a MIM switch 20, a ferroelectric capacitor 21, and a MOSFET 22.
Are arranged in parallel with each other. In this case, the ON resistance of each MOMFET 22 is set at a ratio of 1: 2: 4: 8. In the figure, reference numeral 33 is a memory write / read terminal of each MIM switch 20, and reference numeral 34 is a read control terminal of a read control switch 35 commonly connected to one of the current paths of each MOSFET 22. Also, reference number 36
Is a reading ammeter commonly connected to the other of the current paths of the respective MOSFETs 22.

In a 4-bit D / A converter with a memory having such a configuration,
The 4-bit digital data given to the memory write / read terminal 33 is transferred to each ferroelectric capacitor.
By storing the presence or absence of electric charge in 21 and applying a predetermined read control signal to the read control terminal 34, parallel operation is performed according to the presence or absence of electric charge in each ferroelectric capacitor 21, and the operation is completed at the speed of current flow. The operation result is detected by the reading ammeter 36 as the magnitude of the current.

Since the charge storage unit has a structure in which charge transfer is prevented by a ferroelectric or insulating film, the memory is non-volatile.

The time required for the D / A conversion is basically considered to be substantially equal to the switching time of the read control switch 35.

FIG. 5 is a diagram showing the analog output current (8 values) for the 4-bit digital inputs (0000) to (1111) detected by the reading ammeter 36. Thus, the analog output current linearly corresponds to the digital input value.

Thus, MIM switch 20, ferroelectric capacitor 21, M
An n-bit D / A converter with a memory can be realized by using a memory cell in which n gate detection memory cells 31 composed of the OSFET 22 are arranged in parallel.

FIG. 6 is a schematic configuration of an analog readout memory that outputs m ² pieces of information as ( ²ⁿ multi-valued) analog values using m × m pieces of such n-bit D / A converters with memory. FIG. 1 is a detailed diagram when an n-bit D / A converter with a memory is used.

As shown in these figures, X,
At each intersection of the Y address lines XA, YA (XA ₁ , XA ₂ ,…, YA ₁ , YA ₂ ,…), connect the memory cells 32 to those X, Y address lines XA, YA, and connect them to each address line. X, Y address switches 37, 38 (37 ₁ , 37 ₂ ,..., 38 ₁ , 38 ₂ ,...) For selecting. A current detector (ammeter) 39 is commonly connected to the other end of the current path of the Y address switch 38. Reference numeral 40 in FIG. 1 is a protection diode, and 41 is a write control switch.

In the analog read type memory device having such a configuration, writing of digital data is performed as follows. That is, first, the memory cell 32 to which data is to be written
Out of the X and Y addresses to specify the data write terminal (D select ₀ ~D ₃₎ 33,
Data to be written to those terminals 33 is set. In this case, for example, if the data to be written is “1”, “5V” is applied to those terminals 33 if it is “0”. Next, the Y address switch 38 (for example, 38 ₁ ) corresponding to the memory cell 32 to which data is to be written and the write control switch 41 are turned on in accordance with the Y address. As a result, the data write terminals (D _{0 to} D ₃ )
Information corresponding to the data set in 33 is the gate oxide film
The electric charge is stored in the ferroelectric capacitor 21 disposed on the reference numeral 25.

When writing to another column, the Y of the column to be written
The address switch 38 is turned on, and the write control switch 41 is turned on. Thus, the Y address switch 38
, And turning on the write control switch 41, data can be written in a desired column.

When reading is performed, the X address switches 37 and Y corresponding to the memory cells 32 from which information is to be read are used.
The address switch 38 is turned on, and the analog value is read by the current detector 39. Reading to other memory cells 32
This is done by switching both the X and Y addresses.

Thus, it is possible to provide an analog readout type high-speed memory device which can output an analog signal only in the memory readout time.

Further, the analog readout type memory device is an electrically rewritable nonvolatile memory device, and does not require a backup power supply.

It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications and changes are possible.

For example, instead of distributing the on-resistance of the gate detection memory cell 31 at a ratio of 2 ⁿ ,
By distributing at a ratio of 2 ⁿ , an n-bit D / A converter can be realized, and the analog read memory device as described above can be configured by combining them.

Alternatively, n ² n-bit D / A converters may be arranged, and digital data from 0 to 2 ⁿ may be stored in a memory cell in advance in the order of addresses. Thus, an analog amount corresponding to an address can be obtained only by addressing, and a high-speed D / A converter can be realized.

In addition to distributing the ON resistance of the gate detection type memory cell 31 at a ratio of 2 ⁿ , a non-linear D / A conversion function such as a sigmoid function can be provided by arbitrarily combining them. Thereby, the non-linear operation can be performed in parallel and at high speed.

As described above, in the analog readout memory device of the present invention, not only linear parallel operation but also nonlinear high-speed operation can be performed according to the contents in the memory.

Further, instead of the ferroelectric capacitor 21, a dielectric capacitor can be used.

[Effects of the Invention] As described above in detail, according to the present invention, it is possible to provide an analog readout type high-speed memory device which can output an analog signal only in a memory readout time.

[Brief description of the drawings]

FIG. 1 is a detailed circuit configuration diagram of the analog readout type memory device of the embodiment, FIGS. 2 (a) to 2 (c) are circuit diagrams showing the circuit configuration of a memory element, respectively, and FIGS. 3 (a) and 3 (b). ) Are cross-sectional views each showing a laminated structure of a memory element.
FIG. 4 is a circuit diagram of a 4-bit D / A converter with memory, FIG. 5 is a diagram showing input / output characteristics of the 4-bit D / A converter with memory, and FIG. 6 is an analog readout type of the embodiment. FIG. 7 is a schematic circuit configuration diagram of a memory device, and FIG. 7 is a circuit configuration diagram of a conventional D / A converter. 20 …… MIM switch, 21 …… Ferroelectric capacitor, 22…
... MOSFET, 32 ... memory cell, 33 ... data write terminal (memory write / read terminal), 37 ... switch for X address, 38 ... switch for Y address, 39 ... current detector (ammeter), 40 …… Protective diode, 41 ……
Write control switch, XA ... X address line, YA ... Y
Address line.

────────────────────────────────────────────────── ─── Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/22 G11C 11/56 G11C 27/00 H01L 27/00-49/02 G11C 11/34 G11C 16 / 00

Claims (1)

(57) [Claims] An output means comprising a gate electrode provided on an insulating film formed on a semiconductor substrate and current path electrodes formed on both sides of the gate electrode; and an output means formed on the gate electrode of the output means. Polarization charge accumulating means comprising a ferroelectric film or a dielectric film formed as described above, and a first conductive film, an insulating tunnel film, and a second film formed on the ferroelectric film or the dielectric film of the polarization charge accumulating means. Combining a plurality of memory cells each having an input means comprising a non-linear conductivity element having a MIM structure of a conductive film, storing a plurality of bits of digital data in the memory cells comprising the plurality of units, and storing the stored digital data. An analog readout type memory device, wherein an output current from each memory cell is calculated to output an analog current amount or an analog voltage amount.