JP3302721B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device. More specifically, an FET having a metal film-ferroelectric film-semiconductor layer structure using a ferroelectric film (hereinafter referred to as MFS)
A non-volatile semiconductor memory device capable of selectively writing and non-destructively reading using an FET.

[0002]

2. Description of the Related Art As shown in FIG. 4, a ferroelectric film has a hysteresis. Therefore, once a voltage higher than an electric field (A in FIG. 4) at which sufficient polarization is obtained is applied, the polarized electric charge becomes polarized. It remains even when the applied voltage becomes 0, and can retain the memory even when the power is turned off. Moreover, by arranging the ferroelectric film between the gate electrode and the channel region, even if a current flows between the source and the drain during reading,
The polarization in the ferroelectric film is not affected and can be read nondestructively, and a memory cell having an MFS-FET structure is being developed.

FIG. 5 shows an example of such an MFS-FET structure.
5 (a) to 5 (c), and FIG. 5 (d) shows the state of the channel when the ferroelectric film is polarized. FIG. 5A shows an example of the simplest structure of the MFS-FET. For example, a ferroelectric film 27 and a gate electrode are formed on the surface of a p-type semiconductor substrate 21.
28, an n ⁺ -type impurity region, for example, is formed on both sides of the channel region 26 on the surface of the semiconductor substrate 21 below the ferroelectric film 27 to form a source region 22 and a drain region 23. The FET is configured. Here, the ferroelectric film 27 is made of PZT having an oxide perovskite structure.
_{(Pb (Zr 1-x Ti} x) O 3), PLZT (Pb 1-x
La _x (Zr _1-y Ti _y ) _{1-x / 4} O ₃ ), PbTi
O ₃ , BaTiO _{3, and the} like are preferable because a film with good crystallinity can be obtained from the viewpoint of compatibility with the base. Further, the gate electrode 28 is preferably made of platinum because of its adhesion to the ferroelectric film 27.

In the structure shown in FIG. 5B, an insulating film 25 such as CaF ₂ or SiO ₂ is interposed between the ferroelectric film 27 and the semiconductor substrate 21. This is to prevent the Pb of PZT from melting into the semiconductor substrate 21.

In the structure shown in FIG. 5C, an electrode film 24 made of platinum or the like is further interposed between the ferroelectric film 27 and the insulating film 25 shown in FIG. Ferroelectric film 27
Is intended to improve the orientation. That is, SiO ₂
The insulating film 25 such as PZT is amorphous, and the ferroelectric film 27 such as PZT is crystalline. When the ferroelectric film 27 is formed on the amorphous, the film has no orientation. However, this is because a platinum film is a film having <111> orientation, and PZT formed thereon is also a crystalline film having orientation.

When a voltage is applied between the gate electrode 28 of the MFS-FET and the semiconductor substrate 21 so that the gate electrode 28 becomes a positive voltage and a sufficient polarization is obtained, FIG. As shown, electrons are induced in the channel region 26 of the semiconductor substrate 21 to form a depletion layer. Therefore, even when the gate electrode is at 0 V, the voltage is applied to the source region 22 and the drain region 23 of the n ⁺ -type region so that the gate electrode becomes conductive and a sense amplifier (not shown) connected to the source region 22 Through this, the storage state of the ferroelectric film 27 can be read.

However, when the MFS-FETs are arranged as a memory cell in a matrix and used as a storage device, a selection circuit which can selectively perform writing and reading for each cell is required. A circuit conventionally considered as such a selection circuit is disclosed, for example, in Japanese Patent Laid-Open No. 2-6499.
As disclosed in Japanese Unexamined Patent Publication No. 3 (1993), there has been proposed a circuit in which two MOS transistors are connected in series on both sides of a memory MFS-FET.

FIG. 6 shows an equivalent circuit of such a memory cell MC. In this configuration, the writing is first with the transistors T ₁ to ON, the transistor T ₂ O
FF, and the data from the bit line BL is MFS-FET
And application of the memory transistor T _M, the gate electrode of the transistor T _M - voltage 1 / 2Vc of predetermined orientation between the substrates
Apply c. Thus, transistor T _M is the ferroelectric film becomes electric polarization state of the predetermined direction, the data can be written.

On the other hand, in a read operation is also turned on transistors T ₁ advance to turn on the transistor T _2. As a result, depending on the direction of the electric polarization of the ferroelectric film, the memory transistor _TM becomes conductive or non-conductive, corresponding to the storage states “1” and “0”,
Data can be read by detecting a potential change of the bit line BL.

[0010]

The above-mentioned MFS-FET
Is a memory cell structure using MFS-FE for memory.
Since it is composed of one T1 and two MOSFETs,
Since three transistors are formed in one cell, a large cell area is required. Therefore, there is a problem that high integration in which a large number of cells are formed on a chip having a small area cannot be achieved.

Further, in a memory cell using such a ferroelectric film, even if a voltage lower than the threshold voltage is applied to the gate electrode, the polarization state changes and a data error is likely to occur, and a parasitic capacitance and the like are generated. There is a problem that an unnecessary potential difference easily occurs due to the influence of the above.

The present invention solves such a problem and allows a cell to be selected with a simple configuration, high integration, and an unnecessary potential difference does not occur in the ferroelectric except at the time of writing and erasing. It is an object to provide a semiconductor memory device having a memory cell in which no error occurs.

[0013]

A semiconductor memory device according to the present invention comprises: a nonvolatile memory transistor having at least a ferroelectric film between a gate electrode and a semiconductor substrate;
Potential equalization means connected between the gate electrode and the semiconductor substrate in parallel with the memory transistor, two diodes connected in series to which a unique potential can be applied to both ends, and connection of the two diodes It has a memory cell in which a point and the gate electrode are connected.

Further, in the semiconductor memory device according to the present invention, a third diode is connected to a source electrode of the memory transistor, and the series-connected two diodes are connected in series.
Terminals at both ends of each of the three diodes, the terminal at the other end of the third diode, and the substrate of the memory transistor.
As terminals, the respective terminals of the memory cells arranged in a matrix are connected vertically and horizontally.

[0015]

According to the present invention, the gate electrode of the MFS-FET is connected to the semiconductor substrate via the potential equalizing means. Since a high resistance of, for example, about 1 G to 1 MΩ is used as the potential equalizing means, even if floating charge due to parasitic capacitance or the like is generated in the gate electrode, the floating charge is discharged through the potential equalizing means and adversely affects the polarization state. Has no effect. In addition, when a voltage is applied between the gate electrode and the semiconductor substrate at the time of writing, reading, or the like, the voltage is held at the gate electrode via the potential equalizing means, so that writing and reading can be performed.

Further, in order to selectively write, read and erase each cell, two diodes are connected in series so that a unique potential can be applied to both ends, and the midpoint thereof is connected to the gate electrode of the transistor. Therefore, by using the switching means of the diode, the gate electrode of the memory transistor can be controlled, each cell can be selectively driven at a low voltage, and the semiconductor memory device can be configured with a small cell area.

[0017]

Next, a memory cell of a semiconductor memory device according to the present invention will be described with reference to the drawings. FIG. 1 is an equivalent circuit diagram of a main part of a memory cell section according to one embodiment of the present invention.

In FIG. 1, T _M is an MFS- for memory.
In FET, the gate electrode g of the memory transistor T _M is connected to one end of the high resistance R of the potential equivalent means, the other end of the high-resistance R is the drain electrode 3 of the memory transistors T _M, is connected with the substrate 1 . The source electrode 2 of the memory transistor T _M is drawn independently to be connected to the bit line. When writing to the memory transistors T _M in this configuration, by an electric field or voltage is sufficient polarization between terminal g and the substrate is e is applied, the resistance R as a potential equivalent means a high resistance For this reason, a voltage is applied between both ends of the ferroelectric film with almost no current flowing, and polarization can be caused in the ferroelectric film. At this time, if a positive voltage is applied to the gate electrode side, a positive charge is polarized on the semiconductor substrate side of the ferroelectric film, and electrons are generated on the semiconductor substrate surface (channel region) after the write voltage is removed. Induced. Conversely, when a negative voltage is applied to the gate electrode side, negative charges are polarized on the semiconductor substrate side of the ferroelectric film, and holes are induced on the semiconductor substrate surface after the write voltage is removed. You. Therefore, writing or the like is performed by applying a positive or negative voltage to the gate electrode, that is, the terminal g, depending on whether the MFS-FET is the p-channel or the n-channel and according to the setting of the threshold voltage.

[0019] In this embodiment, between the gate electrode and the substrate of the memory transistors T _M, because the memory transistors T _M to the potential equivalent means in parallel (e.g. resistor R) is connected, the voltage on the terminal g is applied Otherwise, even if floating charges are generated, they are discharged through the potential equalizing means, the gate electrode g is kept at the same potential as the substrate, and adversely affects the charges separated into the ferroelectric film by the floating charges. Has no effect.

[0020] In the present invention, for selectively applying a voltage to the aforementioned terminal g, the two diodes to the gate electrode of the memory transistor T _M by connecting the middle point connected in series the two
Performs pieces of or a voltage is applied to the gate electrode of the series connected diodes of the anode terminal a and the cathode-side terminal c to the memory transistor T _M by controlling the voltages applied, the switching action or not It is. Incidentally, by connecting the diode to the terminal b is the source side of the memory transistors T _M, the memory transistor when the semiconductor memory device teamed a matrix, it is possible to read each memory transistor selectively.

The anode-side terminals a of the _two series-connected diodes D ₁ and D ₂ are connected to each other by a vertically arranged cell of each memory cell arranged in a matrix.
Word lines a _1, a ₂ ... a _n is formed and said two series connected diodes D _1, D ₂ of the cathode-side terminal c of
Are connected by cells arranged in the vertical direction of each memory cell arranged in a matrix to form second word lines c ₁ , c ₂ ,.
_n is formed, further the memory transistors T a _M terminal b connected diodes D ₃ to the source electrode of the first bit line b ₁ are connected by vertically aligned cells of each memory cell,
b ₂ ... b _n are formed. Further, connected opposite terminal and the gate electrode side connected to the potential equivalent means of each memory cell, the connection point d which connects the drain electrode and the substrate of the memory transistor T _M in aligned cells in the horizontal direction of the memory cell second bit lines d _1, d ₂ ... to form a d _n, by connecting the respective memory cells arranged in a matrix of four lines selectively writing to each cell, reading, to be able to erase Te Is configured.

Next, a semiconductor memory device in which memory cells according to the present invention are arranged in a matrix form will be described.
An erasing driving method will be described.

FIG. 2 is an equivalent circuit diagram of a part of a semiconductor memory device in which memory cells according to one embodiment of the present invention are arranged in a matrix. In the figure, a memory transistor T
_M is a p-channel MFS-FET. The cell Q ₁ to perform writing in this _{configuration, a 1, c 1, a} 2 ... a n,
d ₂ ... d _n to _{-V cc, b 1, d 1} , b 2 ... b n, c 2 ...
Set c _n to 0. That is, the gate electrode is -V _cc next memory transistors T _M for a ₁ and c ₁ in cell Q ₁ represents a -V _cc at the same potential, the memory transistors T _M ferroelectric film for the substrate side is zero Has a negative charge polarized on the substrate side. In contrast cell Q ₂ for c ₂ is 0, there reverse breakdown voltage of the diode D ₁ is more -V _cc memory transistors T
The gate electrode of _M becomes 0 V, and the substrate is also 0 V (d ₁ = 0)
Is not written. The cell Q _3, Q ₄ is a write for a -V _cc gate electrode of the memory transistor T _M, the substrate both Sarezu, is only the write eventually cell Q _1.

Next, reading will be described. Cell Q ₁
, A ₁ , b ₁ , a ₂ ... _An , d ₂ .
The -V _cc to _{d n, c 1, b 2} ... b n, c 2 ... c n in V _cc
, And by connecting d ₁ to the sense amplifier SA, the cell Q ₁ can be read. That is, the cell Q ₁ in the diode D _1, D ₂ current flows not gate electrode is between the substrate and the same potential (d ₁₎ via a potential equivalent means R. However, the electric field effect of the ferroelectric polarization acts on the channel, and the conduction and non-conduction between the drain and the source are made in accordance with the polarization state of the ferroelectric, so that the state of "1" and "0" can be read. In the cells Q ₂ and Q ₄ , regardless of whether the transistors are conductive or non-conductive, the diode connected to the source is in the opposite direction, no current flows between the drain and the source, and reading cannot be performed. Can not be between the cell Q ₃ drain and source are read at the same potential, it is possible to eventually read only the cells Q _1.

Next, erasure will be described. Cell Q ₁
A ₁ , b ₁ , c ₁ , b ₂ ... B _n , c
₂ ... c _n, and the d ₂ ... d _n to V _cc, to d ₁ and a ₂ ... a _n 0. That is, in the cell Q _1, since both ends of the potentials of both diodes D _1, D ₂ are the same V _cc, a gate electrode g which satisfied even V _cc of memory transistors which is a middle point, the potential of the substrate (d), 0 Therefore, a voltage opposite to that at the time of writing is applied, and the data is erased. on the other hand,
Cell Q ₂ in the two diodes D _1, D ₂ reverse voltage V _cc across is applied, the diode V _cc from the inverse breakdown voltage of the D ₂
Is low, the gate electrode g of the transistor T _M of 0 substrate potential (d ₁₎ is also erased 0 is not the sole, cell Q ₃ in Getoto electrode g, the substrate both in V _cc, erasing is not.
Further cell Q ₄ In the gate electrode g is the potential of the substrate (d ₂₎
It is equal to _Vcc and is not erased.

[0026] The above-described memory transistor _{T M} is p
Channel, summarized writing when the direction of the diode D ₁ to D ₃ shown in FIG. 2 are connected, reading, the relationship between the voltage applied at the time of performing the cell Q ₁ erase in Table 1. Here, if V _cc is set to about 3 V, it is sufficient that the voltage is higher than a voltage at which sufficient polarization of the ferroelectric can be obtained.

[0027]

[Table 1]

Next, an equivalent circuit diagram when placing the memory transistors T _M in a matrix in the case where a memory cell in MFS-FET of the n-channel in Fig. Although the orientation of the diode D ₃ in this embodiment is connected to the source electrode of the memory transistor T _M are opposite others are the same as in the previous embodiment.

To perform writing with this configuration, a ₁ ,
_{c 1, c 2 ... c n} , the d ₂ ... d _n to V _cc, the other b _{1,
d 1, a 2 ... a n} , a b ₂ ... b _n to 0. That is,
In cell Q _1, the potential of the two diodes D _1, the potential across the D ₂ equals V _cc at which for intermediate gate electrode g of the potential i.e. transistor also becomes V _cc. On the other hand, since the potential (d ₁ ) of the substrate is 0, the ferroelectric film is polarized, and writing is performed in which the substrate is polarized to a positive charge. Even if the potential of the gate electrode becomes 0, electrons are induced in the channel region of the semiconductor substrate by the remnant-polarized positive charges, and the n-channel FE
T is made conductive. On the other hand, cell Q ₂ is the gate electrode g to reverse direction voltage diodes D _1, D ₂ becomes 0, and the potential of the substrate (d ₁₎ at 0 write is not.
The cell Q ₃ are the potential of the gate electrode g is V _cc not even V _cc next write potential of the substrate (d ₂ ... d _n).
Cell Q ₄ are the potential of the gate electrode g of the substrate potential (d ₂ ... d
_n ) It is equal to _Vcc and no writing is performed.

Next, reading will be described. Cell Q
To _one of the _{reading, a 1, a 2 ... a} n, b 2 ... b n
To _{-V cc, b 1, c 1} , c 2 ... c n, d 2 ... d n to V _cc
And a negative voltage is applied to d ₁ via the sense amplifier SA. That is, in the cell Q _1, the potential of the gate electrode is the same as the substrate, the source - a potential difference is generated between the drain and the channel region is ON, turns OFF in accordance with the polarization state, continuity, "1" by the non-conducting, The state of "0" can be read. On the other hand, in the cells Q ₂ and Q ₄ , no current flows regardless of whether the channel is conducting or non-conducting because the voltage between the source and the drain is opposite to that of the diode D _3, and reading cannot be performed. Further, the cell Q _3, the source - drain is again no current flows at the same potential, it can not read, eventually cell Q ₁
Only the data can be read.

Next, erasure will be described. Cell Q ₁
, A ₁ , b ₁ c ₁ , a ₂ ... _An ,
_{b 2 ... b n, d 2} ... d n to -V _cc, is applied to d _1, c ₂ ... 0 to c _n. That is, the potential of the cell Q ₁ in the gate electrode substrate potential -V _cc (d ₁₎ is reversed the potential relation in the case of writing for 0, are erased. On the other hand, cell Q ₂
Are not erased because the gate electrode g and the substrate co-potential become 0. Also not erased cell Q ₃ in the gate electrode g, the substrate both in -V _cc. Potential of the cell Q ₄ In the gate electrode g is equal to the potential -V _cc of the substrate, not erased.

[0032] The above-described memory transistor _{T M} is n
Channel, summarized writing when the direction of the diode D ₁ to D ₃ shown in FIG. 3 is connected, read, the relationship between the voltage applied when performing the cell Q ₁ erase in Table 2. Here, V _cc is the same as in the above-described example.

[0033]

[Table 2]

[0034] Also with the polarity diodes D _1, D ₂ in the reverse from the above description, it is needless to say that the same if the voltage applied to a ₁ ... a _n and c ₁ ... c _n reversed.

[0035]

According to the present invention, a semiconductor memory device in which non-volatile memory cells using a strong dielectric film are formed in a matrix is connected to a potential equalizing means between a gate electrode of a memory transistor and a substrate. By connecting the middle point of two diodes connected in series to the gate electrode and connecting the third diode to the source electrode side, each memory cell can be selectively written, read, and erased. Since a diode can be formed with a small area, a nonvolatile semiconductor memory device using a ferroelectric film with a small cell area can be configured.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram when memory cells according to an embodiment of the present invention are formed in a matrix.

FIG. 3 is an equivalent circuit diagram when memory cells according to another embodiment of the present invention are formed in a matrix.

FIG. 4 is a diagram showing a hysteresis characteristic of a ferroelectric material.

FIGS. 5A to 5C are diagrams showing examples of an MFS structure.
(D) is a diagram illustrating a state when the ferroelectric film is polarized.

FIG. 6 is an example of a circuit configuration of a memory cell of a conventional semiconductor memory device using an MFS-FET.

[Explanation of symbols]

g gate electrode T _M memory transistor (MFS-FET) R resistor D _1, D ₂ diode D ₃ diode

Claims (2)

(57) [Claims] 1. A non-volatile memory transistor having at least a ferroelectric film between a gate electrode and a semiconductor substrate, and potential equalizing means connected in parallel with the memory transistor between the gate electrode and the semiconductor substrate. And a memory cell including two diodes connected in series to each other to which a unique potential can be applied to both ends, and a connection point between the two diodes and the gate electrode. 2. A memory cell according to claim 1, wherein a third diode is connected to a source electrode of said memory transistor, and each terminal at both ends of said two diodes connected in series, and said third diode is connected to said other terminal. A semiconductor memory device in which each terminal of each memory cell arranged in a matrix is vertically and horizontally connected with four terminals having an end terminal and a substrate of the memory transistor.