WO1995008132A1 - Compact projection illumination system and method of using same - Google Patents
Compact projection illumination system and method of using same Download PDFInfo
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- WO1995008132A1 WO1995008132A1 PCT/US1994/010622 US9410622W WO9508132A1 WO 1995008132 A1 WO1995008132 A1 WO 1995008132A1 US 9410622 W US9410622 W US 9410622W WO 9508132 A1 WO9508132 A1 WO 9508132A1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/74—Projection arrangements for image reproduction, e.g. using eidophor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/74—Projection arrangements for image reproduction, e.g. using eidophor
- H04N5/7416—Projection arrangements for image reproduction, e.g. using eidophor involving the use of a spatial light modulator, e.g. a light valve, controlled by a video signal
- H04N5/7441—Projection arrangements for image reproduction, e.g. using eidophor involving the use of a spatial light modulator, e.g. a light valve, controlled by a video signal the modulator being an array of liquid crystal cells
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0414—Vertical resolution change
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0421—Horizontal resolution change
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/045—Zooming at least part of an image, i.e. enlarging it or shrinking it
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
- G09G2340/0471—Vertical positioning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
- G09G2340/0478—Horizontal positioning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
- G09G2340/0485—Centering horizontally or vertically
Definitions
- the present invention relates to a projection illumination system and illumination methods therefor. It more particularly relates to an improved compact liquid crystal projector system, which is relatively small in size and thus able to be readily transported.
- the present invention also relates in general to an improved lens arrangement and method of using it.
- the invention more particularly relates to a projection lens arrangement which may be used to facilitate focusing a projected image on a remote viewing surface.
- the present invention further relates in general to a display control system and method of controlling the display of information images.
- the invention more particularly relates to a display control system and method of controlling a display to enable the
- Overhead projectors for large audience presentations are well known in the prior art. Such systems typically utilize transparencies for conveying the information to be viewed by the audience.
- liquid crystal display panel is typically positioned on the stage of an overhead projector to project an image onto a remote viewing surface.
- an integrated compact projection system has been employed and has been proven to be highly successful.
- the integrated system includes a computer driven display panel built into a small, low profile projector.
- Such an integrated projector is disclosed in the foregoing mentioned patent and patent applications.
- Such an integrated compact projector is so small and compact that it can be readily carried, for example, onto an airplane. In this manner, an entire display
- presentation can be pre-programmed and stored in a small personal computer, and the projector can be readily transported therewith. Thus, a person can conveniently travel with the presentation equipment, for use when traveling.
- the light image can become distorted as a result of the serrated devices producing a plurality of smaller light beams. While the serrated devices tend to expand the light image in both the horizontal and vertical dimensions, the stepped surfaces produce the smaller beams are spaced apart, thereby distorting the image. Moreover, since there are two serrated devices, the distortion is compounded. As a consequence of such inherent distortion, the patented system employs a highly dispersive viewing surface, such as one having ground glass to blur the smaller beams together.
- Such lens arrangements include those utilized with front and overhead projectors, and still and motion picture video projectors.
- the lens is mounted above and spaced-apart from the stage of the projector.
- a transparency or computer controlled liquid crystal panel for providing an image to be projected is positioned on the stage.
- the distance between the transparency or object and the entranceway to the projection lens is referred to as the object length and is about 15 inches in length in some overhead projectors.
- a Fresnel lens arrangement causes light, emitted from a high intensity lamp disposed below the stage, to be directed upwardly into the projection lens at an angle. This angle is called the field
- the overall length of the projection lens arrangement is adjustable. This overall length is referred to as the vertex length of the lens arrangement.
- the object length must be substantially shorter and thus, the field coverage angle must be substantially greater.
- the field coverage angle must be substantially greater.
- aberrations can be introduced, such as field curvature aberrations and other types of known aberrations.
- a projection lens arrangement In order to focus a variety of different sized images to be projected onto a remote viewing surface, a projection lens arrangement must be variable for focusing purposes.
- the vertex length of the lens arrangement must be variable but yet sufficiently small to enable the lens arrangement to be utilized in a small compact projector system.
- shortening the vertex length introduces other problems. For example, by shortening the vertex length it is difficult, if not impossible to have
- a new and improved display control system which is capable of enabling a high resolution image such as a 1,280 ⁇ 1024 workstation image to be displayed on a low resolution monitor such as a 1024 ⁇ 768 personal computer liquid crystal display monitor.
- a display control system should enable a
- the projection display system In addition to the ability to be compatible with a variety of different computers, it would also be highly desirable to enable the projection display system to provide a zoom function.
- the system should be able to zoom from a small size image to an enlarged image in a convenient manner, such as by means of a remote control arrangement.
- Such a system should be relatively inexpensive to manufacture, and should be able to operate "on the fly" as the video images are being presented to the projection system.
- the system should be compatible with not only computers, but also video recorders and live television video signals.
- pointing devices, graphic tablets and like devices have been employed for drawing attention to particular aspects of a displayed image.
- a hand held laser light generator has been employed to produce a highly focused beam of light for creating an auxiliary light image on that part of the primary image to be accentuated.
- a user is able to move the laser pointer so that the spot of auxiliary light travels along a desired path from one primary image portion to another.
- a laser driven optical communication apparatus includes a laser pointer for forming a spot of auxiliary control light on a projected image cooperates with an optical receiver for detecting the spot of auxiliary light reflecting from the projected image.
- a secondary projector responsive to the receiver then projects a calculated image representation of the path traced out by the spot of auxiliary light as the user moves the pointer from one primary image
- the principal object of the present invention is to provide a new and improved precisely controlled projection system and method for projecting a bright image having little or no image distortion.
- Another object of the present invention is to provide such a new and improved projection system and method to facilitate the provision of a compact size projector.
- the above and further objects of the present invention are realized by providing a new and improved projection system and technique, to project a light image with a precisely controlled projection light with little or no image distortion.
- a projection system includes a pair of finely faceted mirrors angularly disposed relative to one another to spread projection light emitted from a high intensity projection light source in two directions, and direct the reflected light to an image forming display device where an image is formed for projection purposes.
- the light is spread to illuminate precisely the light impinging surface of the image forming display device in a compact and efficient manner.
- the light source and optic elements including the mirrors are arranged and constructed to permit the beam segments to converge sufficiently to fill in dark or shadow areas between the beam segments prior to the segments impinging on the image forming display device, so that the
- resulting image is formed uniformly and substantially distortion free in a narrowly defined, compact space.
- illumination arrangement of the present invention can be used in a projector having an integrated liquid crystal display as the image forming display device, and in an overhead projector having a transparency supporting transparent stage as the image forming device.
- the principal object of the present invention is to provide a new and improved projection lens arrangement and method of using the arrangement which can be used readily in a small compact projector that is easily transportable.
- Another object of the present invention is to provide such a new and improved projection lens
- optical aberrations such as field curvature aberrations and other known aberrations.
- Yet another object of the present invention is to provide such a new and improved projection lens
- a further object of the present invention is to provide a new and improved projection lens arrangement which can be easily and automatically adjusted to focus an image on a remote viewing surface. Such a lens arrangement should be easily adjusted for focusing purposes, and relatively inexpensive to manufacture.
- the projection lens arrangement is configured in a Tessar configuration having generally three groups of optical elements aligned along a common optical axis with a variable vertex length and field coverage angle of up to about 22.1 degrees.
- a plurality of the element surfaces are aspheric.
- One element group near the object is a doublet having a negative element with a concave surface and having a positive element, which is bi-convex and has one surface near the image, the surface being complementary shaped to the concave surface of the negative element.
- the principal object of the present invention is to provide a new and improved display control system and method of using it to enable a high resolution image to be displayed on a low resolution display monitor.
- Another object of the present invention is to provide such a new and improved display control system and method of using it to enable workstation-based information to be shared with a large group of users in a relative inexpensive manner.
- Still yet another object of the present invention is to provide such a new and improved display control system and method of constructing it so that it converts
- the display control system includes a set of low speed relatively inexpensive analog to digital converters for converting incoming high resolution information into digital information for display on a low resolution display monitor.
- the system converts and displays one half of the incoming information during one frame cycle and then converts and displays the other half of the incoming information during the next frame cycle.
- the display control system also includes a logic arrangement that compresses the high resolution
- the principal object of the present invention is to provide a new and improved display control system and method of using it to enable a
- Another object of the present invention is to provide such a new and improved display control system and method of using it to enable panning of the
- a new and improved display control system which includes a logic arrangement for causing a displayed image indicative of a portion of a corresponding larger image to be displayed upon an input command from a user.
- a line control circuit responsive to user input commands enables the displayed image to be shifted visually from a current visualization position, up or down, row by row for line pan visualization of corresponding portions of the larger image.
- a pixel control circuit also responsive to user input command enables the displayed image to be shifted visually from a current visualization position right or left, column by column, for column pan visualization of corresponding portions of the larger image.
- the line control circuit and the pixel control circuit operate independently of one another or in combination with one another to achieve any desired panning effect.
- the principal object of the present invention is to provide a new and improved projection display control system and method of using it to enable various size images from various sources, such as
- Another object of the present invention is to provide such a new and improved projection display control system and method of using it to enable zooming of the image to be projected in a fast and convenient manner.
- a new and improved display control system which includes a logic arrangement for causing a display image of a given resolution to be displayed in an adjusted size to
- the system also enables an image to be zoomed in size prior to projecting it.
- the principal object of the present invention is to provide a new and improved display control system and method of using it to enable one or more portions of a primary video image to be accentuated with an auxiliary light image continuously.
- Another object of the present invention is to provide such a new and improved display control system and method of using it to enable accentuating one or more desired portions of the primary image in a fast and convenient manner.
- Another object of the present invention is to provide such a new and improved display control system and method of using it, to accentuate selected portions of a primary image without the use of multiple projectors or special types of screen materials.
- Another object of the present invention is to provide such a new and improved display control system and method of using it, to enable accentuated portions of a primary image to be normalized either simultaneously or selectively in part by the deletion of one or more accentuating images.
- Another object of the present invention is to provide such a new and improved display control system and method of using it to accentuate selected portions of a primary image with an accentuating image having a desired color.
- a display control circuit causes the underlying primary image to be altered to include an accentuating image indicative of the path of travel followed by a spot of auxiliary control light as it is directed by a user via the hand held light wand.
- a color control circuit responsive to user input commands enables the
- An erase control circuit also responds to user input commands to enable the user entered accentuating images to be deleted selectively individually or in total simultaneously.
- FIG. 1A is a pictorial diagrammatic, partially broken away view of an integrated projector, which is constructed in accordance with the present invention
- FIG. 2A is a top plan diagrammatic view of the projector of FIG. 1A;
- FIG. 3A is a front elevational, diagrammatic view of the projector of FIG. 1A;
- FIG. 4A is a diagrammatic view of a portion of a finely faceted mirror of the projector of FIG. 1A, illustrating the principles of the present invention
- FIG. 5A is a diagrammatic view of an overhead projector, which is also constructed in accordance with the present invention.
- FIG. 6A is a top plan diagrammatic view of an integrated projector, which is constructed in accordance with the present invention.
- FIG. 1B is a diagrammatic view of a projection lens system which is constructed in accordance with the present invention and which is illustrated with a liquid crystal projector;
- FIGS. 2AB-2CB is a graphical representation of ray deflection of the projection lens arrangement of FIG. 1B for various FOB lengths where the conjugate is 5.6 feet in length;
- FIGS. 3AB-3CB is a graphical representation of ray deflection of the projection lens arrangement of FIG. 1B for various FOB lengths where the conjugate is 4.0 feet in length;
- FIGS. 4AB-4CB is a graphical representation of ray deflection of the projection lens arrangement of FIG. 1B for various FOB lengths where the conjugate is 10.0 feet in length;
- FIGS. 5AB-5CB are astigmatism, distortion, lateral color curves for the lens arrangement of FIG. 1B where the conjugate is 4.0 feet in length;
- FIGS. 6AB-6CB are astigmatism, distortion, lateral color curves for the lens arrangement of FIG. 1B where the conjugate is 5.6 feet in length;
- FIGS. 7AB-7CB are astigmatism, distortion, lateral color curves for the lens arrangement of FIG. 1B where the conjugate is 10.0 feet in length;
- FIG. 8B is a modulation verus frequency
- FIG. 9B is a modulation verus frequency
- FIG. 10B is a modulation verus frequency
- FIG. 1C is a block diagram of a display control system which is constructed in accordance with the present invention.
- FIG. 2C is a schematic diagram of the display control system of FIG. 1C;
- FIG. 3C is a timing control circuit of the display control system of FIG. 1C;
- FIG. 4C is a timing diagram of the clock signals generated by the timing control circuit of FIG. 3C;
- FIGS. 5C and 6C are fragmentary diagrammatic views of the liquid crystal display panel of FIG. 1C.
- FIGS. 7C and 8C are fragmentary diagrammatic views of the liquid crystal display panel of FIG. 1C
- FIG. 1D is a block diagram of a display control system which is constructed in accordance with the present invention
- FIG. 2D is a diagrammatic view illustrating in phantom various image panning positions corresponding to the workstation image of FIG. 1D;
- FIGS 3D-12D illustrate various image panning
- FIG. 13D is a top plan view of the remote control unit of FIG. 1D;
- FIG. 1E is a block diagram of a display control system which is constructed in accordance with the present invention.
- FIG. 2E illustrates a 640 ⁇ 480 low resolution personal computer monitor image displayed on a 1024 ⁇ 768 liquid crystal panel of FIG. 1E;
- FIG. 3E illustrates a 640 ⁇ 480 low resolution personal computer monitor image displayed as a zoomed image on the 1024 ⁇ 768 low resolution liquid crystal panel of FIG. 2E;
- FIG. 4E is a block diagram of the timing control circuit of FIG. 1E;
- FIG. 5E is a block diagram of the output logic arrangement of FIG. 1E;
- FIG. 6E is a greatly enlarged top plan view of the remote control device of FIG. 1E;
- FIG. 7E is a timing diagram of the clock signals generated by the timing control circuit of FIG. 4E;
- FIGS. 8E and 9E are fragmentary diagrammatic views of the liquid crystal display panel of FIG. 1E.
- FIGS. 10E and 11E are block diagrams of the output data logic devices of FIG. 5E;
- FIG. 1F is a block diagram of a display control system which is constructed in accordance with the present invention.
- FIG. 2F is a simplified flowchart diagram
- FIG. 3F is a fragmentary top plan view of the liquid crystal display panel of FIG. 1F;
- FIG. 4F is a diagrammatic view of a projected primary display image illustrating a tool bar without a color palette
- FIG. 5F is a diagrammatic view of another projected primary image illustrating a tool bar with a color palette
- FIG. 6F is a diagrammatic view of a menu window generated by the display control system of FIG. 1F;
- FIG. 7F is a diagrammatic view of a primary video display image illustrated without an accentuating image
- FIG. 8F is a diagrammatic view of the primary video display image of FIG. 7F illustrating an auxiliary light path of travel for forming a single accentuating image;
- FIG. 9F is a diagrammatic view of the primary video display image of FIG. 8F illustrating the accentuating image formed by the auxiliary light;
- FIG. 10F is a diagrammatic view of the primary video display image of FIG. 8F illustrated with a plurality of accentuating images
- FIG. 11F is a diagrammatic view of the primary video display image of FIG. 10F illustrated with one of the plurality of accentuating images erased;
- FIG. 12F is a diagrammatic view of the primary video display image of FIG. 8F illustrated another accentuating image. Best Mode for Carrying Out the Invention
- FIGS. 1A-6A of the drawings there is shown a projection illumination system 6A which is constructed in accordance with the present invention, and which is illustrated connected to a video signal producing system 7A including a personal computer 8A and monitor 9A.
- the system 6A is adapted to project computer generated images onto a projection illumination system 6A.
- the system 6A generally includes an integrated projector 10A having a base portion or housing 20A, confining a projection lamp assembly HA including a high intensity lamp 13A (as shown in FIG. 2) and a condenser lens assembly 26A, together with a pair of spaced-apart finely faceted mirrors 15A and 17A for directing the light from the assembly HA onto a lower light impinging surface of a horizontal liquid crystal display 24A, which serves as an image forming display device. Disposed above the liquid crystal display 24A is a top output mirror assembly 19A, and a projection lens system or assembly 22A, for facilitating the projection of an image onto a remote viewing surface (not shown) . This is just one possible orientation of the lens assembly 22A. Other orientations are possible, such as a vertically directed orientation.
- a display control system 25A responsive to the personal computer 8A, sends control signals to the display 24A.
- the display control system 25A includes various control logic for
- the liquid crystal panel 24A is supported by four legs, such as the leg 27A, enabling the housing 20A to have a low profile and thus be more compact.
- the liquid crystal display panel 24A is more fully described in U.S. patent application Serial No. 08/237,013 filed on April 29, 1994, which is incorporated herein by reference.
- transmissive and reflective spatial modulators or light valves which may be used in place of the liquid crystal display 24A.
- the lamp assembly HA including the condenser lens assembly 26A is mounted at a rear portion of the housing 20A and provides a source of high intensity projection light for passing through the liquid crystal display panel 24A.
- the finely faceted mirrors which will be described hereinafter in greater detail, form part of the inventive projection illumination arrangement for
- the faceted mirror directing light from the condenser lens assembly 26A, through the liquid crystal display panel 24A, to the top output mirror assembly 19A for projection via the lens assembly 22A.
- the faceted mirror In this regard, the faceted mirror
- the arrangement directs the horizontal, forwardly directed high intensity light within the housing 20A along an irregularly shaped light path extending from the mirror 15A perpendicularly to the mirror 17A and then upwardly through the liquid crystal display panel 24A.
- the projector 10A is positioned on a stationary surface, such as a table top (not shown) with a front portion of the housing disposed closest to the remotely located surface to receive the projected image.
- the personal computer 8A is coupled electrically to the display panel 24A via the display control system 25A for enabling computer generated images to be formed by the display panel 24A.
- Light from the condenser lens assembly 26A is directed by the faceted mirror arrangement along the irregularly shaped light path which extends from the condenser lens assembly 26A to the mirror 15A and
- the top output mirror assembly 19A and the projection lens assembly 22A projects reflectively the light image formed by the display panel 24A onto a viewing surface (not shown).
- the faceted mirror arrangement is disposed between the light source and the display panel, and the mirrors are constructed and arranged to reduce image distortion.
- the projection light from the condenser lens assembly 26A can be precisely directed onto the light impinging surface of the display panel 24A by adjusting its shape in both the X and Y dimensions as hereinafter described in greater detail.
- the light is confined in a compact space to reduce the overall size of the housing 20A.
- the faceted mirrors spread the light into a set of beam segments to form an overall beam of a generally rectangular cross-sectional configuration, which is generally similar to the size of the face of the display panel 24A.
- the faceted mirrors spread the light into a set of beam segments to form an overall beam of a generally rectangular cross-sectional configuration, which is generally similar to the size of the face of the display panel 24A.
- the mirror 15A is spaced sufficiently from the mirror 17A, which, in turn, is spaced sufficiently from the display panel 24A to permit the beam segments to diverge sufficiently to uniformly cover the bottom face of the display panel 24A with little or no dark or shadow areas.
- the image is then formed by the display panel 24A in a
- the assembly 11A generally includes a lamp housing unit 12A which is mounted at the rear portion of the housing 20A.
- the lamp housing unit 12A includes a high intensity lamp 13A (FIG. 2A) and a spherical reflector 14A, both of which direct the light generated thereby to the condenser lens assembly 26A, which includes condenser lens elements 21A, 22A and 23A, for directing the light toward the first faceted mirror 15A.
- the three lens elements are nested and curved, and are progressively larger in size as they are positioned further from the lamp 13A. It should be understood that other types and kinds of lamps may also be employed.
- the lamp housing unit 12A provides a means for mounting the condenser lens assembly 26A at a
- the faceted mirrors 15A and 17A are angularly spaced apart in close proximity to one another.
- the mirror 15A is vertically disposed and is positioned with its light impinging face at an angle to the horizontal collimated light emitted from the lamp 13A to reflect such light perpendicularly horizontally toward the mirror 17A.
- the faceted mirror 17A is inclined backwardly at an angle and is supported at its upper edge 17BA by a
- the mirror 17A is supported at its lower edge 17AA by an elongated support bracket 28A mounted on the housing 20A.
- the mirror 17A is positioned at a sufficient angle to reflect the incident horizontal beam perpendicularly vertically upwardly toward the bottom face of the horizontal display panel 24A for illuminating it.
- the faceted mirrors 15A and 17A have sufficiently finely spaced facets for segmenting the light being reflected from their surfaces. The resulting
- spaced-apart light beam segments are sufficiently closely spaced to cause them to diverge and fill in any dark or shadow spaces therebetween, before they impinge upon the .adjacent surface.
- this result is dependent on various factors, including the redirecting of light beams from the light source, the size of the light source, and the effective focal length of the condenser lens assembly 26A, for a given configuration of the angle of the mirror facets, the spacing of the individual facets, and the distance between each mirror and its adjacent component, such as the distance between the mirrors 15A and 17A, and the distance between the mirror 17A and the display panel 24A.
- the mirrors 15A and 17A are each similar to one another, and thus only the mirror 15A will now be
- the vertical mirror 15A includes a tapered back plate 15BA having on its face a series of angularly disposed facets, such as the facets 29A and 30A (FIG. 1A) projecting angularly outwardly therefrom.
- the facets extend vertically between the bottom edge 15AA and a top edge 15CA.
- the facets such as facets 37A and 39A, are each generally triangularly shaped in cross section, and are each similar to one another.
- the series of triangularly shaped facets are arranged in a side-by-side arrangement to provide a sawtooth
- Each one of the facets includes a sloping reflecting surface, such as the surface 37AA, which is integrally joined at an external corner edge, such as the edge 37BA, to a right angle surface 37CA.
- the reflecting surface serves to reflect the light from the lamp 13A toward the mirror 17A.
- the angularly disposed reflecting surface such as the surface 37AA, between its corner edge 37BA and an adjacent corner edge 39AA of a facet 39A disposed toward the lamp 13A, to help spread the light beam by separating it into separate beam segments, such as beam segments 40A and 50A.
- the mirrors 15A and 17A are sufficiently spaced apart to permit the beam segments to diverge and overlap or intersect before they impinge on the mirror 17A. In this regard, spaces or gaps between the beam segments are filled in prior to impinging the closest portion of the mirror 17A.
- the mirrors 15A and 17A are disposed at their closest portions at their forward portions thereof, as indicated in FIG. 4A at the forward end facets 37A and 39A.
- the mirrors 15A and 17A are positioned at their closest portions by a distance at least equal to a straight line distance indicated generally at 33A, sufficient to permit the diverging beam segments 40A and 50A to overlap or converge together at a vertical line 31A, before engaging the mirror 17A.
- the straight line distance 33A extends normal to the mirror at the vertical line 31A
- the beam segment 50A overlaps or intersects with its adjacent beam segment 60A at a vertical line 61A (shown as a point in FIG. 4A) .
- a vertical line 61A shown as a point in FIG. 4A.
- intersection are disposed within a vertical plane
- 35A generally indicated at 35A as a line, extending generally parallel to the plane of the back plate 15BA.
- the faceted mirror arrangement acts to spread the light in both the X and Y directions.
- Light from the lamp 13A is directed in a manner perpendicular to the lens assembly 26A surface toward the first faceted mirror 15A.
- the light is spread and enlarged in the Y direction as it is reflected from the finely faceted surface of mirror 15A in a precise manner to correspond to the Y dimension of the mirror 17A.
- the mirror 15A directs these Y direction spread apart light beam segments toward the second faceted mirror 17A.
- the second faceted mirror 17A then segments and spreads the light in the X direction
- the individual light beams diverge and intersect or slightly overlap just as they impinge on the surface of the underside of the liquid crystal display panel 24A.
- the light generated by the lamp 13A has been adjusted precisely in the X and Y directions to provide a compact and effective configuration for the projection equipment of FIG. 1A.
- the faceted mirrors 15A and 17A are arranged in close
- the overall configuration facilitates the construction of a very compact projector unit capable of employing a conventional lamp assembly such as assembly HA to generate high luminosity for projection illumination purposes in a highly efficient and effective manner.
- the light source has a finite extent, thelight rays from lamp 13 are distributed over an angular range instead of traveling parallel as shown
- the spacing between the mirrors 15A, 17A and the panel 24A can be adjusted so that the shadow areas between the beams are filled in before they impinge on the surface of the panel 24A (FIG. 1A). This is very important, as the LCD display panel 24A is where the image is formed and the presence of the shadow areas here would otherwise cause image distortion or other undesirable results.
- the internal components of the projector such as the mirrors 15A and 17A, the LCD panel 24A, the light source and the
- condenser lens assembly 26A should all be positioned as close together as possible to reduce light loss.
- the closest distance is represented by the line 38A.
- Angle A represents the degree of light spreading.
- Angle A is critical, because if angle A were smaller than as indicated in FIG. 4A, the two adjacent light beams 40A and 50A would not intersect at point 31A and the second mirror 17A surface, and therefore there would be a spacing or shadow area between the two adjacent light beams. Although not shown in FIG. 4A, the same would be true regarding the beams reflecting from the second mirror 17A to the LCD display panel 24A in FIG. 1A, when the light is reflected from the second mirror 17A onto the LCD panel 24A. Therefore, in accordance with the invention, the angle A is determined such that the shadow areas are eliminated, certainly once the reflected light impinges on the LCD panel 24A of FIG. 1A to form properly the image to be projected.
- the angle A is equal to the arc tangent of the size of the light source 13A, divided by the effective focal length of the condenser lens assembly 26A. This relationship is expressed as follows:
- the size of the light source is a dimension that can be determined by a measurement of a given light source
- the optical element is the lens assembly 26A. Therefore, by taking the arc tangent of the size of the light source, divided by the effective focal length of the condenser lens assembly, the angle A of the spreading of the light is determined so that the angles of the plane of the mirror 15A and its facets can be adjusted to cause the light beams to overlap at least within the shortest distance 38 as indicated in FIG. 4A.
- FIG. 5A there is shown an overhead projector 60A constructed in accordance with the present invention.
- the overhead projector 60A is generally similar to the apparatus of FIGS. 1A-3A, except that the projector 60A is adapted to project images formed by a transparency (not shown) or the like.
- the projector 60A includes a conventional mirror and projection lens assembly 62A mounted in place by means of a support arm 68A above an image forming display device in the form of a transparency supporting stage 64A (in place of the display panel 24A of FIG. 1A).
- a projection illumination arrangement 66A is disposed below the stage 64A.
- the projection illumination arrangement 66A is generally similar to the illumination system of FIG. 1A, and includes a high intensity light source 71A, a
- collimating lens (not shown), and two angularly disposed faceted mirrors 73A and 75A.
- the light emitted by the light source 71A is collected and directed toward the vertical faceted mirror 73A by a parabolic reflector (not shown) or a collimating lens, such as a 3-element condenser lens (not shown) .
- the light is then reflected from the surface of the vertical faceted mirror 73A toward the backwardly inclined upwardly faceted mirror 75A, and reflected therefrom vertically upwardly through the stage 64A.
- the light is segmented and spread in the X and Y dimensions in a similar manner as described in connection with the illumination system of FIG. 1A.
- the spacing between the mirrors 73A and 75A, and between the mirror 75A and the image forming device 64A are similar to the illumination arrangement of FIG. 1A.
- the stage 64A is positioned between the projector illumination arrangement 66A and the projection lens assembly 62A.
- the stage 64A aids in forming a desired image by supporting from below transparencies (not shown), separate liquid, crystal display panels (not shown), or the like.
- FIG. 6A there is shown another form of an overhead projector 100A, constructed in accordance with the present invention.
- the overhead projector 100A is generally similar to the apparatus of FIGS. 1A-3A, except that the lamp assembly 103A includes a high intensity lamp 101A having a parabolic reflector 107A instead of a condenser lens assembly.
- the lamp assembly generally includes a lamp housing unit 105A which is mounted at the rear portion of the projector housing (not shown) .
- the lamp housing unit 105A includes a high intensity lamp 101A and a parabolic reflector 107A disposed therebehind, which directs the light generated thereby toward the first faceted mirror 112A. It should be understood that other types and kinds of lamps may also be employed.
- the parabolic reflector 107A acts to collect and to redirect forwardly the light emitted by the high intensity lamp 101A in such a way that substantially all light beams are generally parallel. In this regard, as indicated in FIG. 6A, substantially all light rays generated by the lamp 101A travel in a
- the light beam directed from the parabolic reflector 107A also spreads angularly outwardly, and therefore, is not precisely parallel as a practical matter.
- the angle of spreading of the light beam must be adjusted in order to eliminate shadow areas between adjacent light beams being reflected from the faceted mirror 112A and 114A surfaces for the closest spacing between the mirror, and between the second mirror and the LCD panel. It has been determined for the projector 100A that the angle of spreading is equal to:
- the spacing or shadow areas between adjacent light beams can be substantially eliminated by adjusting the size of the light source or effective focal length of the parabolic reflector appropriately. Since there is some known aberration that occurs when a parabolic reflector is employed, a condenser lens assembly is preferred.
- FIGS. 1A, 2A and 3A are identical to FIGS. 1A, 2A and 3A.
- FIGS. 1B-10B of the drawings there is shown a projection lens system or assembly 10B which is constructed in accordance with the present invention.
- the projection lens system 10B is illustrated with a liquid crystal projector 12B can be employed as the projection lens system 22A of FIG. 1A, and in accordance with the method of the present invention can cause a liquid crystal image to be focused on a remote viewing surface, such as a remote viewing surface 16B.
- the projection lens system 10B generally comprises a projection lens arrangement 20B having a Tessar
- the lens arrangement 20B is similar to lens 22A and is coupled mechanically to a servo system 22B for adjusting the focal length of the lens
- the projection lens arrangement 20B generally includes three groups G1, G2 and G3 (FIG. 1B) of lens elements arranged along a common optical path P from an object end ⁇ to an image end I of the lens arrangement 20B.
- the lens arrangement 20B is disposed between an object surface S1 via a mirror surface S1A and an image surface S10.
- the first group, said second group and said third group having respective optical powers K1, K2 and K3, with an overall optical power of about 0.0037 inverse millimeter.
- the optical power K1 is about 0.00825 inverse millimeter.
- the optical power K2 is about - 0.01365 inverse millimeter.
- the optical power K3 is about 0.00783 inverse millimeter.
- the back focal length between the back vertex of the lens arrangement 20B and the object surface S1A is about twelve inches or about 254.6 millimeters.
- the object surface S1A is generally rectangular in shape having a corner to corner diagonal length of about 8.4 inches or about 106.68 millimeters. Based on the foregoing, those skilled in the art will understand the effective focal length of the lens arrangement is between about 10.24 inches or about 260.86 millimeter and about 11.00 inches or about 280.01 millimeters.
- the lens arrangement 20B In order to reach full field coverage of the object with good resolution, the lens arrangement 20B has a field coverage angle of up to about 22.1 degrees. In this regard, the resolution of the projection lens arrangement 20B is about 6 line pairs per millimeter.
- the vertex length of the projection lens arrangement 20B is about 1.81 inches or about 46.22 millimeters.
- the vertex length is adjustable and has an adjustment range between a short length of about 1.497 inches or about 38.02 millimeters and a full length of about 1.81 inches or about 46.22 millimeters.
- the aperture or speed of the projection lens arrangement 20B is about f/5.
- the lens elements are designated in their
- Groups G1 and G2 comprise the inventive projection lens.
- Lens L4 is a Fresnel lens. Also, in order to identify the sequence
- the surfaces are designated in their sequential positions as S2-S9 from the object end ⁇ to the image end I of the lens arrangement 20B.
- group G1 is configured in a doublet arrangement including the lens elements L1 and L2
- Lens elements L1 and L2 cooperate together to provide positive optical power where lens element L2 counter corrects lens aberrations introduced by lens element L1.
- lens element L1 in greater detail with reference to FIG. 1B, surface S3 is complementary to surface S4 of lens element L2 to permit the two lens elements L1 and L2 to be contiguous along their
- lens element L2 in greater detail with reference to FIG. 1B, surface S5 of lens element L2 is generally piano while surface S4 of lens element L2 is generally concave. As noted earlier, surface S4 is complementary to surface S3 of lens element L1.
- the function of lens element L2 is to balance the aberration of lens L1 and L3 by introducing overcorrected spherical aberration and astigmatism, as well as negative field curvature.
- group G2 includes a single lens element L3, having a lens stop LS.
- Lens element L3 is a bi-concave element of negative optical power for counter correcting lens aberration introduced by lens elements L1 and L2.
- Lens element L3 includes two surfaces S6 and S7 respectively, where each of the surfaces S6 and S7 are generally concave. The distance between surface S7 of lens element L3 and surface S8 of lens group G3 is variable.
- group G3 includes a single lens element L4 of positive optical power.
- the function of lens element L4 is to relay the height output from the projection lens groups G1 and G2.
- lens element L4 includes two surfaces S8 and S9.
- Lens surface S9 of lens element L4 is generally aspheric while surface S8 of lens element L4 is generally piano.
- the distance between surface S8 of lens element L4 and surface S7 of lens element L3 is variable as lens element L4 is mounted movably relative to lens element L3.
- the servo system 22B enables the lens element L4 to be moved rectilinearly along a track 26B by about .313 inches or about 8.20 millimeters.
- the lens arrangement 20B preferably has at least two aspheric surfaces as previously described, such as the surfaces S2 and S9.
- the aspherical surfaces may be defined by the following equation:
- X is a surface sag from the semi-aperture distance y from the axis or optical path P; that C is the curvature of a lens surface of the optical axis P equal to the reciprocal of the radius of the optical axis P; and that K is a conic constant (cc) or other surface of revolution.
- Tables 1B is an exemplary of the lens arrangement 20B embodying the present
- the lens arrangement of Table 1B has aspheric surfaces defined by the foregoing aspheric equation.
- the surface radius for each surface such as surface S2
- N d is the index of refraction
- V d is the Abbe number.
- Positive surface radii are struck from the right and negative radii are struck from the left.
- the object is to the left at surface SI of a liquid crystal display panel 24B.
- a lens as shown in FIG. 1B scaled for a 5.6 foot
- FIGS. 2AB-2CB there is illustrated the ray displacement caused by the lens arrangement 20B.
- FIG. 2AB illustrates ray displacement where the FOB is about 1.0 and a 5.6 foot conjugate.
- a pair of displacement curves 302B and 303B illustrates the ray displacement when the image wavelength is about 0.588 microns.
- a pair of displacement curves 304B and 305B illustrate the ray displacement when the image wavelength is about 0.486 microns
- a pair of displacement curves 306B and 307B illustrate the ray displacement when the image wavelength is about 0.656 microns
- a pair of displacement curves 308B and 309B illustrate the ray displacement when the image wavelength is about 0.436 microns.
- FIG. 2BB is similar to FIG. 2AB except the FOB is about 0.7.
- the pairs of ray displacement curves for wavelengths of 0.588; 0.486; 0.656; and 0.436 are
- FIG. 2CB is similar to FIGS. 2AB and 2BB except the FOB is about 0.0.
- the pairs of ray displacement curves for wavelengths of 0.588; 0.486; 09.656; and 0.436 are 322B,323B; 324B,325B; 326B,327B; and 328B,329B
- FIGS. 3AB-3CB and 4AB-4CB are similar to FIGS. 2AB-2CB and illustrate pairs of displacement curves for wavelengths of 0.588; 0.486; 0.656 and 0.436 relative to different FOB of 1.0, 0.7 and 0 respectively.
- the first character reference number identifying the curves in FIGS. 3AB-3CB and 4AB-4CB have been sequentially increased.
- a curve pair 402B and 403B correspond in description to the curve pair 302B and 303B.
- FIGS. 5AB-5CB; FIGS. 6AB-6CB and FIG. 7AB-7CB there is illustrated astigmatism, distortion and lateral color curves for the lens arrangement
- the respective astigmatism, distortion and lateral color curves are identified as 601B; 602B; 603B; 604B and 605B for the 4.0 foot conjugate, 701B; 702B; 703B; 704B and 705B for the 5.6 foot conjugate, and 801B; 802B; 803B; 804B and 805B for the 10.0 foot conjugate.
- FIG. 8B there is illustrated a series of modulation transfer function curves 901B-905B of the lens arrangement example having the 4.0 foot conjugate. Each curve depicted illustrates the
- modulation as a function of frequency (cycles per millimeter) .
- FIGS. 9B and 10B are similar to FIG. 8B and
- FIGS. 1C-8C of the drawings and more particularly to FIG. 1C thereof, there is shown a display control system 10C which is constructed in accordance with the present invention.
- the display control system 10C can be employed as the display control system 25A of FIG. 1A, and is illustrated coupled between a video signal producing device, such as a video output module 12C of a personal computer 14C and a display device, such as a liquid crystal display unit or panel 16C for displaying a compressed image defined by a matrix array of pixel images arranged in n number of rows and m number of columns.
- the number n is about 1024 and the number m is about 768.
- the display control system 10C generally includes a low speed sampling circuit 20C that converts an incoming analog RGB video data signal 18C, developed by the output module 12C, into a pixel data signal 21C for helping a compressed image to be displayed by the liquid crystal display unit 16C in a cost effective manner.
- the sampling circuit 20C includes a low cost, low speed, analog to digital converter arrangement that has a sampling rate which is substantially slower than the incoming rate of the video data signal which is typically between about 15 MHz and about 135 MHz.
- a timing circuit 22C develops various timing signals that enable the sampling circuit 20C to receive and convert the incoming video data signal into pixel data 21C that is indicative of a workstation image or image to be compressed defined by a matrix array of pixel images arrayed in N number of rows and M number of columns.
- the number N is about 1280 and the number M is about 1024.
- the sampling rate of the sampling circuit 20C is substantially slower than the incoming data rate of the video data signal 18C, it should be understood by those skilled in the art that during any given frame time period, only one-half of the pixel image information for any frame cycle is converted into pixel data. Thus, the whole workstation image is converted into pixel data once every two frame cycle periods.
- the display control system 10C also includes a programmable logic device or state machine 24C which is responsive to the timing circuit 22C for generating addressing or compression signals to help compress the whole workstation image on the fly into a compressed image that is displayed by the liquid crystal display unit 16C.
- the state machine 24C is driven by frame signals indicative of ODD frame time periods and EVEN frame time periods.
- One such state machine 24C was constructed using GAL logic. The actual program design of the GAL logic is shown in Appendix AC.
- the system 10C also includes a data output circuit 26C responsive to the timing logic circuit 22C and the programmable logic device 24C for causing only certain portions of the pixel data 21C to be gated to the liquid crystal display panel 16C each frame.
- the sampling circuit 20C converts the incoming video data signal 18C based upon whether a given frame cycle is an odd frame time period or cycle or an even frame time period or cycle and whether the video data signal being sampled is indicative of an odd pixel image in the M by N pixel image array or an even pixel image in the M by N pixel image array. More
- the sampling circuit 20C converts the video data signal indicative of odd pixel images on odd lines in the M by N matrix array and even pixel images on even lines for every even frame time period. Alternately, for every odd frame time period, the sampling circuit 20C converts the video data signal indicative of even pixel images on odd lines in the M by N matrix array and odd pixel images on even lines. In this manner, every analog pixel image signal embodied within the workstation-based image is converted into pixel data once every two frame time periods.
- the compression technique of the programmable logic device 24C also alternates between odd frame time periods and even frame time periods.
- the device 24C causes designated pairs of pixel image columns and designated pairs of pixel images within each rows to be averaged over every two frame cycle periods to produce a series of averaged or single pixel image columns and a series of averaged pixel image pairs.
- the averaged pixel image columns are indicative of a single pixel image column.
- the averaged pixel image pairs are indicative of a single pixel image.
- the above described compression technique does not involve composite pixel arrangements, nor expensive buffer memory devices. Instead, conversion of the incoming video data signal 18C into a compressed image is accomplished on the fly in a relatively inexpensive manner with simple buffer logic and low speed analog to digital converters.
- the sampling circuit 20C includes a set of analog to digital converter
- a sample clock signal 34C generated by a logic gating arrangement 36C enables the incoming analog signals to be converted at a predefined rate that allows only odd pixel image data to be converted during odd line, odd frame time periods and odd line, even frame time periods and only even pixel image data to be converted during even line, odd frame time periods and odd line, even frame time periods. In this manner, the image to be compressed, is sampled or converted on the fly at a rate that is substantially slower than the incoming data rate.
- each circled pixel image element such as an element 501C and an element 502C is indicative of a converted incoming analog signal during an odd frame time period.
- odd lines such as lines 1, 3, 5, . . . 1023
- even lines such as lines 2, 4, 6, . . . 1024 even pixel image data has been converted.
- FIG. 6C illustrates the conversion of the M by N matrix image data diagrammatically.
- each circled pixel image element such as an element 503C and an element 504C is indicative of the converted incoming analog signals during an even frame time period. More particularly, as best seen in FIG. 6C, during odd lines, even pixel image data has been converted and during even lines, odd pixel image data has been converted.
- the image formed by the panel 16C during the odd frame time period is combined with the image formed by the panel 16C during the even frame time period to be perceived by a viewer as a whole image in a substantially flicker free manner.
- the gating arrangement 36C generally includes a set of logic gates 101C-105C which implements the function of determining which pixel data is to be sampled or converted.
- a clock signal HOC will be passed by one of the gates 101C-104C to a logic OR gate 105C to cause the sample clock signal 34C to be generated.
- the device 24C generally includes a group of logic circuits 1000C-1512C and a multiplexor arrangement 42C for generating a line address or compression signal for causing the vertical portion of the image to be compressed from N lines to n lines.
- the logic circuits 1000C-1512C are embodied in gate array logic, and are shown in Appendix AC.
- the preferred language is ALTERA's Advanced Hardware Descriptive Language (AHDL).
- the logic circuits 1000C-1512C are arranged to cause certain lines or rows of pixel image data in the
- FIGS. 7C and 8C the averaging of lines of pixel image data is illustrated diagrammatically in greater detail.
- every third out of four rows or lines of pixel image data is eliminated such as a row 703C, 707C and 7HC.
- lines 3, 7, 11, etc. are eliminated.
- every fourth out of four rows or lines of pixel image data is eliminated such as a row 704C and 708C.
- lines 4, 8, 12 etc. are eliminated.
- the eliminated third and fourth line groups, such as line 3C and line 4C are adjacent to one another, the viewer perceives the resulting image as a combination of both the eliminated lines. Because the entire workstation-based image is actually displayed every two frame cycles, the resulting image is displayed without introducing any substantial stripping.
- the multiplexor arrangement 42C generally includes a plurality of groups of line address pair circuits.
- the odd frame time logic for gating lines 1, 2, 3 is multiplexed with the even frame time logic for gating lines 1, 2, 4 to permit lines 3 and 4 to be averaged.
- the multiplexor arrangement 42C includes a plurality of line address drivers (not shown) which are coupled to data output logic 26C by an address buss line 29C.
- the data output logic 26C generally includes a set 50C of frame buffer devices coupled to the address buss line 29C and a set 52C of multiplexors for assembling output data in odd and even byte pairs.
- the set 50C of frame buffer devices are responsive to pixel data converted by the sampling circuit 20C as well as the line address signals generated by the programmable logic device 24C.
- the set 50C of frame buffer devices enables certain adjacent columns of pixel image data to be averaged together over every two frame cycles to form sets of single pixel image columns.
- the set 50C of devices generally includes a group of logic circuits 60C-64C for generating •compression signals 70C-73C for causing the horizontal portion of the image to be compressed from M lines to m lines.
- the logic circuits 60C-64C are embedded in the previously mentioned GAL and are shown in Appendix AC.
- the logic circuits 60C-64C are arranged to cause certain columns of pixel image data in the workstation image to be eliminated during every odd frame cycle and certain other columns of pixel image data to be
- FIGS. 7C and 8C the averaging of columns of pixel image data is illustrated in greater detail.
- FIG. 7C during an odd frame time cycle, every four out of five columns of pixel image data is eliminated. Thus, columns 4, 9, 14 etc. are eliminated.
- FIG. 8C during the even frame time cycle, every fifth out of five columns of pixel image data is eliminated. Thus, columns 5, 10, 15 etc. are eliminated.
- the eliminated column groups such as columns 4 and 5 in the first group and columns 9 and 10 in the second group are adjacent to one another, the viewer perceives the
- the set 52C generally includes a pair of devices for sending odd and even pixel data information to the liquid crystal display unit 16C.
- multiplexor devices includes an odd multiplexor device 80C and an even multiplexor device 82C.
- multiplexor device 80C is coupled to the output of the logic circuits 60C and 62C.
- the even multiplexor device 82C is coupled to the output of the logic circuits 63C and 64C.
- logic circuits 60C-64C control compression for the columns indicated in Table IC.
- the output drivers of logic circuits 63C and 64C are enabled by a pair of logic signals, an ODD FRAME signal 220C and an EVEN FRAME signal 222C.
- FRAME signal 222C are conventional flip flops (not shown) and will not be described herein.
- the output signals from drivers 63C and 64C are connected together at a common node N and are coupled to the multiplexor 82C.
- the timing circuit 22C generally includes a phase
- VCO or pixel clock generator 200C for generating a reference or pixel clock signal 202C and a pair of unsynchronized clock generators, such as an odd clock generator 204C and an even clock generator 206C for generating a CLKA signal 205C and CLKB signal 207C respectively.
- a phase lock loop 201C causes the signals 205C and 207C to be synchronized relative to one another as best seen in FIG. 4C.
- a logic arrangement 208C consisting of a set of logic gates 210C-212C coupled to the clock generators 204C and 206C develop an output CLOCK signal 214C.
- the clock signal 214C is phase shifted once each frame cycle to enable odd pixel data to be sampled during one frame cycle period and even pixel data to be sampled during the next frame cycle period.
- the timing circuit also includes a group of logic elements (not shown) that generate an ODD line signal
- FIGS. 1D-13D of the drawings and more particularly to FIG. 1D thereof, there is shown a display control system 10D which is constructed in accordance with the present invention.
- the display control system 10D can be employed as the display control system 25A of FIG. 1A, and is illustrated connected to a personal computer 12D, having a video control module (not shown) for driving a workstation monitor 14D and a liquid crystal display monitor 16D simultaneously.
- the display control system 10D in accordance with the method of the present invention, can rewrite the video information from the personal computer 12D to both the workstation monitor 14D having an M by N or 1280 ⁇ 1024 pixel element matrix array and the liquid crystal display unit 16D having an m by n 1024 x 768 pixel element matrix array simultaneously.
- the display control system 10D compresses a workstation video image 14AD displayed on the workstation monitor 14D in such a manner so that substantially the entire 1280 ⁇ 1024 workstation image is displayed as a 1024 ⁇ 768 liquid crystal display image 16AD by the liquid crystal display panel 16D.
- the display control system 10D can control the liquid crystal display unit 16D to enable the workstation image 14AD to be panned in accordance with the method of the present invention.
- the display control system 10D generally includes a control circuit 20D that controls the sampling of an incoming analog RGB video data signal 15D, developed by the video control module in the personal computer 12D.
- the control circuit 20D causes only a selected portion of the incoming video data signal 15D to be sampled and converted into digital data by an analog to digital converter 18D.
- a control gate 34D under the control of the control circuit 20D, passes an A/D clock signal 36D that enables the analog to digital converter 18D to sample the incoming video data signal 15D for conversion purposes.
- the A/D clock signal 36D is synchronized with the
- a video data buffer RAM memory unit 19D coupled to the digital converter 18D by means not shown, stores the selected and converted portion of the video information, where the selected portion is indicative of a 1024 ⁇ 768 portion of 1280 ⁇ 1024 workstation video image.
- a user employing a remote control panning device 22D can select any 1024 ⁇ 768 portion of the 1280 ⁇ 1024 workstation image to be displayed on the liquid crystal display panel 16D.
- a microprocessor 24D coupled to the remote control panning device 22D via an infrared receiver 23D, causes the displayed portion of the workstation image to be changed in response to input command signals generated by the device 22D.
- a voltage controlled oscillator circuit or pixel clock generator 30D synchronized by an HSYNC signal 17D develops the pixel clock signal 32D for synchronizing the A/D clock signal 36D with the incoming video data signal 15D.
- the user via the remote control panning device 22D, causes a panning command signal to be transmitted to the
- the microprocessor 24D In response to receiving the panning control signal, the microprocessor 24D, via the control circuit 20D, causes the workstation image 16AD displayed on the liquid crystal display panel 16D to be changed. In this regard, only a central portion 100D (FIG. 10D) of the workstation image 14AD is displayed, where the central portion 100D is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines 129 to 896 of the workstation image 14AD and columns 129 to 1152 of the workstation image 14AD.
- the user via the remote control panning device 22D, can cause pan left, right, up and down signals to be
- the control circuit 20D In response to each pan left signal received by the microprocessor 24D, the control circuit 20D causes the displayed image to be changed column by column to a left central portion 102D of the workstation image 14AD, where the left portion 102D is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines 129 to 896 of the workstation image 14AD and columns (129-X L ) to (1152-X L ), where X L is a whole number integer between 1 and 128.
- the left central portion 102D is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines 129 to 896 of the workstation image 14A and columns 1 to 1024 of the workstation image 14AD.
- the control circuit 20D in response to each pan right signal received by the microprocessor 24D, causes the displayed image to be changed to a right central portion 104D of the workstation image, where the right portion 104D is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines 129 to 896 of the workstation image and columns (129 + X R ) to (1152 + X R ) , where X R is a whole number integer between 1 and 128.
- the right central portion 104D is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines 129 to 896 of the workstation image 14AD and columns 256 to 1280 of the workstation image 14AD.
- the control circuit 20D In response to each pan up signal received by the microprocessor 24D, the control circuit 20D causes the displayed image to be changed to an upper central portion 106D of the workstation image, where the upper portion is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines (129 _ Y u ) to (896 _ Y u ), where Y ⁇ is a whole number integer between 1 and 128.
- the upper central portion 106D is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines 1 to 768 of the workstation image 14AD and columns 129 to 1152 of the workstation image 14AD.
- the control circuit 20D in response to each pan down signal received by the microprocessor 24D, causes the displayed image to be changed to a lower central portion 108D of the workstation image 14AD, where the lower portion 108D is defined by a 1024 ⁇ 768 matrix array of pixel images indicative of lines
- the lower portion 108D is defined by a 1024 x 768 matrix array of pixel images indicative of lines 258 to 1024 of the workstation image 14AD.
- the displayed image was defined by a 1024 ⁇ 768 matrix array of pixel images, those skilled in the art will understand other matrix arrays of different sizes are contemplated within the scope of the invention.
- control circuit 20D generally
- the line control arrangement 40D comprises a line control arrangement 40D and a column or pixel control arrangement 50D.
- the line control 40D comprises a line control arrangement 40D and a column or pixel control arrangement 50D.
- the pixel control arrangement 50D determines which columns, in columns 1 to 1280 of the workstation image, will be displayed by the liquid crystal display 16D.
- the line control arrangement 40D generally includes a line hold off counter 42D and an active line counter 44D and a pair of decrement gates 43D, 45D which couple decrement pulses to each of the counters 42D and 44D respectively.
- the line hold off counter 42D is synchronized with the incoming video data signal 15D via a VSYNC signal 16D generated by the video module in the personal computer 12D.
- the line hold off counter is enabled by a VSYNC signal 17AD generated by the personal computer 12D.
- the line hold off counter 42D counts a predetermined Y number of display lines, following the VSYNC signal 17AD, to be inhibited from display.
- the microprocessor 24D upon receiving the pan command signal, causes the line hold off counter 42D to be loaded with an initialize Y count via a load signal bus 26D.
- the Y count equals the number of lines the workstation image can be panned either up or down.
- Y can be between a minimum number and a maximum number of lines capable of being panned up or down depending on the size of the screen. More particularly, Y is defined by equation (1D) that follows:
- Y Number of lines inclusive of VSYNC pulses
- the initialized value of Y depends upon both the screen size and the starting line number of the image.
- Y will be initialized to a value of 128 plus VSYNC pulses plus VSYNC blanking.
- the line hold off counter 42D is enabled causing its output to a logic LOW level disabling the active line counter 44D and the pixel control arrangement 50D.
- the line off counter 42D is then loaded with the initialize count of 128, which count is decremented once each time the HSYNC signal 17D goes to a logic HIGH level.
- a terminal count signal 46D is generated which in turn, enables both the active line counter 44D, and the pixel control
- the active line counter 44D When the active line counter 44D is enabled, it is decrement once for each occurrence of the HSYNC signal 17D after the terminal count signal 46D rises to a logic HIGH level.
- the active line counter 44D is initialized by the microprocessor 24D, via the load signal bus 26D, with a predetermined M number, where M is indicative of the total number of matrix display lines available on the liquid crystal display unit 16D. In this regard, the counter 44D is loaded with the number 768 via the load signal bus 26D.
- the microprocessor 24D is responsive to both the
- microprocessor 24D includes a conventional algorithm for determining the current position of the panel image relative to the corresponding workstation image. Based on this determination the microprocessor 24D causes the line control circuit 40D and the pixel control circuit 50D to be loaded with appropriate counts for inhibiting and enabling display of the user selected portion of the workstation image.
- the pixel control arrangement 50D generally includes a pixel hold off counter 52D and an active pixel counter 54D.
- the pixel hold off counter 52D is synchronized with the incoming analog video data signal 15D via the line hold off counter terminal count signal 46D and the pixel clock signal 32D.
- the pixel hold off counter 52D is enabled.
- the counter 52D is initialized by the microprocessor 24D which causes the counter 52D to be loaded with an initialize X count via the load signal bus 26D.
- the X count equals the number of columns the workstation image can be panned either left or right.
- X can be between a minimum number and a maximum number of columns capable of being panned either to the left or to the right depending on the size of the screen. More particularly, X is defined by equation (2D) that follows:
- the initialized value of X depends upon both the screen size and the starting pixel column number within the panned image. Thus, for example, to start from a center screen position with a screen size of 1024 by 768 pixels, X will be initialized to a value of 128 plus HSYNC pulses plus HSYNC blanking.
- the pixel hold off counter 52D When the pixel hold off counter 52D is enabled, it is decrement once for each occurrence of the pixel clock signal 32D. Thus, the output of the pixel hold off counter 52D will remain at a logic LOW level for 128 pixel clocks. When the pixel hold off counter 52D is decremented to zero, its output generates a start
- sampling signal 56D goes to a logic HIGH level which in turn, enables both the active pixel counter 54D and the A/D clock gate 34D.
- the active pixel counter 54D When the active pixel counter 54D is enabled, it is decremented once for each occurrence of the pixel clock signal 32D.
- the active pixel counter 54D is initialized by the microprocessor 24D, via the load signal bus 26D with a predetermined N number, where N is indicative of the total number of matrix display columns available on the liquid crystal display unit 16D.
- the counter 54D is loaded with the number 1024 via the load signal bus 26D.
- the active pixel counter 54D is enabled, it is decremented once for each occurrence of the pixel clock signal 32D.
- the counter 54D is decremented to a zero count, it generates a stop sampling signal 57D which in turn, causes the A/D clock gate 34D to be disabled.
- the A/D clock gate 34D is enabled only during that time period the pixel hold off counter start sampling sinal 56D is at a logic HIGH level.
- the remote device 22D generally includes a pan command key 302D which, when actuated cause a pan command to be sent to the
- control circuit will cause the compressed image 16AD as illustrated in FIG. 3D to be changed to a central pan image 100D
- FIG. 10D upon receipt of the pan command.
- the remote device 22D also includes a group 304D of panning keys that includes a pan left key 310D, a pan right key 311D, a pan up key 312D, and a pan down key 313D.
- a group 304D of panning keys that includes a pan left key 310D, a pan right key 311D, a pan up key 312D, and a pan down key 313D.
- any panning position as illustrated in FIGS. 3D-11D can be achieved.
- an upper left pan position 110D, an upper right pan position 111D, a lower left pan position 112D, and a lower right pan position 113D can be viewed as best seen in FIGS. 8D-9D and 11D-12D respectively.
- initialized values for X and Y with a screen size of 1024 by 768 pixels was specified for a centralized portion of the image to be panned. It will be understood by those skilled in the art that other initialized values of X and Y will result for different screen sizes. Thus, X and Y will be different for screen sizes of 1152 by 900 pixels, and the like.
- FIGS. 1E-HE of the drawings and more particularly to FIG. 1E thereof, there is shown a display control system 10E which is constructed in accordance with the present invention.
- the display control system 10E can be employed as the display control system 25A of FIG. 1A and is illustrated coupled between a video signal producing device, such as a personal computer 12E having a monitor 13E, and a display device, such as a liquid crystal display unit 15E. While the preferred embodiment of the present invention describes the use of a personal computer 12E, it will be understood by one skilled in the art that other devices including both high and low resolution devices will also perform satisfactorily.
- the liquid crystal display unit 15E includes a liquid crystal panel 16E (FIGS. 1E-3E) having a 1024 ⁇ 768 matrix array of pixel elements for displaying a monitor image 18E.
- the monitor image 18 can be either a virtually duplicated image 30E (FIG. 2E) of a personal computer monitor image 14E, or a zoomed image 31E (FIG. 3E) of the personal computer monitor image 14E.
- the duplicated image 30E is defined by a matrix array of pixel images arranged in n number of rows and m number of columns, while the zoomed image 31E is defined by a matrix array of pixel elements arranged in N numbers of rows and M number of columns.
- the numbers m and M are about 640 and 1024 respectively
- the numbers n and N are about 480 and 720
- the display system 10E enables a user (not shown) to view an image from the liquid crystal display panel 16E as either a virtually duplicated image of the computer monitor image 14E arranged in a matrix array of 640 ⁇ 480 pixels, such as image 30E, or as the
- the display control system 10E generally includes a low speed sampling arrangement indicated generally at 20E that helps convert an incoming analog RGB video data signal 119E developed by the personal computer 12E into a pixel data signal 21AE that is indicative of the 640 x 480 monitor image 14E.
- the sampling arrangement 20E includes a low cost, low speed analog to digital
- converter arrangement indicated generally at 21E that has a sampling rate which is sufficient to sample all of incoming video data indicative of the 640 ⁇ 480 computer image at least once each frame time period.
- the low speed sampling arrangement 20E also includes a timing control circuit 22E to develop various timing signals that enable the analog to digital converter arrangement 21E to convert the incoming video data signal 119E into pixel data 21AE arranged in a proper format for display on the panel 16E.
- the sampling arrangement 20E also includes a video RAM memory 23E that receives and stores the pixel data converted by the analog to digital converter 21E.
- the pixel data 21AE is stored as an array having the dimensions m ⁇ n, where m is about 1024 and n is about 768 for displaying image 30E, and m is about 1280 and n is about 512 for displaying zoomed image 31E. It will be understood by one skilled in the art that dimensions m ⁇ n of the array described are the preferred dimensions. However, other dimensions are contemplated and are within the scope of the present invention.
- data is retrieved from the memory 23E, it is formatted to be a centered 640 ⁇ 480 image, such as the image 30E displayed in the center of the upper portion of the
- the centered image 30E has the same pixel image configuration of 640 ⁇ 480 pixel images as the computer monitor image 14E, while the zoomed image 31E has an enlarged
- the display control system 10E also includes an output logic arrangement 24E which is responsive to the timing control circuit 22E for generating addressing or scaling signals to help either zoom the whole computer monitor image 14E into a zoomed image, such as the zoomed image 31E, or to merely duplicate the whole computer monitor image 14E as a centered image, such as the centered image 30E.
- the output logic arrangement 24E enables the pixel data 21AE to either be retrieved and displayed as 640 ⁇ 480 lines of display information, or to be scaled and displayed as 1024 ⁇ 720 lines of information, as will be explained hereinafter in greater detail.
- the display control system 10E also includes a microprocessor 29E coupled to a remote control zoom device 27E via an infrared receiver 28E, to cause the liquid crystal display panel 16E to display in response to input command signals generated by the device 27E, either the centered 640 x 480 image, such as the centered image 30E, or the zoomed image, such as the zoomed image 31E.
- a microprocessor 29E coupled to a remote control zoom device 27E via an infrared receiver 28E, to cause the liquid crystal display panel 16E to display in response to input command signals generated by the device 27E, either the centered 640 x 480 image, such as the centered image 30E, or the zoomed image, such as the zoomed image 31E.
- the microprocessor 29E initially detects the format of the incoming analog video data 119E to determine the size of memory required to store the analog video data 119E which has been converted in the memory 23E, for displaying both image 30E and zoomed image 31E. The microprocessor subsequently assigns the required memory space of memory 23E for temporarily storing the analog video data 119E which has been
- the sampling arrangement 20E causes the incoming analog video data 119E to be stored in the predetermined locations in the memory 23E. More particularly, the sampling arrangement 20E converts the video data signal 119E into digital pixel data 21AE while the video data RAM memory 23E stores the pixel data 21AE.
- a user employing the remote control zoom device 27E can select either a duplicate of the monitor image 14E to be displayed as a centered 640 ⁇ 480 image, such as the centered image 30E, or a zoomed 1024 ⁇ 720 image, such as the zoomed image 31E.
- the centered image 30E is displayed on panel 16.
- the user via the remote control zoom device 27E, causes a zoomed command signal to be transmitted to the microprocessor 29E.
- the microprocessor 29E In response to receiving the zoom command signal, the microprocessor 29E generates a zoom signal 191E to cause the centered image 30E displayed on the liquid crystal display panel 16E to be changed to the zoomed image 31E.
- the image changes from the centered image 30E having a 640 ⁇ 480 pixel format to a zoomed image 31E having a 1024 ⁇ 720 pixel format.
- the user via the remote control zoom device 27E, can cause a restore command signal to be transmitted to the zoomed image 31E.
- microprocessor 29E to restore the centered image 30E so a duplicate image of the computer image 14E can be viewed.
- the microprocessor 29E generates a restore signal 192E to cause the image 30E to be
- the centered image 30E is defined by a
- the zoomed image 31E will be displayed.
- the zoomed image is defined by a 1024 ⁇ 720 matrix array pixel image disposed in the 1024 ⁇ 768 matrix array at columns 1E to 1024E, and lines 1E to 720E, as defined by imaginary lines 95E and 96E respectively (FIG. 3E).
- both images 30E and 31E are both positioned at the upper edge of panel 16E in the preferred embodiment of the present invention, one skilled in the art will understand that the images 30E and 31E can be centered between the upper and lower edges of panel 16E.
- the displayed zoomed image 31E is defined by a 1024 ⁇ 720 matrix array of pixel images, those skilled in the art will understand other matrix arrays of different sizes are also contemplated and are within the scope of the invention.
- the video data signal 119E was defined as an analog signal.
- digital signals are also contemplated, thereby eliminating the need for conversion from an analog to a digital signal.
- an analog to digital converter is not required as such digital signals can be gated directly into a video data RAM memory.
- the remote device 27E generally includes a zoom up command key 302E which, when actuated, causes a zoom command to be sent to the
- microprocessor 29E will cause the centered image 30E as illustrated in FIG. 2E to be changed to the zoomed image 31E (FIG. 3E) upon receipt of the zoom command.
- the remote device 27E also includes a restore or zoom down key 310E.
- a restore or zoom down key 310E In operation, by actuating the key 310E, the zoomed down image 30E as illustrated in FIG. 2E can be achieved.
- the sampling arrangement 20E includes the analog to digital converter arrangement 21E for converting the incoming analog red, green and blue video signals into digital signals.
- a sample clock signal 36E generated by a logic gating arrangement indicated generally at 37E (FIG. 4E) enables the incoming analog signals to be converted at a variable rate that allows all of the pixel image data to be converted during odd frame time periods and all of pixel image data to be converted during even frame time periods.
- the incoming analog signals are converted at a normal rate when duplicate image 30E is desired, and are converted at a zoomed rate when the zoomed image 31E is desired.
- the gating arrangement 37E generally includes a set of logic gates 101E-103E to generate a SAMPLE CLOCK clock signal 36E to determine which pixel data is to be sampled or converted, as well as the rate at which the pixel data is to be sampled.
- the clock signal 36E is generated by the logic OR gate 103E.
- clock signal 36E will either be a PXCLK clock signal 34E from the gate 101E or a ZOOM CLOCK clock signal 136E from the gate 102E, respectively.
- the ZOOM CLOCK clock signal 136E has a frequency which is
- the input analog data 119E may be sampled during the zoom mode at twice the rate of the sampling during the restore mode. This results in the ability to sample the same pixel information two times, and then to store the same pixel information two times, side by side, in the memory 23E.
- a 640 ⁇ 480 image is converted into a 1280 ⁇ 480 image, which is then stored in the memory 23E for subsequent scaling operations, as will be discussed hereinafter in greater detail.
- the gating arrangement 37E further includes a VCO CLOCK vertical count clock 200E connected to the HSYNC signal 117E to generate the PXCLK pixel clock signal 34E.
- Pixel clock signal 34E cooperates with the restore command signal 192E from the microprocessor 29E at gate 101E to generate the restore mode input for the OR gate 103E, wherein gate 101E generates a signal substantially equal to PXCLK clock signal 34E.
- the zoom command signal 191E from the microprocessor 29E cooperates with the ZOOM CLOCK signal 136E at gate 102E to generate the zoom mode input for the OR gate 103E, wherein gate 102E generates a signal substantially equal to ZOOM CLOCK clock signal 136E.
- the ZOOM CLOCK clock signal 136E is generated by any well known method or device for doubling the frequency of a pixel clock signal 36E, such as PXCLK clock signal.
- a frame counter 45E is connected to HSYNC signal 117E and VSYNC signal 116E to generate ODD FRAME signal 220E and EVEN FRAME signal 222E for varying the output data from output logic arrangement 24E according to the even or odd status of the video frame being operated on, as described hereinafter in greater detail.
- either the restore signal 192E or the zoom signal 191E is activated.
- the gate 101E generates a restore mode signal substantially similar to PXCLK clock signal 34E.
- the gate 102E is deactivated.
- the OR gate 103E generates SAMPLE CLOCK clock signal 36E, which is substantially equal to PXCLK clock signal 34E, to selectively activate the analog to digital converter arrangement 21E.
- the gate 102E When activated, the gate 102E generates a zoom mode signal substantially similar to ZOOM CLOCK clock signal 136E. Simultaneously, the gate 101E is deactivated. The OR gate 103E then generates the SAMPLE CLOCK clock signal 36E, based on the zoom mode signal, to double the
- sampling rate for doubling the storage of each piece of pixel information converted from input analog data 119E.
- the memory 23E is connected to the microprocessor 29E by means not shown to control the storage of
- the memory 23E has a storage capacity large enough to accommodate an image from a high resolution device, such as a workstation having a pixel array dimension of 1280 ⁇ 1024.
- the microprocessor 29E detects the pixel array dimension of the input device image, such as image 18E, and assigns an appropriate number of locations within the memory 23E to accommodate the image 18E.
- the memory 23E performs two different functions according to the mode of operation selected by the user. For example, in the restore mode, the restore mode
- microprocessor 29E clears the entire memory 23E to eliminate extraneous data previously stored in the memory 23E. The microprocessor 29E then detects the array dimensions of the image 18E.
- the image 18E has an array of 640 ⁇ 480 while panel 16E has an array of 1024 ⁇ 768.
- microprocessor 29E determines the appropriate memory locations within the memory 23E necessary to recreate the image 16E within the memory 24E. In this regard, the microprocessor 29E sets up a storage array within the memory 23E having the same dimensions as the panel 16E, 1024 x 768. The portion of the array starting at column 193 to column 832, and row 1 to 480 are reserved by the microprocessor 29E for receiving the pixel data 21AE, while the remaining columns and rows remain cleared.
- the sampling arrangement 20E converts the incoming analog data 119E into the pixel data 21AE which is then stored in the reserved portion of the memory 23E.
- the image 30E is stored in the memory 23E, at the upper central portions of the 1024 ⁇ 768 array.
- the stored image 30E is then transferred to the panel 16E, wherein the duplicate image 30E is positioned on panel 16E between columns 193 and 832, and rows 1 and 480 as shown in FIG. 2E.
- the microprocessor In the zoom mode, the microprocessor initially clears the entire memory 23E.
- An array having dimensions of about 1280 x 512 is set aside in memory locations of the memory 23E to receive and store digital reproduction of the image 14E, wherein the number of columns of pixel information from the image 14E has been doubled while the number of rows remains the same.
- the microprocessor 29E reserves memory columns 1 to 1280 and rows 1 to 480 for storing the enlarged representation of image 14E.
- the sampling arrangement 20E converts the incoming analog data 119E into the pixel data 21AE, wherein the incoming pixel data 21AE is sampled twice during the frame to enable the memory 23E to store each piece of pixel information twice.
- the pixel data 21AE is stored in the reserved memory of memory 23E before being transferred to the output logic arrangement 24E for scaling to
- the memory 23E provides a means for temporarily reproducing the final image 18E to be displayed on panel 16E, including the empty space surrounding the image 30E, before transferring it for display in the restore mode.
- the memory 23E provides a means for temporarily reproducing the image 14E in an
- the arrangement 24E generally includes a pair of output data logic units 91E and 92E for causing the pixel data retrieved from the video ram memory 23E to be displayed in the 640 ⁇ 480 or 1024 ⁇ 720 formats of the restore mode or the zoom mode, respectively.
- a gate control circuit 90E gates the pixel data information to one of the units 91E or 92E depending upon which operating mode has been selected.
- a multiplexer 93E controls the data passed by either the logic unit 91E or 92E to the display 16E.
- the unit 91E generally includes a row logic device or
- programmable logic device 124E and a column logic device 126E for scaling the horizontal and vertical pixel data, respectively.
- the programmable logic device 124E generally includes a group of logic circuits 1000E-1767E and a multiplexer arrangement 142E for generating a line address signal 38E for causing the lines or rows of the image to be scaled from n lines to N lines.
- the logic circuits 1000E-1767E are embodied in gate array logic.
- the logic circuits 1000E-1767E are arranged to cause certain lines or rows of pixel image data in the computer, monitor-based image 14E to be repeated every odd frame cycle. During every even frame cycle, certain other lines or rows of pixel image data are repeated.
- Combining the odd frame cycle with the even frame cycle in an alternating manner causes some of the repeated lines from each cycle to overlap, thereby increasing the number of lines from n lines to N lines.
- logic circuit 1000E causes the line information stored in the memory 23E at line 2 or VL2 to be displayed twice, while the line information stored in memory 23E at line 1 or VL1 is displayed only once during an even frame cycle.
- logic circuit 1001E causes the line information stored in the memory 23E at line 1 or VL1 to be displayed twice, while the line information stored at line 2 or VL2 of the memory 23E is displayed only once.
- the first three lines of information displayed on panel 16E comprise lines VL1, VL2 and VL2, respectively, during the even frame cycle.
- the first three lines of information displayed on panel 16E comprise VL1, VL1 and VL2, respectively.
- lines VL481 through VL512 of memory 23 which were initially cleared by the microprocessor 29E are also converted by the same method to provide line information to address the remaining 48 lines of panel 16E.
- logic circuits 1766E and 1767E provide the final three lines of the 768 lines which can be displayed by panel 16E.
- FIG. 8E illustrates the pixel and line information generated by scaling logic unit 91E for display on panel 16E during an even frame cycle.
- the left side of the diagram contains two vertical columns which identify the associated line or row.
- the innermost column is identified by VIDEO RAM LINES VL which
- PANEL LINES PL represents the line number of the panel 16E that is displayed.
- logic circuit 1000E of FIG. 10E displays VL1, VL2 and VL2 as the first three display lines of panel 16E during the even frame cycle. This same display of lines VL1, VL2 and VL2 is shown in FIG. 8E, together with the corresponding displayed lines PL1, PL2 and PL3 of panel 16E. The pattern is repeated until lines VL511, VL512 and VL512 are displayed on panel 16E as lines PL766, PL767 and PL768.
- FIG. 9E illustrates the pixel and line information generated by scaling logic unit 91E for display on panel 16E during an odd frame cycle, and includes the same headings. However, during the odd frame cycle, the odd numbered lines stored in the memory 23E are repeated instead of the even numbed lines.
- the multiplexer arrangement 142E generally includes a plurality of groups of line address pair circuits.
- the even frame time logic for gating lines VL1, VL2, VL2 is multiplexed with the odd frame time logic for gating lines VL1, VL1, VL3 to permit stored lines VL1 and VL2 to be expanded into displayed lines PL1, PL2, and PL3.
- the stored lines are increased for display purposes by a ratio of 2 to 3.
- the multiplexer arrangement 142E includes a plurality of line address drivers (not shown) which are coupled to column logic device 126E by an address buss line 38E.
- the column logic 126E generally includes a set 51E of frame memory 23E devices coupled to the address buss line 38E and a set 52E of multiplexers 80E, 82E for assembling output data.
- the set 51E of frame memory 23E devices are responsive to pixel data retrieved from the memory 23E as well as the line address signals generated by the programmable logic device 124E.
- the set 51E of frame memory 23E devices enables certain adjacent columns of pixel image data to be averaged together over every two frame cycles to form sets of single pixel image columns.
- the logic circuits 60E-64E are arranged to cause certain columns of pixel image data stored in the memory 23E to be eliminated during every odd frame cycle and certain other columns of stored pixel image data to be eliminated during every even frame cycle.
- the two sets of eliminated columns are thus averaged together, to cause the number of columns to be compressed from 1280E columns to 1024E columns.
- FIGS. 8E and 9E include two rows of pixel information identification, V1DEO RAM PIXELS VP and PANEL PIXELS PP, to identify the stored column of pixel
- VL14 VL1279 are eliminated.
- adjacent columns of stored pixel image data are eliminated.
- stored columns VL5, VL10, VL15...VL1280 are eliminated.
- column VL4 is not displayed during the even frame cycle while stored column VL5 is displayed as pixel column PP4 of panel 16E.
- stored column VL5 is not displayed while the column VL4 is displayed as pixel column PP4.
- stored columns VL4 and VL5 alternate as displayed column PP4 allowing the viewer to perceive the resulting image as a combination of both columns VL4 and VL5.
- This pattern is repeated for all groups of five pixel columns, thereby permitting the columns to be scaled down from 1280 to 1024 columns.
- the set 52E generally includes a pair of multiplexer devices 80E and 82E for sending pairs of pixel data information to the liquid crystal display unit 16E.
- the set 52E of multiplexer devices includes multiplexer device 80E coupled to the output of the logic circuits 60E and 62E, and a multiplexer device 82E coupled to the output of the logic circuits 61E, 63E and 64E.
- the output signals from drivers 63E and 64E are connected together at a common node N and are coupled to the multiplexer 82E.
- logic circuits 60E-64E control scaling for the columns
- logic circuits 63E and 64E facilitates the scaling of stored pixel image data columns from 1280 to 1024 columns of displayed pixel image data.
- the scaling down of pixel image data from 1280 to 1024 requires a scaling down ratio of five to four.
- the desired scaling will be achieved.
- continuity between non-eliminated columns is maintained, thereby reducing any tearing effect a viewer might observe.
- the output drivers of logic circuits 64E and 63E are enabled by a pair of logic signals, an ODD FRAME signal 220E and an EVEN FRAME signal 222E.
- Logic signals 220E and 222E are generated by a frame counter 45E
- FIG. 4E are indicative of an ODD frame time period and an EVEN frame time period, respectively.
- the frame counter for generating the ODD FRAME signal 220E and the EVEN FRAME signal 222E is conventional flip flops (not shown) and will not be described herein.
- the output data logic unit 92E is similar to the scaling logic unit 91E and includes a row logic device 224E connected to a column logic device 226E by a line address bus.
- the row logic device 224E includes a group of logic circuits and multiplexers similar to those of row logic device 124E.
- the column logic device 226E includes a set of frame memory 23E devices and a set of multiplexers similar to those of column logic device 126E. However, unlike the row logic device 124E, the row logic device 224E does not perform a scaling function.
- the row logic device 224E merely retrieves stored line information from the memory 23E and transmits the line information to the panel 16E unchanged.
- column logic device 226E merely retrieves stored pixel information from the memory 23E and transmits the pixel information to the panel 16E unchanged.
- output data logic unit 92E facilitates the transfer of the image 14E, as it is stored in the memory 23E, from the memory 23E to the panel 16E, where the image 30E is displayed as a result.
- Appendix AE is a listing of the gate array logic utilized in an actual system of the present. invention which was built and tested, and which employed ALTERA'S Advanced Hardware Descriptive Language (AHDL).
- AHDL ALTERA'S Advanced Hardware Descriptive Language
- FIGS. 1F-12F of the drawings and more particularly to FIG. 1F thereof, there is shown a display control system 10F which is constructed in accordance with the present invention.
- the display control system 10F is illustrated connected to a computer system HF having a personal computer 16F and peripheral devices including a computer mouse 13F, a video monitor 15F, and a liquid crystal display panel 12F mounted on an overhead projector 2OF.
- the display control system 10F generally includes a signal processor 25F and a charge couple device or camera 14F that can be mounted conveniently on the housing of the overhead projector 20F or some other convenient location.
- the signal processor 25F is
- the signal processor 25F can be employed as the display control system 25A of FIG. 1A.
- liquid crystal panel 12F and the overhead projector 2OF can be an integrated arrangement, such as the integrated projector 10A of FIG. 1A.
- a video output port 17F in the personal computer 16F supplies via a video cable 23F primary video information signals indicative of a primary video image 50F to the video monitor 15F and the liquid crystal panel 12F simultaneously.
- the display control system 10F in accordance with the method of the present invention can, upon the command of a user, alter the primary video image 50F projected by the liquid crystal display projector 20F to include an auxiliary or
- the signal processor 25F is responsive to the camera 14F, processes auxiliary light information generated by a hand held light wand or light generating device 24F to generate an auxiliary light video image 8OF which in turn, as more fully described herein, is converted to an image accentuating signal via the display control system 10F to cause the accentuating video image.
- the image sensor 14F may alternatively be located in other locations, such as on the LCD panel 12F or in an integrated projector as more fully described in U.S.
- the signal processor 25F generally includes a microprocessor 30F that controls the display of auxiliary information.
- the signal processor 25F display control system 10F has at least four different modes of operation for controlling the display of auxiliary information, including a DRAW mode, an ERASE mode, an ERASE ALL mode and a COLOR SELECT mode, each of which will be described hereinafter in greater detail.
- the signal processor 25F also includes a 2:1 multiplex unit 40F for supplying the liquid crystal display panel 12F with RGB video data via a data cable 28F.
- a 2:1 multiplex unit 40F for supplying the liquid crystal display panel 12F with RGB video data via a data cable 28F.
- the RGB video data supplied to the panel 12F is either similar to the RGB video data generated by the personal computer 16F or is modified RGB video data that includes auxiliary video data for accentuating selected portions of the primary video image or for displaying menu information.
- the memory units 42F and 44F each contain RGB video information that is mapped into a matrix array that corresponds to the video image to be displayed. More specifically, the liquid crystal display panel 12F has a matrix array of 1024 by 768 pixel element.
- individual ones of the pixel elements are coupled to the multiplex unit 40F and are energized on and off in accordance with the output signals generated by the multiplex unit 40F.
- a GATE control signal 45F from the overlay bit map memory unit 42F remains at a logic LOW level permitting the data retrieved from the bit map memory unit 44F to be transferred to the multiplex unit 40F via a frame buffer data cable 44AF.
- information may or may not be stored in the overlay unit 42F.
- the absence of stored data in the overlay bit map memory unit 42F for any given memory address will cause the GATE control signal 45F to remain at a logic LOW level permitting the data retrieved from the frame buffer unit 44F to be transferred to the multiplexor unit 40F.
- the presence of stored data at any given address in the overlay unit 42F will cause the GATE control signal 45F to be at a logic HIGH level.
- the multiplexor 40F via an overlay data cable 42AF in place of the video information stored in the corresponding memory location in the frame buffer bit map memory unit 44F.
- the information in the corresponding memory location in the frame buffer bit-map memory unit 44F will be transferred to the multiplexor unit 40F.
- the display control system also includes a control panel pad 46F (Fig. 3F).
- the control panel 46F in the preferred embodiment is disposed on the liquid crystal display panel 12F.
- the control panel 46F can be located at other convenient locations, such as on a housing (not shown) for the display control system 10F.
- control panel 46F includes a set of control switches for helping to control the operation of the display control system 10F.
- control panel 46F includes a power on-off switch 48F for energizing the display control system 10F as well as the liquid crystal display panel 12F, and a menu select switch 49F that causes the liquid crystal display panel 12F to display a main menu window 60F
- a menu control switch indicated generally at 70F includes a set of arrow keys or buttons including an up control key 71F, a down control key 72F, a right control key 74F and a left control key 73F.
- the user 12AF activates the menu switch 49F, a top portion of the image projected upon the viewing screen 21F will be overlaid with the main menu window 60F.
- the user activates the control switches 71F-74F to move a menu selection bar or cursor 51F to a desired one of the menu items.
- the menu selection bar 51F when moved, causes the currently selected menu item to be highlighted.
- left and right control keys 73F and 74F respectively, cause the selection bar 51F to move across the main menu window 60F to a desired setting
- the up and down control keys 71F and 72F respectively cause the selection bar 51F to move up and down the main menu window 60F to a desired setting.
- the user 12AF After the user 12AF has positioned the selection bar 51F to a desired setting, the user using either the light wand 24F, or the mouse 13F, or the control pad 46F, as will be explained hereinafter in greater detail, causes the selected menu item to be activated.
- the main menu window 60F includes a plurality of different selections including a "CyclopsTM" selection 61F which allows the user to set up and control the
- the pop-up window 65F includes a "CyclopsTM" menu selection 65AF and a draw selection 65BF.
- the main menu window 60F is replaced with a draw window 80F (FIG. 4F) and the display control system 10F
- the draw window 80F includes a set of tool windows including a draw tool selection window 81F, an erase tool selection window 82F, an erase all selection window 83F, and a color selection window 84F.
- the draw tool selection 81F allows the user 12AF to use the light wand 24F to accentuate desired portions of the primary video image being displayed.
- the erase tool selection 82F enables the display control system 10F to be placed in the ERASE mode
- the erase all selection 83F enables the user to erase all of the accentuating images previously entered into the overlay memory 42F.
- the color selection 84F causes a set of color selection windows 90F-97F (FIG. 5F) to be displayed below the draw window 8OF.
- a user 12AF is enabled to accentuate any portion of a primary video image, such as a primary image 50BF (FIG. 7F), with an accentuating video image such as the accentuating image 52F (FIG. 9F).
- a primary video image such as a primary image 50BF (FIG. 7F)
- an accentuating video image such as the accentuating image 52F (FIG. 9F).
- the user causes the hand held light wand 24F to be energized and directs the light generated therefrom to form a spot of auxiliary light 60F on a desired location on the primary image 50BF, such as a desired point A.
- the user 12AF then activates the draw mode feature by depressing an activate feature switch 27F on the light wand 24F.
- the user 12AF moves the light wand 24F causing the spot of auxiliary light 60F to traverse a desired path of travel from, for example, point A to point B.
- the display control system 10F generates an image accentuation signal which is indicative of a representative path of travel which, in turn, causes an accentuating image corresponding to the representative path, such as the accentuating image 52F (FIG. 9F), to be displayed on the primary image 50BF.
- the auxiliary image 52F replaces that portion of the primary image previously defined by a given group of pixel elements that now define the auxiliary image 52F.
- the feature switch 27F is deactivated causing the spot of auxiliary light 60F to be
- the microprocessor 3OF determines that the auxiliary light 60F has been
- the display control system 10F causes the primary image 50BF to be altered to include the representative path of travel followed by the spot of auxiliary control light as it traversed from point A to point B.
- the path of travel was representative of a straight line, it should be understood that the path of travel can be any path, for example, the path can be a circle as defined by another accentuating image 57F (FIG. 12F).
- the user 12AF can create an illusion that the light wand 24F was used to draw or write on the projected primary image, such as the image 50BF.
- the user 12AF is able to select the color of the accentuating image, such as the color of accentuating image 52F.
- the user 12AF can select one of N number of different colors for each accentuating image, where N is equal to at least eight different colors.
- the user 12AF points the light wand 24F toward the projected window 8OF to cause a spot of auxiliary control light to be reflected in a desired one of the color selection window, such as in the color selection window 9OF.
- the user 12AF then activates the tool selection switch 27F which causes the color in the selected window, such as window 90F, to be selected.
- the user 12AF is able to erase selectively any accentuating image presently displayed on the primary image .
- the user causes the hand held light wand 24F to be energized and directs a spot of auxiliary light 62F to any location on an accentuating image, such as point C on the accentuating image 53F.
- the user 12AF then activates the erase mode feature by depressing the activate selected tool switch 27F on the light wand 24F. When the switch is depressed, the user moves the light wand 24F causing the spot of auxiliary light 62F to be superimposed on the accentuating image
- any part of an accentuating image may be deleted.
- accentuating image 54F, 55F and 56F can also be deleted.
- the user 12AF is able to erase all of the accentuating images displayed on a primary image.
- all of the accentuating images 52F-56F on the primary image 50BF as shown in FIG. 10F can be erased simultaneously to restore the displayed image to an unaccentuated image as shown in FIG. 7F.
- the user 12AF causes a tool bar 80F to be displayed on the liquid crystal display panel 12F by depressing a menu key or control button 49F on a control panel 46F forming part of the liquid crystal panel 12F.
- a menu window 60F is superimposed in the upper portion of the projected primary image, such as the image 50AF, as illustrated in FIG. 6F.
- the menu will remain on the projected image 50AF until the user 12AF depresses the menu key 49F a second time.
- the display control system 10F will cause the then active menu setting to be automatically stored in the memory (not shown) of the microprocessor 30F so that the next time the menu key 49F is depressed, the last selected menu will be displayed again.
- the user selects a CyclopsTM menu feature by using the select or arrow keys 70F on the control panel 46F.
- the user depresses one or more of the arrow keys 71F-74F to cause a menu curser 51F to move across the Cyclops menu 61F to a DRAW feature 65BF.
- the user 12AF then directs either a spot of auxiliary control light from the light wand 24F to the DRAW window 65BF, such as a spot 94F (FIG. 6F) and depresses and releases the activate feature switch 27F on the light wand 24F to emulate a mouse CLICK causing the menu window 60F to be replaced with a draw bar window 80F (FIG. 4F).
- the user 12AF then opens or activates the draw bar window 80F by directing another spot of auxiliary control light 95F (FIG. 4F) to an activate button image 86F and depresses and releases the switch 27F on the light wand 24F to emulate another mouse CLICK causing the draw bar window features to be made active.
- auxiliary control light 95F FIG. 4F
- auxiliary control light 96F (FIG. 5F) to the ERASE ALL window feature 83F and depresses and releases the switch 27F to emulate another mouse CLICK causing all the accentuating images 52F-57F to be deleted from the projected image 50BF.
- the last selected feature on the draw bar 80F will be stored when the menu is exited and will be highlighted by an accentuating image, such as an image 87F the next time the draw bar feature is selected.
- the user directs another spot of auxiliary control light 66F to a close bar 85F and depresses and releases the light wand switch 27F to emulate another mouse CLICK.
- the color selected will be displaced in the color select window 84F and an accenting image, such as the image 89F, will be superimposed on the color window 84F.
- the user 12AF causes another spot of auxiliary control light to be directed to the close bar 85F in the upper left portion of the draw window 8OF.
- a primary image such as the primary image 50BF is displayed.
- the user 12AF may now utilize the light wand 24F to draw one or more accentuating images on the primary image.
- the program returns to the program entry instruction 102F and proceeds as previously described.
- the program advances to a command instruction 106F which activates the display control system 10F to interact with auxiliary light information produced by the light wand 24F.
- the program After activating the system 10F for interaction, the program proceeds to a draw mode instruction 108F that causes the draw mode window 80F to be displayed by the panel 12F. The program then advances to a decision instruction 110F to determine whether or not the user 12AF has activated the menu selection key 49F.
- the program advances to a decision instruction 112F to determine whether or not the user has activated the tool switch 27F. If switch 27F has not been activated, the program returns to the draw mode instruction 108F and proceeds as previously described.
- FIG. 2BF to determine whether or not the user 12AF elected to close the draw mode window by selecting the close bar 85F.
- the program returns to the main menu mode instruction 102F. If the user has not elected to close the draw mode, the program advances to a decision instruction 116F to determine whether or not the user has elected to open the draw mode features by selecting the open triangle 86F.
- the program goes to a decision instruction 118F to determine whether or not the color select feature was selected. If the palette is not displayed, the program goes to command instruction 121F which causes the color palette windows 90F to 97F to be displayed. If the color palette was displayed, the program goes to a command instruction 120F which causes the color palette windows 90F to 97F to be deleted from the projected image.
- command instruction 124F to activate the draw feature commands.
- command instruction 124F After command instruction 124F has been completed, the program proceeds to a decision instruction 126F.
- the program advances to the decision instruction 126F to determine whether or not the erase feature has been selected.
- the program advances to a decision instruction 130F to determine whether or not the color selection feature has been selected. If at decision instruction 126F it is determined that the erase feature was selected, the program advances to a command instruction 128F which activates the erase selective feature. After instruction 128F is executed, the program goes to the decision instruction 130F
- the program proceeds to a command instruction 132F which causes the color selection to be changed.
- the command 132F also causes the color palette windows to be deleted from the display image.
- the color window 84F will now display the last user selected color.
- the program then goes to a decision instruction 134F to determine whether a new page is required where all accentuating images are to be deleted.
- the program proceeds to the instruction 134F.
- instruction 134F if it is determined the erase all feature was selected, the program goes to command instruction 136F which causes all of the accentuating information in the overlay buffer memory unit 42F to be erased.
- the program goes to the decision instruction 142F to determine if the erase feature is active.
- the program advances to a command instruction 144F which clears all the overlay bit map memory locations for those pixel elements from the last accentuating image x, y coordinates values to the detected or mouse x, y coordinate values.
- the program then advances to instruction 108F and proceeds as previously described.
- the program also proceeds to instruction 106F.
- DRAW mode features are described as operating interactively with the light wand 24F, it will be understood by those skilled that control codes entered via the mouse 13F or the control pad 46F can also be communicated to the display control system 10F via the RS232 serial port interface 18F to cause the same draw mode commands to be executed.
- FIGS. 2AF-2CF are high level flow charts.
- Appendix AF attached hereto and incorporated herein, includes a complete source code listing for all of the draw mode commands described herein as well as the operation of the menu feature via the mouse 13F, the keyboard 19F and/or the light wand 24F.
- cvcnfrm Icvcnfnn ; % an even frame bit ON/OFF %
- count[ ] count[ ] + 1 ;
- count[ ] count[ ] + 2 ;
- count[ ] count[ ]
- zoom & preview THEN control zoml; % Zoom mode for VGA and Video %
- control upcl; % zoom mode or %
- count[] count[] + 1 ;
- count[] count ⁇ - 1 ;
- const ITEM li_tb15 ⁇ IT0.110,95.140,125.
- const ITEM Ii_tb7 ⁇ IT0,110,25,140,55,
- const ITEM Ii_tb2 ⁇ &i_tb3.20,0,120.20.
- DoPointerEvent() Process local Cyclops and Mouse data.
- OVLColor 0VL_BLACK
- OVLColor 0VL_WHITE
- OVLPixOp PIX_NORMAL
- buttons & SELECT MASK are buttons & SELECT MASK.
- MGrp.BoxXI MGrp.XPos- MGrp.Xofs;
- MGrp.BoxYI MGrp.YPos + MGrp.Yofs;
- OVLPixOp PIX_XOR
- OVLColor OVL BLACK
- OVLColor OVL_WHITE
- OVLPixOp PIX_NORMAL
- MGrp.Fir ⁇ tMe ⁇ u->X1 MGrp.BoxX1;
- MGrp.FirstMenu->X2 (MGrp.BoxX1 + MGrp.BoxW);
- MGrp.Fir ⁇ tMenu->Y2 (MGrp.BoxY1 + MGrp.BoxH);
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Transforming Electric Information Into Light Information (AREA)
- Projection Apparatus (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7509406A JPH09503313A (en) | 1993-09-17 | 1994-09-16 | Small projection lighting device and image projection method |
EP94928631A EP0719421A1 (en) | 1993-09-17 | 1994-09-16 | Compact projection illumination system and method of using same |
AU77994/94A AU7799494A (en) | 1993-09-17 | 1994-09-16 | Compact projection illumination system and method of using same |
Applications Claiming Priority (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/123,133 US5483382A (en) | 1993-05-11 | 1993-09-17 | Projection lens and method of using same |
US08/123,133 | 1993-09-17 | ||
US23529294A | 1994-04-29 | 1994-04-29 | |
US08/235,292 | 1994-04-29 | ||
US08/237,013 US5459484A (en) | 1994-04-29 | 1994-04-29 | Display control system and method of using same |
US08/237,013 | 1994-04-29 | ||
US08/247,720 US5682181A (en) | 1994-04-29 | 1994-05-23 | Method and display control system for accentuating |
US08/247,720 | 1994-05-23 | ||
US28601094A | 1994-08-04 | 1994-08-04 | |
US08/286,010 | 1994-08-04 | ||
US08/306,366 US5510861A (en) | 1993-05-11 | 1994-09-15 | Compact projector and method of using same |
US08/306,366 | 1994-09-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1995008132A1 true WO1995008132A1 (en) | 1995-03-23 |
Family
ID=27557997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1994/010622 WO1995008132A1 (en) | 1993-09-17 | 1994-09-16 | Compact projection illumination system and method of using same |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0719421A1 (en) |
JP (1) | JPH09503313A (en) |
AU (1) | AU7799494A (en) |
CA (1) | CA2171961A1 (en) |
WO (1) | WO1995008132A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0851401A2 (en) | 1996-12-27 | 1998-07-01 | Matsushita Electric Industrial Co., Ltd. | Width adjustment circuit and video image display device employing thereof |
WO2000079791A1 (en) * | 1999-06-17 | 2000-12-28 | 3M Innovative Properties Company | Freeze-frame function in an electronic projection system |
EP1100277A1 (en) * | 1999-11-12 | 2001-05-16 | International Business Machines Corporation | Devices with embedded projectors |
USRE41522E1 (en) | 1995-10-20 | 2010-08-17 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
CN101375313B (en) * | 2006-01-24 | 2012-10-31 | 诺基亚公司 | Compression of images for computer graphics |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5767444B2 (en) | 2010-06-16 | 2015-08-19 | ソニー株式会社 | Light source device and image projection device |
JP6388051B2 (en) * | 2017-04-05 | 2018-09-12 | ソニー株式会社 | Light source device and image projection device |
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-
1994
- 1994-09-16 JP JP7509406A patent/JPH09503313A/en not_active Withdrawn
- 1994-09-16 EP EP94928631A patent/EP0719421A1/en not_active Withdrawn
- 1994-09-16 CA CA 2171961 patent/CA2171961A1/en not_active Abandoned
- 1994-09-16 WO PCT/US1994/010622 patent/WO1995008132A1/en not_active Application Discontinuation
- 1994-09-16 AU AU77994/94A patent/AU7799494A/en not_active Abandoned
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US4006971A (en) * | 1973-02-16 | 1977-02-08 | Polaroid Corporation | Reflective imaging apparatus |
US3905686A (en) * | 1974-10-18 | 1975-09-16 | Eastman Kodak Co | Three element projection lens |
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US4487484A (en) * | 1982-09-16 | 1984-12-11 | Olympus Optical Co., Ltd. | Behind-stop Tesser type lens system |
US4916747A (en) * | 1983-06-06 | 1990-04-10 | Canon Kabushiki Kaisha | Image processing system |
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US5138490A (en) * | 1989-04-29 | 1992-08-11 | Carl-Zeiss-Stiftung | Arrangement for changing the geometrical form of a light beam |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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USRE41522E1 (en) | 1995-10-20 | 2010-08-17 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
USRE42656E1 (en) | 1995-10-20 | 2011-08-30 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
USRE43641E1 (en) | 1995-10-20 | 2012-09-11 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
EP0851401A2 (en) | 1996-12-27 | 1998-07-01 | Matsushita Electric Industrial Co., Ltd. | Width adjustment circuit and video image display device employing thereof |
WO2000079791A1 (en) * | 1999-06-17 | 2000-12-28 | 3M Innovative Properties Company | Freeze-frame function in an electronic projection system |
EP1100277A1 (en) * | 1999-11-12 | 2001-05-16 | International Business Machines Corporation | Devices with embedded projectors |
US6371616B1 (en) | 1999-11-12 | 2002-04-16 | International Business Machines Corporation | Information processing miniature devices with embedded projectors |
CN101375313B (en) * | 2006-01-24 | 2012-10-31 | 诺基亚公司 | Compression of images for computer graphics |
Also Published As
Publication number | Publication date |
---|---|
JPH09503313A (en) | 1997-03-31 |
CA2171961A1 (en) | 1995-03-23 |
EP0719421A1 (en) | 1996-07-03 |
AU7799494A (en) | 1995-04-03 |
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