WO1995005675B1 - Method of forming electrically conductive polymer interconnects on electrical substrates - Google Patents
Method of forming electrically conductive polymer interconnects on electrical substratesInfo
- Publication number
- WO1995005675B1 WO1995005675B1 PCT/US1994/009227 US9409227W WO9505675B1 WO 1995005675 B1 WO1995005675 B1 WO 1995005675B1 US 9409227 W US9409227 W US 9409227W WO 9505675 B1 WO9505675 B1 WO 9505675B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bond pads
- substrate
- electrically conductive
- forming
- bumps
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract 50
- 229920001940 conductive polymer Polymers 0.000 title claims abstract 20
- 239000011241 protective layer Substances 0.000 claims abstract 15
- 238000000608 laser ablation Methods 0.000 claims abstract 4
- 239000011253 protective coating Substances 0.000 claims abstract 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 230000002093 peripheral Effects 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 229920001169 thermoplastic Polymers 0.000 claims 1
- 229920001187 thermosetting polymer Polymers 0.000 claims 1
- 239000004416 thermosoftening plastic Substances 0.000 claims 1
Abstract
A method is presented for forming a bumped substrate and for forming an electrical circuit which includes the bumped substrate. The method of forming the bumped substrate includes forming at least one electrically conductive polymer bump on each of a first set of bond pads of the substrate. At least one electrically conductive polymer bump is then formed on each of a second set of the bond pads of the substrate. The circuit is formed by selectively forming an organic protective layer around the bond pads of a second substrate by laser ablation of an organic protective coating on the second substrate. The electrically conductive polymer bumps on the first and second portions of the bond pads of the first substrate are then contacted with the bond pads of the second substrate, thereby forming the electrical circuit.
Claims
1. A method of forming interconnection bumps on bond pads of a substrate, comprising the steps of:
a) forming an electrically conductive polymer bump on each of a first set of bond pads of the substrate; and thereafter
b) forming an electrically conductive polymer bump on each of a second set of bond pads of the substrate, and
wherein at least one bond pad of the first set is located between two bond pads of the second set.
2. A method of forming interconnection bumps on bond pads of a substrate, comprising the steps of:
a) aligning a first template over the substrate, said first template having openings which coincide with each of a first set of bond pads of the substrate;
b) forming bumps of electrically conductive polymer on the first set of bond pads by directing the electrically conductive polymer through said aligned
openings of the first template and onto each of said
first set of bond pads;
c) removing the first template from the
substrate;
d) aligning a second template over the substrate, said second template having openings which coincide with each of a second set of bond pads of the substrate;
e) forming bumps of electrically conductive
polymer on the second set of bond pads by directing the electrically conductive polymer through said aligned
openings of the second template and onto each of said
second set of bond pads; and
f) removing the second template from the substrate.
3. A method of Claim 2 wherein the electrically conductive polymer bumps are formed on the bond pads of a flip chip.
4. A method of Claim 2 wherein the electrically conductive polymer bumps are formed on the bond pads of a multichip module.
5. A method of Claim 2 wherein the electrically conductive polymer bumps are formed on the bond pads of a lead frame.
6. A method of Claim 2 wherein the electrically conductive polymer bumps are formed on the bond pads of a printed circuit board.
7. A method of claim 2 wherein the electrically conductive bumps are formed on bond pads that are arranged in a peripheral pattern on the substrate.
8. A method of Claim 2 wherein the electrically conductive bumps are formed on bond pads that are arranged in a staggered pattern on the substrate.
9. A method of Claim 2 wherein the electrically conductive bumps are formed in bond pads that are arranged in a array on the substrate.
10. A method of Claim 2 wherein the average distance between bond pads of the first portion and bond pads of the second portion is between about one and six mils.
11. A method of Claim 2 wherein thermoplastic electrically conductive polymer bumps are formed on the bond pads.
12. A method of Claim 2 wherein the B-stage polymer electrically conductive bumps are formed on the bond pads.
13. A method of Claim 2 wherein thermoset electrically conductive polymer bumps are formed on the bonds pads.
14. A method of Claim 2 further including the step of forming an organic protective layer over a surface of the substrate.
15. A method of Claim 2 further including the steps of aligning the electrically conductive bumps with the bond pads of a second substrate and then contacting the electrically conductive polymer humps with the bond pads of said second substrate, thereby forming electrical interconnections between said substrates.
16. A method of claim 2 further including the steps of selectively forming an organic protective layer on a second substrate which leaves bond pads on said second substrate exposed, and then contacting the electrically conductive polymer bumps with the bond pads of said second substrate, thereby forming electrical interconnections between said substrates.
17. A method of Claim 16 wherein the organic protective layer is selectively formed by coating the second substrate with the organic protective layer and then removing portions of the organic protective layer which cover the bond pads of said second substrate.
18. A method of Claim 17 wherein the portions of the organic protective layer which cover the bond pads are removed by laser ablation.
19. A method of selectively forming an organic protective layer on a substrate having bond pads,
comprising the steps of:
a) coating the substrate and the bond pads with an organic protective layer; and
b) removing portions of the organic protective layer which covers the bond pads of the substrate.
20. A method of claim 19 wherein portions of the organic protective layer which cover the bond pads are removed by laser ablation.
21. A method of forming an electrical circuit, comprising the steps of:
a) forming electrically conductive bumps on bond pads of a first substrate;
b) selectively forming an organic protective layer on a second substrate leaving bond pads of the second substrate exposed; and
c) contacting the electrically conductive bumps with the bond pads of the second substrate, thereby forming electrical interconnections between said
substrates.
22. A method of forming an electrical circuit, comprising the steps of:
a) forming electrically conductive bumps on bond pads of a first substrate;
b) selectively forming an organic protective layer on a second substrate, leaving bond pads of the second substrate exposed; and c) contacting the electrically conductive bumps with the bond pads of the second substrate, thereby forming electrical interconnections between said substrates, and
wherein the electrically conductive bumps are formed on the bond pads of the first substrate by a method comprising the steps of:
a) forming an electrically conductive polymer bump on each of a first set of bond pads of the first substrate; and
b) forming an electrically conductive polymer bump on each of a second set of bond pads of the first substrate.
23. A method of Claim 22 wherein at least one bond pad of said second set is located between at least two bond pads of said first set.
24. A method of Claim 23 wherein the organic protective layer is formed by forming an organic protective coating on the second substrate and then removing the portion of the organic protective layer which covers the bond pads by laser ablation.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE69421539T DE69421539T2 (en) | 1993-08-17 | 1994-08-15 | METHOD FOR SHAPING ELECTRICALLY CONDUCTING POLYMER COMPOUNDS ON ELECTRONIC SUBSTRATES |
| EP94925280A EP0714553B1 (en) | 1993-08-17 | 1994-08-15 | Method of forming electrically conductive polymer interconnects on electrical substrates |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10749893A | 1993-08-17 | 1993-08-17 | |
| US08/107,498 | 1993-08-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1995005675A1 WO1995005675A1 (en) | 1995-02-23 |
| WO1995005675B1 true WO1995005675B1 (en) | 1995-05-26 |
Family
ID=22316935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1994/009227 WO1995005675A1 (en) | 1993-08-17 | 1994-08-15 | Method of forming electrically conductive polymer interconnects on electrical substrates |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0714553B1 (en) |
| DE (1) | DE69421539T2 (en) |
| WO (1) | WO1995005675A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19639934A1 (en) * | 1996-09-27 | 1998-04-09 | Siemens Ag | Method for flip-chip contacting of a semiconductor chip with a small number of connections |
| EP0849983B1 (en) * | 1996-12-20 | 2001-10-24 | Alcatel | Process to create metallic stand-offs on a circuit board |
| US7297572B2 (en) | 2001-09-07 | 2007-11-20 | Hynix Semiconductor, Inc. | Fabrication method for electronic system modules |
| US6927471B2 (en) | 2001-09-07 | 2005-08-09 | Peter C. Salmon | Electronic system modules and method of fabrication |
| US6982191B2 (en) | 2003-09-19 | 2006-01-03 | Micron Technology, Inc. | Methods relating to forming interconnects and resulting assemblies |
| US10795452B2 (en) * | 2018-02-07 | 2020-10-06 | Microsoft Technology Licensing, Llc | Multi-stage cure bare die light emitting diode |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279773A (en) * | 1975-12-26 | 1977-07-05 | Seiko Epson Corp | Bonding method of ic |
| JPS56167340A (en) * | 1980-05-27 | 1981-12-23 | Toshiba Corp | Junction of semicondctor pellet with substrate |
| JPS62283644A (en) * | 1986-05-31 | 1987-12-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63151031A (en) * | 1986-12-16 | 1988-06-23 | Matsushita Electric Ind Co Ltd | Connection of semiconductor device |
| JPH0254945A (en) * | 1988-08-19 | 1990-02-23 | Toshiba Corp | Electronic part |
| US5074947A (en) * | 1989-12-18 | 1991-12-24 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
| MY129942A (en) * | 1990-08-23 | 2007-05-31 | Siemens Ag | Method and apparatus for connecting a semiconductor chip to a carrier. |
| DE4032397A1 (en) * | 1990-10-12 | 1992-04-16 | Bosch Gmbh Robert | METHOD FOR PRODUCING A HYBRID SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE PRODUCED BY THE METHOD |
-
1994
- 1994-08-15 WO PCT/US1994/009227 patent/WO1995005675A1/en active IP Right Grant
- 1994-08-15 DE DE69421539T patent/DE69421539T2/en not_active Expired - Fee Related
- 1994-08-15 EP EP94925280A patent/EP0714553B1/en not_active Expired - Lifetime
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