WO1994016501A1

WO1994016501A1 - Sigma-delta type analogue-to-digital converter

Info

Publication number: WO1994016501A1
Application number: PCT/FR1994/000022
Authority: WO
Inventors: Philippe Benabes; Daniel Billet; Alain Gauthier
Original assignee: Thomson-Csf
Priority date: 1993-01-15
Filing date: 1994-01-07
Publication date: 1994-07-21
Also published as: FR2700648A1; FR2700648B1

Abstract

In sigma-delta type baseband converters including two cascade stages, the converter input signal (e1) is applied in parallel to all adders (501, 511, 521) in the first cascade stage, and a resonator (522) is used instead of an integrator in the second cascade stage, whereby noise in the useful band may be reduced and two or more bits may be gained on the useful signal.

Description

Σ Δ TYPE ANALOG-TO-DIGITAL CONVERTER

The present invention relates to analog-digital converters, which make it possible, from an analog signal, to obtain a digital signal representing this analog signal. This digital signal can then be processed in a particularly powerful and efficient manner. The invention is more particularly useful in Σ Δ converters operating in baseband It allows in particular to process the acoustic signals coming from different sources

The principle diagram known in itself of a converter Σ Δ is represented in FIG. 1 An input signal e1 is applied to the input + of a subtractor 101 The output of this subtractor 101 is applied to an integrator 102 whose output is itself applied to a comparator 103 The output of this comparator 103 is looped back to the input - of the subtractor 101 by means of a digital analog converter 105, itself of a very known type simplified. There is thus obtained at the output of the comparator 103 a digital signal which represents the signal e1 on one bit This 1 bit signal is applied to a digital processing device 104 which simultaneously transforms this 1 bit signal into an n bit signal, n = 16 for example , and performs a digital filtering which makes it possible to deliver a digital output signal S, representing on 16 bits and with a sufficiently low signal-to-noise ratio the input signal e1 FIG. 2 represents the frequency / amplitude diagram corresponding to the processing of the signals in the converter of FIG. 1 The input signal e1 is represented by the frequency 201 The 1-bit output signal from the comparator 103 has a strongly noisy spectrum 202 The effect of the filter 104 is represented by the spectral window 203, which eliminates high frequency noise from the spectrum 202 to obtain an output signal comprising the line 201 with superimposed noise of reasonable amplitude

The converter of FIG. 1 is said to be of order 1 because it has only one integration stage 102 It is also known to produce modulators of higher order comprising several integration stages in cascade, but this quickly leads to unstable systems. This drawback is however limited in the case of a converter of order 2, as shown in FIG. 3 in a representation which uses in known manner the system of the transform in Z. The signal e (Z) is applied to the input + of an adder 301 whose output is applied to an integration stage 302 performing the function 1 / (1 - Z ^" 1). The output of this stage is applied to a correction amplifier 306 which makes it possible to adjust the output level at a desirable value to apply it to the input + of a second summation stage 311. The output of this second summation stage is applied to the input of a second integration stage 312 realizing it the Z function " ¹ / (1 -Z"^'1 ). The output of this stage 312 is then applied to a comparator 303 whose output delivers the digital signal 1 bit s (Z). This is looped back to the inputs - summers 301 and 311. The signal s (Z) is then applied to the circuit filter 304 to obtain the output signal S on the desired number of bits.

A known solution to this stability problem consists in producing a high order modulator, by adopting a cascade structure such as that shown in FIG. 4, in which the integration and summation stages have been brought together in modules realizing treatments symbolized by G (Z).

In such a structure, the signal e1 is applied to a first stage comprising a module 400 performing the processing G1 (Z) to deliver an intermediate signal y1 which is applied to a comparator 403 which delivers a 1 bit signal si. This is applied to a specific digital processing circuit 407, which performs processing T1. The signal si is also applied in feedback to a second input of the module 400.

In addition if and y1 are applied to a circuit forming a linear combination of these two signals, to obtain a signal e2 which is applied to the input of the second stage cascaded with the first. This second stage comprises a module 410 carrying out a processing G2 (Z) to obtain a signal y2 applied to a comparator 413 which delivers a signal s2. This signal s2 is applied to a digital processing device 417 which performs T2 digital processing. The signal s2 is also applied in feedback to an input of the module 410.

The signals s2 and y2 are then applied to the third stage of the cascade, and so on to the last stage of the cascade, which receives an input signal from a circuit 486 which performs a linear combination on the signals sn -1 and yn-1 from the previous cascade stage.

This last cascade stage therefore comprises a module 490 performing a processing Gn (Z), a comparator 493 and a digital processing module 497 performing a digital processing Tn. The signals leaving the digital processing circuits 407 to

497 are added together in an adder 408, whose output signal on n bits is applied to a digital low-pass filter 404 which delivers the output signal S of the converter.

This system therefore makes it possible to obtain a stable high-order converter, but it requires having digital processing T1 to Tn specific to each stage. In addition, faults on the components of the analog stages lead to significant deformations of the response curve, which means that precision components which are particularly selected and which are therefore expensive, have to be used. To overcome these drawbacks, the invention provides a device according to claim 1.

Other features and advantages of the invention will appear clearly in the following description given with reference to the appended figures which represent: - Figure 1, a known Σ Δ converter with one stage;

- Figure 2, the response curve of this converter;

- Figure 3, a known Σ Δ converter with two stages in series;

- Figure 4, a known Σ Δ converter with n stages in cascade;

- Figure 5, a Σ Δ converter according to the invention; - Figure 6, the response curve of this converter; and

FIG. 7, an exemplary embodiment of the circuit 522 of FIG. 6.

The diagram of FIG. 5 represents, with the calculation convention according to the transform in Z, a converter Σ Δ according to the invention comprising two stages in cascade; the first floor itself being of the second order. This first stage comprises, as in the converter of FIG. 3, a first summator 501 in series with a first integrator 502, a correction normalizer 506 essentially serving to avoid saturation of the following stages, a second summator 511, a second integrator 512 and a first comparator 503 However, according to the invention, the input signal e1 is applied directly to the input of comparator 503 via a third summator 521 which makes it possible to add it to the output signal of the second integrator 512 II is also applied to the inputs of the summers 501 and 511. This makes it possible to obtain a transmittance of the assembly with respect to the useful signal equal to 1 Therefore it can be considered that the input of the converter is located just before that of the comparator, and therefore the reaction network comprising the integrators only processes the quantization noise Consequently there is no longer any delay between the input e and the output The converter further comprises a second cascade stage formed by a fifth adder 551 in series with a third integrator 522 then a sixth adder 561 and a second comparator 513

The input signal e2 of this second cascade stage is obtained from the summation, in a fourth summator 541, of the input and output signals of the first comparator 503 The input signal thus obtained is applied as for the first floor, simultaneously on the inputs of summers 551 and 561

The first and second integrators 502 and 512 carry out a conventional integration represented by the function Z " ¹ / (1 -Z" ¹ )

Circuit 522 of the second stage performs a resonator function characterized by the formula p Z

(1) 1—. with p = 2 cos (2 π F0 / FE)

\ - pZ + Z 'where F0 is a frequency in the filter band and FE the sampling frequency

We thus obtain on the output of two stages in cascade respectively the 1 bit output signals si and s2

In these conditions, the digital processing which must be applied to the signals si and s2 before summing them is summed up for the first of these to a simple multiplication by 1, that is to say to a direct output without special treatment. For the purposes of the explanation, this direct output has been represented in the figure by a multiplier 507 which performs the operation x 1. The signal s2 on the other hand undergoes digital processing in a circuit 517 which performs the operation represented by the formula : l - 2Z- '+ Z- ^: ¹ î- z- ¹ + cz- ² where C is the multiplying coefficient obtained by circuit 506.

This processing is independent of function 522. It only depends on the first floor.

The signals at the output of these processing circuits 507 and 517 are added in an adder 508, then filtered in the usual way in a low-pass filter 504 which delivers the output signal S.

According to the invention, the circuit 522 instead of being an integrator like the circuits 502 and 512, is a resonator centered on a frequency F0. This resonator performs the function which is represented by formula (1).

The influence of the resonator on the response curve of the converter is shown in the diagram in FIG. 6, which is to be compared to that of FIG. 2. The influence of the first stage with the integrators corresponds to the curve 602 which we see that a part is represented by dotted lines. The influence of the second stage resonator corresponds to the curve 604 centered on the frequency F0. The influence of this resonator then shifts the curve 602 from the frequency F0 by making it undergo a downward movement to obtain the curve 612. The curve 601 represents for example the spectrum of the input signal.

The output filter whose size is represented by 603 makes it possible as previously to eliminate the high frequencies of the noise, but it can be seen that due to this translation of the curve 602 on the curve 612 the residual part of the noise contained in the size of the filter 603 is much lower than what would have remained if we only had curve 602.

The mathematical analysis of this converter shows that compared to conventional structures we obtain the following advantages:

- the transmittance with respect to the useful signal is equal to 1, - the transmittance with respect to noise has a double zero at the frequency zero and two complex zeros conjugate at the frequency F0, which precisely allows the bandwidth to be widened as explained above.

- The digital processing specific to each stage of the converter is less complex, since the output of the first stage is transmitted directly to the adder 508 and that the digital processing is also independent of the position of the zero located at FO.

As a variant, one could use for the integrator 502 an embodiment in which the function 1 / (1-Z " ¹ ) would be carried out as in stage 302 of FIG. 3. At this time, there would have to be use to carry out the specific digital processing of the second stage a circuit 517 which performs the function represented by the formula: l - 2Z- '+ Z- ² 1 + (C - 1) Z-' In this formula C is the multiplier coefficient obtained by circuit 506

This variant makes it possible to slightly simplify the digital processing as well as the overall construction. However, it is observed that in this variant the converter saturates slightly faster than in the first embodiment, which does not present any real practical problems.

The problem which arises, however, lies in the production of the second stage of the converter using new technologies such as, for example, switched capacitors or dynamic current mirrors. Indeed, these technologies make it possible to produce very good integrators, but present difficulties in obtaining non-integer coefficients with good precision. Under these conditions, the invention also proposes to produce this resonator from integrators using a diagram such as that of FIG. 7.

In this diagram, the input signal of the resonator, therefore arriving from the summator 551 of FIG. 5, is applied to a summator 701 whose output is connected to an integrator circuit 702 which performs the function -1 / (1 -Z ^{" 1).} The output of this first integrator is applied to a circuit 703 which performs a multiplication by a coefficient γ p = 1/2.

Since p is equal to 2 cos 2 πFO, we have γ = 2sin ² (π F0 / FE). The output of circuit 703 is applied to a second summer 704 whose output is applied to a second integrator 705 performing the function Z ^{~ 1} / (1 -Z ^"1 ) The second input of summer 704 also receives the applied input signal to the first summator 701 The output of this second integrator is the output of the resonator, which is therefore applied to the input of the summator 561 of FIG. 5

This output is also applied in feedback to the second input of the adder 701 after multiplying by 2 in a circuit 706

The problems which may possibly arise in the production of this converter essentially concern the coefficient C applied in circuit 506 and the coefficient γ applied in circuit 703

The coefficient C, which serves to avoid saturation in the first stage, does not have a critical value II only needs to be carefully paired with the same coefficient C used in the digital processing function performed by the circuit 517 This pairing must be better than 1% if we do not want to increase the signal / noise ratio too much Under these conditions the most practical is to use a value which allows to have only whole coefficients in the second integrator, because the we know how to achieve these whole coefficients better than 1%. Take for example C = 0.5, which results in coefficients in the second integrator equal to 1 or 2

As for the coefficient γ, which determines the central frequency of the resonator, its value is very low, for example of the order of 0.01 We do not know how to achieve such a value with precision, but this is of little importance In fact, this coefficient γ does not appear in digital processing and therefore there is no need for matching In addition, since it only plays on the position of 0 of the noise function in square root, a relative error of for example 10% only leads to an error of 5% on the position of the center frequency. Such an error does not affect the transmittance and therefore the distortion, and has a weak effect on the noise power.

In conclusion, this type of broadband Σ Δ converter makes it possible to gain on the noise factor compared to known converters which makes it possible to obtain a higher resolution in number of bits on the useful signal The theoretical gain is at least 2 significant bits compared to a conventional converter using a quadruple integrator and this at the cost of modifications to wiring diagrams, and therefore of very low production cost. If we place ourselves at the same performance level, we can then gain on the oversampling ratio. In addition, by taking the precautions seen above on the choice of parameters, the converter will be not very sensitive to the tolerances on the components intended to produce the analog stages.

Claims

1 - Converter of the Σ Δ type into baseband, comprising at least a first stage comprising in series at least a first summator (501), a first integrating stage (502), a second summing (511), a second integrating stage ( 512) and a comparator (503), the output of which is connected to an input of the first summator, characterized in that it further comprises a third summator (521) located in series between the second integrating stage (512) and the stage comparator (503), and that the converter input signal is applied in parallel to the inputs of the three summers (501, 506, 521).

2 - Converter according to claim 1, which comprises at least a second stage in cascade with the first; this second stage comprising in series at least a fourth summator (551), a signal processing stage (522) and a second comparator (513), characterized in that the processing stage is a resonator.

3 - Converter according to claim 2, characterized in that it further comprises a fifth summator (561) in series between the processing stage (522) and the second comparator (513) and that the input signal of the second Cascade stage is applied in parallel to the inputs of the fourth and fifth summers (551, 561).

4 - Converter according to any one of claims 2 and 3, characterized in that the resonator comprises a first adder (701) to receive the input signal from the resonator, a first integrator (702) to receive the output signal from the first summator, a multiplier (703) to multiply the output signal of the third integrator by a determined coefficient γ, a second summator (704) to receive the output signal of the multiplier by γ and the input signal of the resonator, a fourth integrator (707) for receiving the output signal from the second adder and outputting the output signal from the resonator; this output signal being looped back to the input of the first adder via a multiplier (706) multiplying this signal by a coefficient 2.