WO1994015336A1 - Systeme de commande de modification de la vitesse de defilement d'une bande comprenant la generation d'une reference servo et d'une horloge audio - Google Patents

Systeme de commande de modification de la vitesse de defilement d'une bande comprenant la generation d'une reference servo et d'une horloge audio Download PDF

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Publication number
WO1994015336A1
WO1994015336A1 PCT/US1993/008415 US9308415W WO9415336A1 WO 1994015336 A1 WO1994015336 A1 WO 1994015336A1 US 9308415 W US9308415 W US 9308415W WO 9415336 A1 WO9415336 A1 WO 9415336A1
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WO
WIPO (PCT)
Prior art keywords
signal
die
frame
pulse
phase
Prior art date
Application number
PCT/US1993/008415
Other languages
English (en)
Inventor
Martin A. Lilley
Original Assignee
Ampex Systems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Ampex Systems Corporation filed Critical Ampex Systems Corporation
Publication of WO1994015336A1 publication Critical patent/WO1994015336A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof
    • H04N5/932—Regeneration of analogue synchronisation signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
    • G11B15/18—Driving; Starting; Stopping; Arrangements for control or regulation thereof
    • G11B15/1808—Driving of both record carrier and head
    • G11B15/1875—Driving of both record carrier and head adaptations for special effects or editing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
    • G11B15/18—Driving; Starting; Stopping; Arrangements for control or regulation thereof
    • G11B15/46—Controlling, regulating, or indicating speed
    • G11B15/467—Controlling, regulating, or indicating speed in arrangements for recording or reproducing wherein both record carriers and heads are driven
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/005—Reproducing at a different information rate from the information rate of recording
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/78—Television signal recording using magnetic recording
    • H04N5/782—Television signal recording using magnetic recording on tape
    • H04N5/783—Adaptations for reproducing at a rate different from the recording rate

Definitions

  • TSO TAPE SPEED OVERRIDE
  • the present invention relates generally to transport control systems for tape recorders and tape playback devices and, more particularly, to tape transport control systems which can accurately re-phase the tape transport when reverting between tape speed override (TSO) and normal tape speed.
  • TSO tape speed override
  • Images may be stored and retrieved such as in the television industry, where it is common for a television broadcast station to have occasions when it is highly desirable to playback a recorded message for broadcast (for example, a commercial advertisement) in slighdy less time, or in slighdy more time, than the normal play time of the recording.
  • a recorded message for broadcast for example, a commercial advertisement
  • TSO tape speed override
  • Video tape recorder/playback devices such as video tape recorder/playback devices (VTRs) have been developed which employ a helical record format.
  • VTRs video tape recorder/playback devices
  • helical recorded audio and video signals are recovered via associated helical signal channels using helical scanning audio/video heads.
  • Precise recovery of the audio presents significant problems when dealing with a helical audio/video format.
  • helical scanning heads can be used to skip or repeat video tracks, to easily perform video special effects such as stop, slow motion, fast motion and so forth.
  • an audio signal must be continuously recovered since any interruption of the digital audio data will result in objectionable noise and what are sometimes referred to in the art as "pops" during reproduction of the recorded signal.
  • the heads which are tracking the helical audio signal cannot skip or repeat with the video head else there would be interruptions in the digital audio data. This condition complicates the process of time compression or expansion when reading out a helical recorded audio signal during a TSO mode of operation.
  • the processing system includes both a video time base corrector (TBC) and an audio TBC which can be clocked at a non-normal rate of the off-speed reference clock.
  • TBC video time base corrector
  • the transport is run from a variable reference clock while the video signal processing circuits run at a constant standard synchronous reference, such that the video TBC and the controllable scan tracking heads operate in conventional fashion as when performing a normal PLAY mode.
  • the audio signal processing circuits can be run faster or slower as required, while keeping the audio circuits on a reference clock which is running at the desired TSO rate. In this way, the audio can be loaded at a faster or slower rate, and read out at an equally faster or slower rate, to provide TSO without causing problems in the video signal processing.
  • a range of TSO operation on the order of plus or minus 15 percent (which is also written as ⁇ 15%) can be provided.
  • a constant standard reference clock is used to run the transport and video signal processing systems, while the audio scanner speed and the tape speed are increased or decreased to provide the desired TSO rate.
  • the audio scanner speed and tape speed are increased or decreased proportionately, thus keeping the audio scanner phase locked with the tape and preventing head jumping of audio tracks.
  • the audio scanner speed When the audio scanner speed is increased, more audio data is recovered from the tape in a given time such that there is a risk of overflowing the audio TBC, thereby "spilling" bits of audio data and causing an objectionable break in the audio signal.
  • the rate of the audio clock is therefore increased to increase the read-out of data from the audio TBC.
  • the tape speed is increased proportionately by means of a control track servo loop and a capstan servo-loop.
  • the system stays in lock in the TSO mode without head jump or loss of audio data.
  • the video signal processing is performed in conventional fashion with suitable skipping of pertinent fields or frames via a frame store to provide the video data compression required to match the audio data compression.
  • a standard synchronous reference signal of constant frequency is applied via a synchronous generator of a VTR system, including a tape transport, control circuits, a video signal processor circuit and an audio signal processor circuit.
  • Audio data compression or expansion is provided by modifying an additional internal audio signal processing clock represented as a voltage controlled oscillator to alter the normally coordinated functions of the audio TBC, the audio scanner, and the control track and capstan servos, thus providing cooperative functions there between when in the TSO mode.
  • known systems are susceptible to inaccuracies. For example, re-entry to a normal playback mode following a TSO mode can result in undesirable audio effects (for example, noise).
  • audio clocks are varied rather coarsely in known TSO modes by, for example, adjusting the divisor of an 18 megahertz (MHz) clock from 375 (for example, the minimum adjustment is 1 375).
  • the servo reference signal used for tape speed control is not derived from the same generator as the audio clock.
  • the audio printed wiring assembly measures the relative timing of a transport drum tachometer and the audio clock frequency by observing the audio buffer centering, and then adjusts the servo reference signal to reduce the error to center the audio buffer.
  • PWA printed wiring assembly
  • the present invention is directed to providing a more precise method and structure for a TSO speed control by using a variable frequency system clock to proportionately vary both the audio clock signals and the servo control signals.
  • teachings of the present invention provide an ability to measure phase differences of the audio clock or servo control signals generated in a TSO mode of operation (when the speed is nominally correct) relative to reference image control signals, here illustratively and not by way of limitation, video control signals to which the audio clock and servo control signals would be locked in a normal PLAY mode.
  • phase measurements of the present invention can be performed at any speed provided some correction is made to compensate for the speed offset and the time of measurement. This permits a system processor to reduce phase errors measured with respect to the reference video control signals to zero, thus allowing a normal PLAY lock mode to be accurately and completely re-established.
  • Embodiments of the present invention relate to structures and methods for controlling a tape transport having a PLAY mode and a variable TSO mode.
  • one exemplary embodiment generates a system clock signal which is fixed during the PLAY mode, but which can be varied during the TSO mode, generates servo control signals for the tape transport in response to the system clock signal, controls a re-phasing of the tape transport following a transition between a TSO mode and a PLAY mode, and generates an audio control signal in response to the system clock.
  • a specially encoded component synchronization (SYNC) signal can be used which is easily generated and decoded.
  • the CNENT SYNC signal is decoded to provide reference video control signals, such as a horizontal reference signal, a frame reference signal and a field reference signal.
  • Exemplary signal processing circuits such as a decoding circuit for the CNENT SYNC signal, include specially designed one-shot circuits which trigger on both positive (for example, rising) edges of an input waveform and on negative (for example, falling) edges of the input waveform.
  • the CNENT SYNC signal is also used to synchronize servo control signals which include a servo reference signal, a frame reset signal and a field reset signal.
  • the servo control signals are specially encoded into a composite signal for transmission over a single data line.
  • alternative exemplary embodiments of the present invention include noise immunity circuits for rendering the system substantially immune to noise during phase locked modes (for example, modes entered after phase lock has been established).
  • FIG. 1 is a block diagram depicting an exemplary embodiment of a TSO reference generator in accordance with the present invention
  • FIG. IA illustrates the relationship among FIGs. IB, 1C, ID and IE, which combine to illustrate more details of the FIG. 1 block diagram depicting an exemplary embodiment of a TSO reference generator in accordance with the present invention
  • FIGs. 2 and 3 show an encoded CNENT SYNC signal and its phasing relative to normal COMPOSITE SYNC signals for use with an NTSC 525-line standard in the TSO reference generator shown in FIGs. 1, IA, IB, 1C, ID and IE;
  • FIGs. 4 and 5 show the encoded CNENT SYNC signal and its phasing relative to normal COMPOSITE SYNC signals for use with a PAL 625-line standard in the TSO reference generator shown in FIGs. 1, IA, IB, 1C, ID and IE;
  • FIG. 6 shows exemplary details of illustrative field 1 IDENT and field 2 IDENT pulses usable in connection with the TSO reference generator shown in FIGs. 1, IA, IB, 1C, ID and IE;
  • FIG. 7 shows an exemplary CNENT SYNC signal encoder generator for use with the TSO reference generator shown in FIGs. 1, 1 A, IB, 1C, ID and IE;
  • FIG. 8 illustrates the relationship among FIGs. 8A, 8B, 8C and 8D, which combine to show an exemplary CNENT SYNC signal decoder for use with the TSO reference generator shown in FIGs. 1, IA, IB, 1C, ID and IE;
  • FIG. 9 illustrates the relationship among FIGs. 9A and 9B, which combine to show an exemplary application specific integrated circuit (ASIC) embodiment of a digital one-shot circuit, which can be used with the CNENT SYNC decoder shown in FIGs. 8, 8A, 8B, 8C and 8D;
  • ASIC application specific integrated circuit
  • FIG. 10 shows an exemplary non-ASIC embodiment of a digital one-shot circuit, which is an alternative to the digital one-shot circuit shown in FIGs. 9, 9A and 9B;
  • FIG. 11 illustrates the relationship among FIGs. 11 A and 1 IB, which combine to show an exemplary line counter with noise immunity circuit for use as a frame lock detector in the TSO reference generator shown in FIGs. 1, IA, IB, IC, ID and IE;
  • FIG. 12 illustrates the relationship among FIGs. 12A, 12B, 12C, 12D, 12E and 12F, which combine to show a more specific embodiment of the exemplary line counter with noise immunity circuit shown in FIGs. 11, 1 IA and 1 IB;
  • FIG. 13 shows an attendant timing diagram of signals labeled as A, B, C, D, E, F, G, H, I, J, K, L, M, N, and P, which are useful in describing the exemplary line counters with noise immunity circuits shown in FIGs. 11, 1 IA and 1 IB as well as FIGs. 12, 12A, 12B, 12C, 12D, 12E and 12F;
  • FIGs. 14 and 15 show attendant timing diagrams, which are useful in describing exemplary encoded servo reference signals that can be generated by the exemplary servo clock signal and servo control signal generators shown in FIG. 16;
  • FIG. 16 shows exemplary servo clock signal and servo control signal generators for use with the TSO reference generator shown in FIGs. 1, IA, IB, IC, ID and IE;
  • FIG. 17 illustrates the relationship among FIGs. 17A, 17B and 17C, which combine to show an exemplary encoded servo reference signal decoder for decoding the signals generated by the structure shown in FIG. 16;
  • FIG. 18 illustrates the relationship among FIGs. 18A, 18B, 18C, 18D, 18E, 18F, 18G and 18H, which combine to show a more specific embodiment of the exemplary encoded servo reference signal decoder shown in FIGs. 17, 17A, 17B and 17C, all in accordance with the principles of the present invention.
  • FIG. 1 a block diagram of a TSO reference generator for controlling a tape transport having a PLAY mode and a variable TSO mode is illustrated.
  • FIG. IA illustrates the relationship among FIGs. IB, IC, ID and IE, which combine to illustrate more details of the FIG. 1 block diagram of an exemplary embodiment of a TSO reference generator.
  • reference to FIG. 1 is meant to also include reference to FIGs. IA, IB, IC, ID and IE.
  • the description of the exemplary tape transport is in terms of a digital video tape recorder/playback transport - it being understood that other tape transports, for example, those transports used for storing and/or retrieving analog, audio, and still other kinds of information, may equally use the principles of the instant invention.
  • the TSO reference generator 100 of FIG. 1 is illustrated as being formed primarily on a single application specific integrated circuit (ASIC) corresponding to the reference numeral 100. Although not all components of the FIG. 1 embodiment are illustrated as being formed on the ASIC, it will be apparent to those skilled in the art that an ASIC with all components being formed thereon could be designed. Notwithstanding, for purposes of illustration and the discussion herein, and not by way of limitation, the following components are all illustrated as being located separately from the ASIC:
  • VCO voltage controlled oscillator
  • a means such as a video control signal generator 190 generates video control signals 171.
  • the video control signals 171 are reference signals which include a horizontal reference (HORIZ REF) signal, a frame reference (FRAME REF) signal and a field reference (FIELD REF) signal, all of which are established in response to an input 191.
  • HORIZ REF horizontal reference
  • FRAME REF frame reference
  • FELD REF field reference
  • each video frame is formed by a combination of two fields and includes a set number of horizontal lines (for example, 525 lines per frame for what is known in the art as an NTSC standard or 625 lines per frame for what is known in the art as a PAL standard).
  • the 525 lines per frame standard will generally be referenced as "(525)” while the 625 lines per frame standard will generally be referenced as "(625)”.
  • the input 191 to a CNENT SYNC decoder embodiment could be the reference signal.
  • a COMPOSITE SYNC signal which is widely used with available television equipment, could be the reference signal.
  • Such signals are well known in the art, in both analog and digital technologies, for transmitting horizontal, vertical and frame synchronizing reference signals.
  • a specially encoded CNENT SYNC signal input can be generated at input 191 using a CNENT SYNC generator 700.
  • the CNENT SYNC signal from CNENT SYNC generator 700 is applied via input 191 to a CNENT SYNC decoder 800 of the video control signal generator 190.
  • the decoder 800 extracts the video control signals 171.
  • the CNENT SYNC decoder 800 also extracts control pulses for input to a frame multiplier reference generator 172.
  • a CNENT SYNC signal which provides the video control signals in accordance with the present invention is usually easier to generate and decode than a conventional COMPOSITE SYNC.
  • HGs. 2 and 3 show an illustratively encoded CNENT SYNC signal and its phasing relative to the normal COMPOSITE SYNC signal for the 525 standard while
  • FIGs. 4 and 5 show an illustratively encoded CNENT SYNC signal and its phasing relative to the normal COMPOSITE SYNC signal for the 625 standard. As illustrated in FIGs. 2, 3,
  • the CNENT SYNC signal comprises an exactiy unity mark/space ratio and is encoded once per field with a field identification pulse.
  • the field identification pulse can be used to provide the field reference (FIELD REF) signal and die frame reference (FRAME REF) signal.
  • the term "unity mark/space ratio”, as referenced herein, means a pulse wave (for example, square wave) having a substantially fifty per-cent (50%) duty cycle (that is, 50% of the wave is mark and 50% of the wave is space).
  • Each pulse of the unity mark/space ratio waveform includes a falling edge aligned with a horizontal line boundary. For example, the falling edge labeled 320 in FIG. 3 coincides with die boundary between horizontal line numbers 262 and 263 of field two of a frame in the 525 standard.
  • Field identification pulses are abbreviated herein as "field IDENTs," and are labeled 210, 310, 410, and 510 in FIGs. 2, 3, 4, and 5, respectively, and are encoded onto the
  • FIGs. 2 and 3 respectively, for the 525 standard which correspond to the horizontal line numbers preceding normal field transitions.
  • field reset pulses can be obtained at exacdy die normal field transition point (for example, at zero reference point "O v ”) or one-half horizontal line early (for example, halfway through horizontal line number
  • the field IDENT pulse 210, 410 is a positive going pulse which identifies die rising edge 220, 420 of the CNENT SYNC signal so it can be used to initiate a frame reset (FRAME RESET) signal.
  • the frame reset (FRAME RESET) signal has a width equal to one horizontal line and straddles the frame boundary located at die zero reference point O v .
  • the pulse 310, 510 is encoded on the CNENT SYNC signal at a location which is one-half horizontal line width prior to the start of horizontal line number
  • the pulse 310 or 510 identifies the falling edge labeled 320 or 520 of the FIG. 3 or 5, respectively, CNENT SYNC signal so it can be used to initiate a field 2 reset signal.
  • the field 2 reset signal has a width equal to one horizontal line width which straddles die mid-point of the video frame (for example, a position halfway through horizontal line number 263 (525) or 313 (625).
  • die field 1 IDENT pulse 210, 410 is a positive pulse of one microsecond.
  • the field 1 IDENT pulse 210, 410 is initiated one microsecond after the negative transition which represents the start of line number 525 (525) or line number 625 (625).
  • the field 2 IDENT pulse 310, 510 is a negative pulse of one microsecond.
  • the field 2 IDENT pulse is initiated one microsecond after the positive transition of the CNENT SYNC signal which represents the mid-point of line number 262 (525) or line number 312 (625).
  • field IDENT pulses While two field IDENT pulses are illustrated for a given frame, it will be appreciated that the field 1 IDENT pulse alone can be used as a frame reference (FRAME REF) signal.
  • FRAME REF frame reference
  • FELD REF field reference
  • FIG. 7 is a block diagram showing details of an exemplary CNENT SYNC signal generator 700 for producing the encoded CNENT SYNC signal of FIGs. 2, 3, 4, 5 and 6. This diagram does not show how signal generator 700 would be locked to a normal television COMPOSITE SYNC signal but the techniques for doing this are well known to those skilled in die art.
  • the signal generator shown is free-running, with an output frequency stability being dependent upon the stability of a fixed 27 megahertz (MHz) reference clock frequency.
  • the CNENT SYNC signal generator 700 includes a dividing means represented as counter 710 for dividing the 27 MHz reference clock by 1716 (525) or 1728 (625) depending upon the desired television standard.
  • the counter 710 produces a pulsed waveform having a frequency F n which is provided as an input to a line counter 720.
  • the counter 710 produces a binary output (shown in FIG. 7 as an 11-bit digital value) which is decoded by a line segment decoder 730.
  • the line segment decoder 730 produces three signals collectively represented as 740:
  • Each of the IDENT pulses in the field IDENT signals is generated by the line segment decoder 730 at the frequency F n .
  • the line counter 720 divides die H-rate pulse from counter 710 by 525 (525) or 625
  • the line decoder 750 decodes the count of counter 720 to provide gating pulses.
  • the gate pulses output from the line decoder 750 are used to produce d e field 1 IDENT on line number 525 (525) or line number 625 (625) and the field 2 IDENT on line number 262 (525) or line number 312 (625).
  • the gating pulses from the line decoder 750 are fed to output gating logic 760 which selectively gates the appropriate field 1 and field 2 pulses from line segment decoder 730 for a given frame.
  • the gated field 1 IDENT and field 2 IDENT pulses are combined and fed into one input of an exclusive-OR gate of the output gating logic 760.
  • the H-rate square wave is fed to a second input of the exclusive-OR gate.
  • the H-rate square wave does a polarity reversal for the duration of die gated IDENT pulse, resulting in the generation of die encoded CNENT SYNC signal shown in HGs. 2-6.
  • the receiver decoder and generator are normally frame locked such tiiat only the field 1 pulse is decoded to produce the frame reset (FRAME RESET) signal for the FIG. 1 generator.
  • FRAME RESET frame reset
  • provision of field 2 encoding permits the decoder to operate if the CNENT SYNC signal is inadvertendy inverted somewhere in the transmission path (for example, with a one field advance or delay in synchronization). In certain circumstances, such a field advance or delay might be desired or at least acceptable.
  • FIG. 8 An exemplary embodiment of the FIG. 1 CNENT SYNC decoder 800 will now be described by reference to FIG. 8.
  • reference to FIG. 8 is meant to also include reference to FIGs. 8 A, 8B, 8C and 8D.
  • die decoder 800 is entirely digital and die decoder's clock 805 is considered asynchronous with the CNENT SYNC signal to be decoded.
  • the decoding of the CNENT SYNC signal is performed by detecting die presence of the field 1 IDENT and field 2 IDENT pulses and by removing them, if present, to allow the uncoded input square wave to be reconstituted.
  • This decoding is performed by generating a waveform at a frequency of 2F n (for example, at twice the frequency of the CNENT SYNC waveform shown in HGs. 2-6).
  • a one-shot circuit 900 which is generally shown in FIG. 8 and which is specifically shown in FIG. 9, it being also understood that reference to FIG. 9 includes reference to FIGs. 9A and 9B, is specially designed to trigger on both positive and negative edges of an input waveform (for example, the CNENT SYNC signal) to output a 2F jj pulse waveform. Further, the specially designed one-shot circuit can distinguish and indicate whedier each pulse of the output waveform was produced in response to a positive (rising) or a negative (falling) edge.
  • an input waveform for example, the CNENT SYNC signal
  • the specially designed one-shot circuit can distinguish and indicate whedier each pulse of the output waveform was produced in response to a positive (rising) or a negative (falling) edge.
  • One-shot circuits used to detect both edges of a pulsed signal are unable to distinguish which pulse edge triggered die one-shot.
  • One approach which can be used to identify a triggering edge is to include two separate one-shots: a first one-shot to detect the rising edges of an input signal and a second one-shot to detect d e falling edges of die input signal.
  • the two one-shots are of the discrete integrated circuit (IC) type, component tolerances make it difficult to match the pulse widtiis generated in response to positive triggering versus the pulse widtiis generated in response to negative triggering.
  • digital one-shots improve the ability to match pulse widths, circuit complexity is dramatically increased.
  • FIG. 9 illustrates an ASIC embodiment of a digital one-shot that eliminates any requirement for two separate digital one-shots while minimizing circuit complexity.
  • an exemplary ASIC embodiment of a non-retriggerable one-shot which can be used as die one-shot circuit 900 is illustrated.
  • the FIG. 9 one-shot circuit can respond to both positive and negative trigger edges of an input signal and can provide separate output pulses for each trigger edge.
  • the FIG. 9 one-shot circuit provides separate outputs 950 and 952 to indicate whether the one-shot circuit responded to a positive or negative trigger.
  • the FIG. 9 one-shot Once the FIG. 9 one-shot is triggered, it can be rendered immune to further triggering until it has timed out, an important feature for detecting the field IDENT pulses encoded on the CNENT SYNC signal of FIGs. 2 and 3.
  • an exemplary one-shot circuit 900 includes an input means
  • the one- shot further includes a means for establishing a delay, represented as a pulse delay means 908 comprising first and second counters 910 and 912, which function as a two-stage counter.
  • the delay is used to produce a pulse from the one-shot circuit 900 of, for example, four microsecond pulse duration. While the exemplary FIG. 9 embodiment illustrates an eight-bit counter for establishing a delay period, tiiose skilled in the art will recognize that any number of bits (for example, n bits with an n-bit counter) can be used.
  • An output means 914 of the one-shot circuit 900 includes first and second D flip-flops 916 and 918.
  • Various logic circuitry is also included in die FIG. 9 one-shot and will be further described witii respect to operation of the FIG. 9 circuit.
  • test inputs in the FIG. 9 circuit are unnecessary to understanding the present invention.
  • the test inputs, and circuitry associated with the test inputs are merely illustrated to reflect an ability to provide testing of the exemplary embodiments described herein.
  • die test inputs can, for example, be maintained at an inactive logic level to permit a non-test mode of operation in accordance with the present invention.
  • the test inputs can be excluded from the circuitry illustrated in the drawings.
  • the pulse delay means 908 generates a ripple carry-out (RCO) pulse from the second counter 912 when a maximum count of the two-stage counter 910, 912 has been reached.
  • This ripple carry-out pulse is
  • the re-clocked ripple carry-out pulse is used to clear the Q outputs of the D flip-flops 904 and 906 and thus drive their QZ outputs high (where "QZ" represents an inverted Q output).
  • a QZ output of the second D flip-flop 918 in output means 914 is a negative-going pulse that is connected to a first input of an AND gate 920 in the input means 902. Due to an inverter 922, the second input to the AND gate 920 is a normally high clear signal (for example, CLRZ).
  • the negative-going pulse output from the second D flip- flop 918 drives the output of AND gate 920 low and tiius clears the active low clear inputs of the D flip-flops 904 and 906.
  • the D inputs of the D flip-flops 904 and 906 are driven high due to the cross-coupling of their QZ outputs. Further, because a test input 924 is inactive low, and the Q outputs of the D flip-flops 904 and 906 are low, an output of a first NOR gate 926 is driven high. The output of the first NOR gate 926, via a second NOR gate 928, drives load inputs for the counters 910 and 912 low to inhibit counting by the pulse delay means 908.
  • Detection of a positive or negative transition at the input means 902 enables the pulse delay means 908.
  • the first D flip-flop 904 is clocked to transfer the logic high D input of this flip-flop to its Q output.
  • the Q output of flip-flop 904 drives the output of NOR gate 926 low, thus driving die load inputs of the two-stage counter high.
  • the two-stage counter 910, 912 counts up through the terminal count and again generates the ripple carry-out pulse.
  • the ripple carry-out pulse clears the D flip-flop 904 and again sets the count _oad inputs of die two-stage counter low to inhibit further counting.
  • the second D flip-flop 906 of the input means is clocked, and used to control the pulse delay means 908 in a manner similar to that described with respect to a positive transition at the trigger input 930.
  • the cross-coupling of the first and second D flip-flops in the input means causes the flip-flop which is not clocked to be inhibited by the flip-flop which is clocked.
  • outputs of the first and second D flip-flops 904, 906 represent pulses generated in response to positive and negative trigger transitions, respectively. Transitions which occur during the time-out period are ignored. This tim&-out period prevents the one-shot circuit 900 from triggering on both edges of a field IDENT pulse so that d e field IDENT pulses can be accurately detected by remaining portions of the FIG. 8 CNENT SYNC decoder circuit 800.
  • the time-out period of the FIG. 9 one-shot circuit 900 is determined by die clock frequency and die counter load number which is input via a counter load input 931 and an eight-bit input 934 of the input means.
  • the eight-bit input 934 can be a software programmable input that is easily adjusted by die user.
  • An octal D flip-flop 936 of the input means 902 is a register that is loaded by die system processor 120 with die counter load number such that a range of one-shot periods can be programmed by software.
  • An output means 914 of the FIG. 9 one-shot includes die flip-flop 916 for re- clocking the positive and negative triggered one-shot pulses which are combined by the NOR gates 926 and 928 (for example, the counter load signal for the two-stage pulse delay means 908).
  • the additional delay of die flip-flop 916 can be included in die timing calculation.
  • die signal received at d e trigger input 930 is assumed to be synchronous with, and of known relative phase with, die clock frequency such that die set-up time for the counter load signal is correct.
  • the trigger input signal is asynchronous with die clock, those skilled in the art will recognize that a provision must be made to re-clock the trigger to prevent a possibility of set-up violations in the counter load signal.
  • FIG. 10 shows a non-ASIC embodiment of the FIG. 9 circuit.
  • discrete integrated circuits are used to form an input means 1002 (which is comparable to input means 902 of FIG. 9) and an analog delay means 1008 (which is comparable to delay means 908 of FIG. 9) as a one-shot pulse generator.
  • D flip-flops 1040 and 1042 of an input means 1002 can be 74F74 integrated circuits available from Texas Instraments, Inc.
  • Monostable multivibrators 1044 and 1046, which use resistor-capacitor (RC) timing components to form an analog delay means 1008, can be 74LS221 integrated circuits available from Texas Instruments, Inc.
  • An output means 1014 (which is comparable to output means 914 of FIG. 9) includes output lines 1048 to provide outputs similar to those of outputs 950, 952 in FIG. 9.
  • the FIG. 10 circuit operates in a manner similar to the digital circuit of FIG. 9.
  • the Q outputs from the D flip-flops 1040 and 1042 generate enable signals in response to positive or negative transitions.
  • the enable signals via an OR gate 1043, start a ramp integration within the delay means 1008 until a tiireshold is reached.
  • the period of delay means 1008 can be user controlled by varying the time constants RiCi and R2C2 of multivibrators 1044 and 1046 respectively. 3.
  • the CNENT SYNC input signal received on line number 191 in FIG. 8 is initially re-clocked in a D flip-flop 810, labeled DDFF1.
  • DDFF1 D flip-flop 810
  • This is a double D flip-flop designed to avoid violation warnings during ASIC simulation when conditions of metastability might occur.
  • a single D flip-flop can be used to re-clock the input signal when metastability concerns are less likely to occur.
  • Re-clocking is used at tiiis point to establish accurate signal timing for the one-shot 900, 1000 which follows.
  • the one-shot 900, 1000 is triggered by the inverted output (labeled QZ) of the D flip-flop 810. Therefore, the negative edge of the CNENT SYNC signal is reclocked to become the positive trigger for the one- shot 900, 1000.
  • FIG. 8 decoder circuit 800 uses the output from the one-shot circuit 900, 1000 to:
  • the pulse delay period of d e one-shot 900 must be sufficiendy long to actually prevent the one-shot from retriggering in response to the field
  • IDENT pulses By responding to both positive and negative edges of the CNENT SYNC signal, and by preventing triggering in response to the field IDENT pulses, a waveform of frequency 2F n can be produced for use witii detecting field IDENT pulses as follows.
  • FIG. 8 non-retriggerable one-shot circuit 900 is prevented during the exemplary four microsecond time-out period of the pulse delay means by the one-shot circuit 900 (FIG. 9). Because the field 1 IDENT pulse 210, 410 of FIG. 6 and field 2 IDENT pulse 310, 510 occur within four microseconds after a negative transition or after a positive transition, respectively, of the CNENT SYNC signal, these IDENTs are ignored by the one-shot circuit 900.
  • the main output Q of the one-shot 900 is therefore a positive pulse of four microseconds duration occurring at twice the horizontal line rate, or 2F jr
  • This Q output from the one-shot 900 triggers a second one-shot 815, which triggers only on a positive going edge to generate pulses of 1.5 microseconds duration at a rate of 2F n .
  • the duration of the pulse produced by one-shot 815 is selected such tiiat its trailing edge occurs at a point midway tiirough the expected IDENT pulse position.
  • the presence of the field 1 IDENT or field 2 IDENT can be detected by monitoring the logic state of the encoded CNENT SYNC signal 1.5 microseconds after each positive or negative transition. For example, referring to FIG.
  • the field 1 IDENT pulses are detected as follows.
  • the HORIZ REFZ square wave signal (here shown as the inverted horizontal reference (HORIZ REF) signal at frequency F n ) from NAND gate 850 is inverted in an inverter 855 labeled
  • a pulse generator responds to the detected field 1 IDENT pulse to produce an advance field 1 reset (abbreviated ADV FLD1 RST) and is used as the frame pulse in other circuits. More particularly, when the Q output of the flip-flop 870 goes high, it triggers a pulse generator comprising flip-flops 872, 880 (labeled DFF5, DFF6), and an AND gate 874 (labeled AN5). Because die flip-flop 880 is triggered by HORIZ REFZ from NAND gate 850, an advance field 1 reset pulse is generated which starts approximately one-half line after the field 1 IDENT is detected and which occurs at a point in time exacdy one-half horizontal line before the field 2 to field 1 transition.
  • ADV FLD1 RST advance field 1 reset
  • the period which corresponds to a horizontal line widtii corresponds to 1 F jj .
  • the resulting advanced field 1 reset pulse which is produced can also be re-clocked by the HORIZ REF signal from inverter 855 in a D flip-flop 884, (labeled DFF7) to occur on horizontal line number 1 (for both 525 and 625 standards).
  • the operation of the field 2 IDENT pulse detector is similar to that for field 1 (for example, including D flip-flops 876, 882 and 890 labeled DFF8, DFF9 and DFF4, respectively) and will not be separately described.
  • the output pulse from a D flip-flop 886 (labeled DFF10) is on line number 263 (525) or line number 313 (625).
  • a latch 894 (labeled LAI) is set by the field 1 pulse from D flip-flop 884 and reset by the field 2 pulse from D flip-flop 886 through AND gate 888 to produce a frame-rate square wave.
  • Advanced field reset pulses and field reset pulses (abbreviated FLD RST) are obtained by logically OR-ing field 1 and field 2 pulses together in NAND gates-896 and 892 (labeled NA6 and NA5 respectively).
  • AND gates 888 (labeled AN6) and 878 (labeled AN7) are only needed for the ASIC application where an inverted clear signal (abbreviated CLRZ) is used to establish initial output levels. Delays labeled DL1, DL2, DLD1, DL3, DL4, and DLD2 prevent timing violations during die ASIC testing but are not required for the functionality of the circuit.
  • CLRZ inverted clear signal
  • the separate outputs for positive and negative triggers of the one-shot 900,1000 are used with inverters 835 (INV1) an 845 (INV2), and
  • the output from gate 850 is a square wave at a frequency F h , representing the inverted horizontal reference (HORIZ REF) signal. This signal is deliberately not reclocked so that die timing edges are preserved for use with a phase-locked loop and only suffer a small propagation delay.
  • the QZ output of the one-shot 900, 1000 is re-clocked by a flip-flop 825 labeled DFF11 and then gated with itself in a NOR gate 830 labeled NO1 to produce a pulse of one clock cycle duration at a frequency of 2F n .
  • the frame multiplier reference generator 172 produces a multiplied frame reference signal 178 at ten times the frequency of die frame reference (FRAME REF) signal produced by the CNENT SYNC decoder 800.
  • Outputs from the CNENT SYNC decoder 800 and die frame multiplier reference generator 172 are produced at output pins 171, 178 of the HG. l ASIC.
  • the FIG. 1 embodiment further includes a horizontal reference presence detector 173 and a frame reference presence detector 174 for indicating the presence of these signals.
  • the indications provided by tiiese signals confirm that die CNENT SYNC reference is present at the TSO reference generator and c ⁇ rrecdy decoded.
  • the FIG. 1 apparatus further includes a means, such as system clock signal generator 110, for generating a system clock signal which is fixed during the PLAY mode, but which can be varied to implement a TSO mode.
  • die system clock signal generator 110 includes a 27 MHz inductor/capacitor (L/C) voltage controlled oscillator (VCO) 111 for generating a clock signal.
  • the clock signal produced by die VCO 111 is input to a dividing means represented as a counter 112 for producing a variable horizontal control signal (VAR H).
  • the counter 112 divides the clock signal from VCO 111 by 1716 (525) during a normal PLAY mode. For the 625 standard, the divisor would be 1728. These division ratios are derived from the 27 MHz clock rate divided by F ⁇ .
  • the divisor of the counter 112 can be selectively varied to implement a TSO mode. To vary the divisor of the counter 112 (for example, by plus-or-minus ten per-cent, which is written as ⁇ 10%), a VTR central processing unit (CPU), represented as a system processor 120, produces an output on an eight-bit data bus 121.
  • CPU central processing unit
  • a wider range of adjustment can be used, for example, such as ⁇ 20% or yet other ranges of adjustment.
  • variable horizontal control signal output by the counter 112 should be of equal frequency to, and in phase with, the horizontal reference (HORIZ REF) signal output from the CNENT SYNC decoder 800.
  • HORIZ REF horizontal reference
  • These signals are input to a phase detector 114 which produces phase detected signals to correct the frequency and phase output of the VCO 111 via a phase error amplifier 113 to maintain the above- mentioned phase relationship.
  • the system processor 120 can instruct the counter 112 to alter the divisor via the data bus 121 such tiiat the variable horizontal control signal will digress momentarily from the horizontal reference (HORIZ REF) signal output of CNENT SYNC decoder 800.
  • the phase detector 114 and amplifier 113 will produce an error signal representing the difference between the variable horizontal control signal output from counter 112 and die horizontal reference (HORIZ REF) signal output from the CNENT SYNC decoder 800 for driving the VCO 111.
  • the variation in the output frequency of the VCO 111 is used to time compress or to time expand die playback of recorded data by speeding up or slowing down the servo control signals and die audio control signals. Once the VCO 111 has re-locked to its new frequency, the variable horizontal control signal will once again be in frequency and phase lock with d e horizontal reference (HORIZ REF) signal.
  • a return transition from a TSO mode to a normal PLAY mode is controlled by a phase measuring means, here rephase controller 180.
  • the phase measuring means provides framing phase error information to system processor 120 for controlling the counter 112 of die clock signal generator 110.
  • the clock signal generating means 110 further receives a control input from an incremental timing adjustment circuit 140 for more precisely re- framing of the TSO generator's FRAME RESET signal and the frame reference (FRAME REF) signal in response to an output from the phase measuring means 180.
  • die FIG. 1 re-phase controller 180 includes a means for counting pulses of the system clock, represented as a 24-bit counter with output register 183.
  • a means for counting pulses of the system clock represented as a 24-bit counter with output register 183.
  • die system clock produced by the output from VCO 111 is returned to its normal PLAY frequency. Alternately, the system clock can be returned to its normal play frequency at the same time or at some specified time after a return from the TSO mode is initiated.
  • the 24-bit counter 183 counts pulses of the output from the VCO 111 to provide a signal which indicates die phase error between the servo control signals and the video control signals.
  • the counter 183 receives the servo control signals representing the frame reset (FRAME RESET) signal, the field reset signal, and the multiplied frame reset (10X FRAME RESET) signal via a multiplexer 181. Further, the counter 183 receives the frame reference (FRAME REF) signal, the field reference (FIELD REF) signal, and die multiplied frame reference (10X FRAME REF) signal via second multiplexer 182.
  • the counter 183 which receives a respective input from one of the selected servo control signals and die video control signals, can identify a phase error for the selected frame reference, field reference or the multiplied frame reference (10X FRAME REF) signals, and direct its output via the eight-bit data bus to die system processor 120.
  • the frame reference (FRAME REF) signal can be used to reset the counter 183, which then counts pulses from the system clock 110 until a strobe pulse is received from the frame reset (FRAME RESET) signal.
  • die count produced by the counter 183 represents the time between the occurrence of a frame reference pulse and a frame reset pulse.
  • the detected phase error can be used to control the counter 112 so that die system can be accurately re-phased during a return from a TSO mode to a normal PLAY mode.
  • Measurement of the relative phase of, for example, the frame reset (FRAME RESET) signal and the frame reference (FRAME REF) signal is achieved by using d e frame reference (FRAME REF) signal pulse to load zero into the counter 183.
  • the frame reset (FRAME RESET) signal is then used to strobe the counter 183 and transfer its count into a storing means, such as a 24-bit register included within the counter 183.
  • the resulting phase measurement which is stored in the 24-bit register represents the phase error between pulses of these two signals.
  • This strobe also sets a latch within the counter 183, the output of which is connected to the system processor 120 via the data bus 121.
  • die 24— bit register of counter 183 includes tiiree eight-bit registers whose outputs can be read by the system processor sequentially.
  • the system processor 120 can compute the change in TSO speed required to re-phase the servo control signals 170 with the reference signals 171, and die time required to return to a frame pulse phased condition. If the measurement of phase error is made at a frame rate, then new TSO speed command values will be sent by the system processor 120 to the counter 112 via the data bus 121 at the frame rate. However, when the phase difference detected by the re-phase controller 180 becomes small, there is a point at which the TSO reference generator 100 of FIG. 1 will enter a hunting condition whereat complete equilibrium (for example, complete re-phasing of the servo control signals 170 and the reference signals 171) cannot be achieved. For example, the TSO speed command input to counter 112 would be updated by the system processor 120 at frame rate, and by changing the TSO speed by 1/1716 (525) for one frame, a phase correction of 525 clock periods would be introduced.
  • the incremental timing adjustment circuit 140 can be used to avoid a hunting condition of die re-phase controller 180 and to more accurately control a re-phasing of the servo control signals 170 and die reference video control signals 171 following a return transition from a TSO mode to a normal mode.
  • a line counter 141 is included in d e incremental timing adjustment circuit 140 for receiving the variable horizontal control signal output from the counter 112.
  • die variable horizontal control signal is input to the counter 112 in an exemplary embodiment, tiiose skilled in the art will recognize that any signal which can be derived (for example, multiple or fraction) from the horizontal rate F n can be used, including, for example, a horizontal pulse signal from servo clock signal generator 150.
  • the output of die line counter 141 is a first input to a ten-bit comparator 142.
  • a second input of the comparator 142 receives a predetermined value over data bus 121, established by the system processor 120 in response to an output of the phase measuring means 180, to produce an incremental timing adjustment control signal for the counter 112.
  • the incremental timing adjustment is achieved by regulating the counter 112 to alter the input to the phase detector 114 so that the VCO 111 can be adjusted at any point within die reproduction of a given frame.
  • the incremental timing adjustment circuit 140 can be used to adjust the clock signal generating means 110 following a return from a TSO mode to a normal mode.
  • the 24-bit counter 183 which measures the phase error between the reference sync signal CNENT SYNC and the reference frame reset signal, can count from 0 to 900,899 (525) or 0 to 1,079,999 (625) in 27 MHz clock periods, when the TSO speed is at the normal play speed. If the phase error is measured at a speed oti er than play speed, the counter 112 may, under certain circumstances, count to greater values. This situation will not permit the counter to overflow because its maximum count is 16,777,215.
  • the count value stored in the register 183 represents the delay of die reference frame reset signal relative to die CNENT SYNC frame pulse. If the count value is greater than 450,450 (525) or 540,000 (625) then die reference frame res ⁇ signal is considered to be advanced on the CNENT SYNC reference frame pulse by 900,900 (525) or 1,080,000 (625) minus the count value.
  • die system processor can, under software control, determine if t . TSO speed should be incremented or decremented to re-phase the two signals.
  • the quotient obtained by dividing the phase error measurement in clock periods by 525 or 625 determines the number of television frames over which a frequency correction needs to be made (coarse correction) by the re-phase controller 180 and the remainder determines the incremental phase correction required (fine correction).
  • the following example illustrates how the re-phasing can be accomplished. If die phase error measured is 3,562 clock periods then for the 525 standard the division of 3,562 by 525 gives a quotient of six and a remainder of 412. To correct the phase, the TSO speed can be increased by incrementing the 1,716 count of counter 112 by one to 1,717 for six frames and for 412 lines of the subsequent seventh frame. Alternately, the incremental phase correction could be applied for 68 lines in five of the six frames and for 72 lines in the sixth frame, by changing the count of counter 112 to 1,718 during this period.
  • the incremental phase correction can be implemented in the foregoing example by loading die number 412 into the comparator 142 via the data bus 121 for comparison with an output from the line counter 141. When the output of line counter 141 equals the value loaded into the comparator 142 (for example, during the sevendi frame in the first example noted above), the divisor of counter 112 can be returned to its normal PLAY mode value.
  • the incremental correction does not have to be applied to only one television frame but can be distributed over several frames by appropriate division of die remainder. It should be noted tiiat the coarse and fine frequency/ hase control system for controlling counter 112 can, under appropriate software control, operate simultaneously to accelerate the re-phasing procedure.
  • the FIG. 1 apparatus 100 further includes means for generating the servo control signals 170 for the tape transport in response to the system clock signal.
  • die servo control signal generating means includes die servo clock signal generator 150 and a servo control signal generator 1600.
  • the servo control signals 170 are labeled in die upper right hand comer of the FIG. 1 ASIC and include an encoded servo reference signal, a CNENT SYNC output signal, a frame reset (FRAME RESET) signal, a field reset signal, and a multiplied frame reset (10X FRAME RESET) signal (the latter of which is here illustrated as ten times the frame reset (FRAME RESET) signal).
  • the servo control signal generator 1600 receives inputs from the servo clock signal generator 150.
  • the servo clock signal generator 150 includes means for identifying portions of lines of a video frame, represented as a line segment counter 152, in response to the system clock signal produced by die VCO 111 of the system clock generator 110.
  • the servo clock signal generator 150 includes means for counting the lines of a video frame, represented as a line counter 1100.
  • the line counter 1100 operates in response to the clock signal from die VCO 111 and a horizontal line pulse from line segment counter 152.
  • die line counter 1100, 1200 which is shown in greater detail in FIGs. 11 and 12, is locked in phase to the frame reference (FRAME REF) signal from the CNENT SYNC decoder 800.
  • FRAME REF frame reference
  • die line segment counter 152 and die line counter 1100, 1200 are disconnected from their respective reference signals so that the servo control signals can be produced at frequencies which are independent of the reference video control signals and die CNENT SYNC signal.
  • the servo control signal generator 1600 of the FIG. 1 embodiment includes a means for decoding a line segment, such as a line segment decoder 1620.
  • the decoder 1620 detects a line segment in response to the output from the line segment counter 152 to produce a signal of a predetermined pulse widtii based on die detection of each line in a video frame.
  • Outputs from the line segment decoder 1620 and the line decoder 1610 are directed to output gating logic 1630 of die servo control signal generator 1600, which decodes a video frame to produce the servo control signals 170.
  • the output gating logic 1630 uses the outputs from the line decoder 1610 to gate pulses produced by die line segment decoder 1620 and tiius produce die servo control signals 170 at output of the FIG. 1 ASIC.
  • the tine counter 1100 of the servo clock signal generator 150 of the mentioned servo control signal generating means can include a means for providing noise immunity, such as the noise immunity circuit 1110 of FIG. 11.
  • FIG. 11 is meant to also include reference to FIGs. 1 IA and 1 IB. While the exemplary noise immunity circuit 1110 of FIG. 11 has been incorporated into the line counter 1100, those skilled in the art will appreciate that a noise immunity circuit in accordance witii the present invention can be used with any synchronizing circuit.
  • reference pulses such as a frame reset reference pulse are not gated.
  • disturbances for example, noise
  • the present invention detects when the frame reset and or horizontal line reset pulses of a sync generator (or similar equipment) are synchronized, and once initial synchronism has been achieved, an acceptance window for any subsequent reset pulses is either considerably reduced or eliminated to ensure that extraneous pulses on the reset signal do not affect the synchronization.
  • the basic components of the line counter 1100 as illustrated in FIG. 11, are a 10- bit counter 1104 which counts inverted horizontal line pulses from the line segment counter 152 (FIG.
  • the frame lock detecting means detects when the system is frame locked to d e frame reference (FRAME REF) signal output from the CNENT SYNC decoder 800.
  • FRAME REF d e frame reference
  • noise immunity when a frame locked condition has been detected, noise immunity is provided by selectively gating reference pulses (for example, frame reset pulses) to a sync generator (for example, the TSO reference generator 100 of FIG. 1).
  • the noise immunity circuit 1100 includes a window generator 1112 for generating a window witii an exemplary width of two horizontal line periods (for example, a 2H window), and a reset enable means 1114 for selectively gating frame reset pulses to the counter 1104 during the 2H window.
  • the first counter is the line segment counter 152 (FIG. 1), which divides die high frequency clock of 27 MHz in component TV systems by F j , where the quotient equals 1716 (525) or 1728 (625), to produce a positive-going pulse which is one clock period wide (for example, 37 nanoseconds, or l/27MHz, wide).
  • This signal is inverted to provide die inverted H-rate waveform A of FIG. 13.
  • This H-rate waveform can be considered a horizontal line reset signal.
  • the positive-going pulse which is one clock period wide is used as the count enable of the counter 1104 in the line counter 1100, which divides by 525 or 625 to produce a frame rate signal.
  • the counter 1104 is reset by a frame reset pulse which can be derived from a second H-rate counter that is phase-locked to the horizontal reference sync.
  • a frame reset (FRAME RESET) signal is illustrated in waveform I of FIG. 13 and can be derived by decoding the COMPOSITE SYNC or other reference signal (for example, CNENT SYNC).
  • the frame reset pulse is of exacdy IH duration but is offset in time from the H rate waveform A, also derived from the CNENT SYNC, by approximately H 2. This offset permits the horizontal phase of waveform A to be adjusted by approximately plus or minus H/2 without the line counter shifting in phase by one horizontal line.
  • the counter 1104 is phased relative to horizontal sync by having the horizontal reset pulse (H PULSEZ) load a specific phasing number from the 12- bit register 1106. This allows the counter 1104 to be phased to any position in a IH period witii a resolution of 37 nanoseconds.
  • H PULSEZ horizontal reset pulse
  • Noise immunity is provided in FIG. 11 by generating the 2H window (waveform F in FIG. 13) at the same time a ripple carry-out is generated by the counter 1104.
  • This window tiierefore starts at a point in time approximately 1/2 horizontal line width (for example, H/2) before a frame reset pulse on line 1126 and finishes at a point in time approximately H/2 after the frame reset pulse on line 1126.
  • the frame reset (FRAME RESET) signal I is received at a point in time approximately halfway into the horizontal line number labeled 1023 in waveform B. This count corresponds to die maximum count of counter 1104. It will be appreciated that the difference between 1023 and 499 is 524, corresponding to the 525 horizontal line numbers associated with the (525) television standard.
  • the ripple carry-out of the counter 1104 occurs at count value 1023 and can be used to signal the end of a frame, thus avoiding any need to decode die counter output.
  • any count values if properly decoded, can be used to signify frame boundaries.
  • the counter 1104 Upon occurrence of a frame reset, the counter 1104 is loaded from register 1106 with die count value of 499 provided both an inverted horizontal pulse of waveform A and a clock pulse are present.
  • die ripple carry-out is actually decoded by a decoder 1118 one horizontal line number early (for example, at count 1022) as illustrated by waveform C in FIG. 13.
  • the decoded ripple carry-out is then reclocked via a one count delay 1120 (waveform D in FIG. 13).
  • the delay 1120 produces an output at the time count value 1023 is output by the counter 1104.
  • This output is re-clocked by a re-clock circuit 1122 (waveform E in FIG. 13).
  • 11 re-clocked delay 1120 is therefore equivalent to the ripple carry-out of the counter 1104, but because it is re-clocked by die delay 1120 and die re-clock circuit 1122, does not include the glitches normally found on the ripple carry-out output.
  • the 2H window signal gates the frame reset pulse (waveform I) on line number
  • the frame lock detector 1108 there is another mode of operation where the frame reset pulse to the line counter 1100 can be disabled under software control.
  • the frame lock detector is constandy checking to ensure that the re-clocked ripple carry-out pulse
  • waveform E and frame reset pulses (waveform I) are in a correct phase relationship.
  • the re-clocked ripple carry-out pulse should precede the frame reset pulse by approximately H 2. Once this condition is established, there is no need for the frame reset to provide a special load pulse to the counter 1104 because the counter will flywheel in the correct phase (for example, the counter will automatically reset after it generates a ripple carry-out pulse).
  • a signal for enabling frame reset can be set to a logic low level under software control to disable die frame reset pulse to the counter 1104. If there is a disturbance or change in the reference signal affecting the timing of the frame reset (FRAME RESET) signal, then die frame lock detector 1108 will detect die loss of frame lock and die system processor 120 will set the enable frame reset (EN FR RST) signal high after a short delay to reset the counter 1104 with d e new reference signal. With a very noisy reference signal this would be the preferred mode of operation.
  • FIG. 12 illustrates an exemplary embodiment of d e FIG. 11 circuit in greater detail.
  • the register 1206 (which is register 1106 in FIG. 11) includes d e 10 least significant bits (LSBs) of the registers labeled QDFF1, QDFF2, and QDFF3.
  • the 10-bit counter 1204 (which is 10-bit counter 1104 in FIG. 11) comprises
  • CNTR1, CNTR2, and CNTR3 are loaded with die number 499.
  • the ripple carry-out would be inverted and fed back to die synchronous load input of the counter.
  • the ripple carry-out is obtained by decoding count 1022 and then re-clocking at F ⁇ and die CLK rate to give a ripple carry-out equivalent signal, labeled RECLK RCO 1, which is the re-clocked ripple carry-out minus one.
  • the re-clocked ripple carry-out signal is fed to an input labeled Bl of OR-NAND gate 1236 (which is the OR gate 1128-NAND gate 1130 combination 1136 in FIG. 11), labeled BF1 and including OR gate 1228 and NAND gate 1230.
  • OR-NAND gate 1236 die re-clocked ripple carry-out signal is AND-ed witii die H-rate waveform A in FIG. 13 to become the counter load signal via an AND gate labeled AN4 in FIG. 12.
  • the reset enable means 1214 (which is the reset enable gate 1114 of FIG. 11) includes an AND gate labeled AN1. To synchronize the counter 1204 (which is 10-bit counter 1104 in FIG. 11), the frame reset pulse is applied to the other input labeled B2 of OR-NAND gate 1236 via the AND gate 1214.
  • AND gate 1214 is enabled by an enable frame reset signal labeled EN FR RST, under system processor control, and the signal from a NAND gate 1232 labeled NA5 which is held high when either the frame lock signal labeled FRAME LOCK is low or the delayed lock signal labeled DLYD CLOCK is held low under system processor control. This pulse forces the counter 1204, 1104 to the load number set in the registers 1206, 1106 so that the signal RECLK RCO 1 and FRAME RESET occur at the same time once synchronism is achieved.
  • the frame lock detector 1208, 1108 includes D flip-flops labeled DFF1, DFF2 (for producing waveforms L and M of FIG. 13), an inverter labeled INV1, and an AND gate labeled AN2 (for producing waveform P of FIG. 13) which use the RECLK RCO 1 and its inverted form to clock the FRAME RESET pulse in DFF1 and DFF2.
  • the frame lock detector also includes a D flip-flop labeled DFF6.
  • the frame lock detector circuit not only checks that die signal is high at the correct time but also verifies that it makes a low-to-high transition at die expected time. Therefore DFF1 QZ is clocked high and DFF2 Q is clocked high to enable AND gate AN2. If the FRAME RESET input was stuck high for some reason, then an erroneous frame lock condition would not be detected. The actual FRAME LOCK signal is generated one line period later when D flip-flop DFF6 is clocked by die trailing edge of die 2H window signal from DFF3 QZ.
  • the 2H window generator 1212, 1112 includes D flip-flops labeled DFF3, DFF4,
  • DFF5 and an AND gate labeled AN3 configured as a pulse generator which is triggered by the count value 1022 output. Triggering of the first flip-flop DFF3 of the pulse generator is enabled at the trailing edge of die count value 1022 output at the same time that the H PULSE is present at NAND gate NA6. DFF4 Q is triggered high one H PULSEZ period later and DFF5 QZ goes low two H PULSEZ periods later to clear DFF3 via AN3 and tiius end die 2H window. Waveforms F, G and H, associated with the 2H window generator are illustrated in FIG. 13.
  • the negative-going 2H wide pulse from DFF3 QZ is fed to one input of the three input NAND gate 1232, 1132, labeled NA5 in FIG. 12.
  • the other two inputs to NA5 are the DLYD LOCK and the FRAME LOCK signals.
  • the output of the NAND gate 1232,1132 (for example, NA5) is re-clocked in a D flip-flop 1238,1138, labeled DFF10, to produce a gated 2H window represented as waveform K in FIG. 13.
  • the 2H WINDOW pulse from the NAND gate NA5, when fed to an AND gate 1234, 1134, labeled AN6, enables die FRAME RESET pulse only (for example, waveform J in FIG. 13). Thus, no other extraneous pulses which might be on this signal line under adverse system operating conditions will affect the gated frame reset signal.
  • the condition of the FRAME LOCK signal is constantly monitored by die system processor. As mentioned previously the FRAME LOCK signal goes active high at the trailing edge of the 2H window if the RECLK RCO 1 and FRAME RESET pulses are correcdy phased.
  • the DLYD LOCK signal is under control of the system processor and can be either left at a logic high continuously or switched high at some programmed time after the FRAME LOCK signal goes high. If either of these inputs to NA5 is low, the output of NA5 will be high and this will continuously enable the AND gate 1214, 1114 if the enable frame reset signal (EN FR RST) is also high.
  • the FRAME LOCK and DLYD LOCK signals are both high, the 2H window signal from DFF3 QZ is inverted by NA5 to become the positive-going 2H WINDOW signal.
  • die enable frame reset signal (EN FR RST) is set low by the system processor, then the FIG. 12 circuit is immune to all extraneous pulses on the FRAME RESET signal line. If the FRAME RESET signal is lost or changes its phase suddenly, die FRAME LOCK signal will go low and the system processor, under software control, can re-enable the FRAME RESET signal by setting EN FR RST high and DLYD LOCK low.
  • FIGs. 14, 15, and 16 features of an exemplary encoded servo reference signal in accordance with the present invention will be described with respect to FIGs. 14, 15, and 16.
  • the servo control signal generator 1600 of FIGs. 1 and 16 has been described as producing an encoded servo reference signal 170. While conventional servo reference signals can be used, exemplary embodiments of die present invention encode die servo reference signal with frame or color frame identification information. In addition to an encoded reference signal, an exemplary encoder can also pass the individual, uncoded reference signals to an output as illustrated by die upper three signals shown to the right hand side of FIG. 16.
  • Conventional servo reference signals include three separate signals: a servo reference signal (for example, typically 180 Hz (525) or 200 Hz (625)), a servo field reference (FIELD REF) signal and a servo frame/color frame reference (FRAME REF) signal (a color frame typically comprises two frames for (525) and four frames for (625)). While such signals can be used witii accordance with the present invention, the transmission of three signals requires three wires. Three wires are required because these signals are of identical pulse shapes with different repetition rates. Thus, possible skew between pulse edges can cause problems in a servo system.
  • a servo reference signal for example, typically 180 Hz (525) or 200 Hz (625)
  • FEF servo field reference
  • FRAME REF servo frame/color frame reference
  • FIG. 14 shows an encoded servo reference signal which includes basic servo reference pulses at 180/200 Hz modified to further include frame or color frame pulses.
  • a pulse widtii of H/8 for the servo reference pulses for example, eight microseconds for 625
  • the decoding of die line segment counter is simplified in the pulse generator.
  • Encoding of die servo reference pulses includes modifying one in six (525) or one in eight (625) of these pulses by inserting a positive-going pulse of one microsecond duration at a location one microsecond after the start of the pulse used to represent the frame pulse. If the color frame identification (CF IDENT) is being encoded instead of the frame identification (FR IDENT), then one in twelve (525) or one in 32 (625) of the reference pulses is modified (for example, since a color frame typically includes two frames for 525 and four frames for 625). The use of color frame identification is typically only necessary for composite television recorders. The location of the frame or color frame IDENT pulse is on line number 1, field 1, for 525 and 625 television standards using conventional line numbering schemes (see, for example, CCIR Rep. 624-4 pages 23 and 22, respectively).
  • FIGs. 14 and 15 show IDENT phasing relative to a COMPOSITE SYNC output in a sync generator ASIC embodiment of this encoding scheme.
  • FIG. 16 is a block diagram of an exemplary embodiment of the servo reference pulse generator and encoder. Features of the FIG. 16 embodiment have been correlated to features illustrated in the TSO reference generator of FIG. 1. Operation of the FIG. 16 circuit is similar to that described with respect to FIG. 1, except that a square wave is generated and encoded witii the IDENT pulses of FIGs. 14 and/or 15.
  • FIG. 17 is a block diagram of a decoder which can be included in tape transport devices to decode die signals produced by die FIG. 1 TSO reference generator (for example, to decode by extracting the three field, frame, and color frame signals from an encoded servo reference signal which has been formatted as described with respect to FIGs. 14, 15 and 16).
  • FIG. 17 is meant to also include reference to FIGs. 17A, 17B and 17C.
  • FIG. 18 is a more detailed diagram of an exemplary implementation of the FIG. 17 decoder for possible inclusion in an ASIC design.
  • reference to FIG. 18 is meant to also include reference to FIGs. 18 A, 18B, 18C, 18D, 18E, 18F, 18G and 18H.
  • the FIG. 17 decoder has four modes of operation which are determined by two control signals referenced herein as FR CFZ and CF RAND/NORMZ (see FIG. 18).
  • the FR CFZ control signal determines a counter 1700 (CNTRl) count range and therefore whether frame or color frame pulses are produced by die decoder.
  • the CF RAND/NORMZ control signal controls the synchronization of the counter 1700 to be either normal (frequency synchronized to a frame rate signal, and phase synchronized to a color frame boundary) or random (frequency synchronized to frame rate, but not necessarily phase synchronized with color frame boundary).
  • the FIG. 17 decoder receives an encoded servo reference signal with color frame identification and synchronizes to this signal to produce a color frame pulse.
  • the servo reference signal is encoded witii frame pulses, there will be no reference frame/color frame pulse (for example, the FIG. 18 output REF FRAME/CFZ) produced by d e decoder.
  • the output REF FRAME/CFZ is always a frame rate pulse which is synchronized to the frame or color frame IDENTs (for example, frame or color frame boundaries) of die encoded servo reference signal. Therefore a color frame pulse is not generated in MODE 2.
  • a color frame pulse is always generated on the output REF FRAME/CFZ irrespective of the encoded servo reference signal IDENT being frame or color frame.
  • the resulting pulse is randomly phased with die color frame boundary, and synchronization of counter CNTRl is slower because the color frame IDENTs are divided by two (525) or four (625).
  • MODE 4 is similar to MODE 2 except that the frame rate pulse is randomly synchronized with the frame IDENT (for example, frame rate pulses generated may or may not coincide with frame boundaries). This mode would not normally be used.
  • the output pulse at OS1 QZ of one-shot 1702, 1802 is negative-going and of five microseconds duration. This is AND-ed with the encoded servo reference signal in an AND gate 1732, 1832 labeled in FIG. 18 as AN1 and removes any encoded pulse which exists in the 180/200 Hz encoded servo reference signal.
  • the output of the AND gate 1732, 1832 is input via an inverter 1740, 1840 to the counter 1700, 1800 as a clock input.
  • the output OS1-Q of the one-shot 1702, 1802 also triggers a one-shot 1704, 1804 which is programmed in an exemplary embodiment for a period of approximately 1.5 microseconds so tiiat the trailing, positive-going edge coincides with a location mid-way along the FIG. 14 frame/color frame identification pulse if present.
  • a detector 1706, 1806 formed, for example, as D flip-flop labeled DFF2, receives the encoded servo reference signal as its data input. If the detector 1706, 1806 detects the IDENT pulse is present, DFF2 Q is clocked high and enables a NAND gate 1708, 1808 labeled NA1.
  • AN1 for example, AN1-Y
  • DFF3-Q goes high and the output of the NAND gate 1708, 1808 goes low.
  • DFF4-QZ of a delay pulse generator 1734, 1834 is clocked low and this couples back through an AND gate AN2 to clear D flip-flops DFF1, DFF3 (of the delay pulse generator 1734, 1834) and DFF2 (of the IDENT pulse detector 1706, 1806).
  • This action inhibits NAND gate 1708, 1808 and forces the signal at NAl-Y high again.
  • the signal at NAl-Y is therefore nominally a negative-going pulse of one clock period duration.
  • die signal at NAl-Y is fed tiirough a multiplexer 1710, 1810 labeled MUX1 and an AND gate AN3 to provide a direct clear to the counter 1700, 1800, which is clocked by the leading edge of the 180 200 Hz, eight microsecond wide pulse.
  • Counter 1700, 1800 is arranged as a modulo-N counter where the division ratio N is determined by a count decoder 1712, 1812 and its feedback into the LOADZ input of the counter.
  • the counter 1700, 1800 is triggered by die servo reference pulses to provide a count value proportional to the number of servo reference pulses. This counter is arranged such that only zero can be loaded whenever the counter is reset.
  • the counter load signal is from the multiplexer 1714, 1814 labeled MUX2 which can select one of four decode numbers depending upon die mode of operation and the TV standard.
  • the counter 1700, 1800 will divide by 12, 32, 6, or 8.
  • the output of the counter 1700, 1800 feeds the decoder 1712, 1812 for decoding the following numbers: 2, 3, 5, 7, 8, 11, 15, 19, 23 and 27.
  • the decode for number 31 is provided by the ripple carry-out of counter 1700, 1800.
  • the negative-going pulses from this decoder then go to the AND gates labeled AN4, AN5, AN6, and AN7 which are used as the negative-OR function and tiien to die multiplexers 1714, 1716 and 1718 labeled MUX2, MUX3, and MUX4 to allow appropriate selection of the pulses for each output and TV standard.
  • die decoded reference signals are re-clocked in flip-flops
  • the output of the flip-flop 1720, 1820 is, in an exemplary embodiment, a negative going pulse at 30 Hz (525) or 25 Hz (625). Alternatively, this output can be divided by 2 (525) or by 4 (625) to give a color frame pulse.
  • the output from the flip-flop 1722, 1822 is similar to the undivided signal output by flip-flop 1720, 1820.
  • the output from the flip-flop 1724, 1824 is a negative going pulse which appears with a frequency of 60 Hz in an exemplary embodiment.
  • the output from the inverter 1738, 1838 is the inverted 180 Hz (525).
  • the random phase control mode is used to generate a color frame pulse randomly synchronized with respect to a color frame boundary. This mode is desirable if the IDENT pulse on the servo reference signal is at frame rate.
  • the frame rate IDENT pulses which normally clear counter 1700 are used to clock a counter 1726 (FIG. 17), 1826 (FIG. 18) of a random color frame generator 1736 (FIG. 17), 1836 (FIG. 18) which divides the pulses by four.
  • the decoder comprising inverters and NAND gates labeled in FIG.
  • INV2 INV3, NA2, NA3, and NA4 decodes 0 (625) as well as 0 and 2 (525) depending upon the TV standard selected for input to a NAND gate labeled NA3 via inverter INV1.
  • the decoder output is re-clocked in a D flip-flop labeled DFF5 and provides a gate signal to a NAND gate labeled NA5 such that either one in two (525) or one in four (625) frame rate pulses is gated through NA5 to the B input of the multiplexer 1710, 1810. If the control input CF RAND/NORMZ is set high, the gated frame rate signal, now at color frame rate, is fed via multiplexer 1710, 1810 to the clear input of counter 1700, 1800 to provide random synchronization.
  • FIG. 17 and FIG. 18 circuit reconstitutes the upper three output signals illustrated in the right hand side of FIG. 16 from the encoded servo reference signal.
  • the FIG. 1 embodiment includes means, such as an audio control signal generator 130, for generating an audio control signal in response to the system clock represented by die VCO 111 of system clock signal generator 110.
  • the audio control signal generator 130 includes a means for generating an audio clock signal, represented as a 24.576 MHz L/C VCO 132 and a divider represented as a 10- bit binary counter 135. Further, a means for producing an audio clock reference signal includes a divider 133 for dividing the output of the VCO 111 by, for example, 1125 to produce a variable clock frequency of 24 KHz. The variable audio clock signal produced by the divider 133 is input to a phase detector 134 which receives the 24 KHz audio clock signal from counter 135 at a second input.
  • variable audio clock signal and die audio clock signal are of equal frequency and phase such that inputs to the phase detector 134 should be in phase (for example, pulses generated by the two outputs of phase detector 134 are nominally of equal pulse width and opposite polarity). Any phase error is detected and amplified in a phase error detector and amplifier 131 and used to alter the frequency of the VCO 132.
  • die variable audio clock signal varies by an amount proportional to d e variation of the output from the VCO 111.
  • phase detector 134 When compared with the audio clock signal produced by the counter 135, the phase detector 134 produces an error signal which is used to phase-lock die audio clock signal to the variable audio clock signal.
  • an audio control signal 177 produced at an output of the FIG. 1 ASIC can be used to time expand or to time compress the audio signal by varying the rate at which the digital audio data are clocked out.
  • die servo control signals 170 and the audio control signal 177 are phase-locked to the CNENT SYNC signal 191 which is input to the CNENT SYNC decoder 800 from CNENT SYNC generator 700 of video control signal generator 190.
  • the servo control signals 170 and the audio control signal 177 are phase-locked with the video control signals 171.
  • the frequency and phase of the 27 MHz VCO 111 are controlled via phase detector 114 and error amplifier 113 of system clock signal generator 110 such that the variable horizontal (VAR H) control signal produced by die counter 112 in system clock signal generator 110 is synchronized to the horizontal reference (HORIZ REF) signal produced by the CNENT SYNC decoder 800.
  • the variable horizontal (VAR H) control signal produced by die counter 112 produces a pulse to control phasing of the line segment counter 152 of servo clock signal generator 150 via a "hard" reset signal 119 which is enabled in PLAY mode or disabled in the TSO mode by the system processor 120.
  • the frame reference (FRAME REF) signal from the CNENT SYNC decoder 800 is applied to the line counter 1100 as a "hard” reset. This reset is disabled during a TSO mode.
  • the servo control signals 170 produced in the upper right hand comer 170 of the FIG. 1 ASIC are 180 Hz (525) or 200 Hz (625), but field and frame pulses are also generated.
  • the basic servo reference signal frequency of 180 Hz can alternatively have the frame or color frame pulses encoded onto it.
  • the CNENT SYNC signal produced in d e upper right hand portion 170 of the FIG. 1 ASIC is a synchronizing signal which is similar to a conventional COMPOSITE SYNC signal in that it can carry timing information for horizontal, field and frame rate synchronization.
  • the multiplied frame reset (10X FRAME RESET) signal can be used as a high frequency system processor interrupt and/or as a timing pulse in the phase-measuring section of the FIG. 1 ASIC.
  • a TSO can be implemented by producing data on the data bus which changes the divisor in the counter 112 and alters the output of the VCO 111. While it is relatively simple matter to alter the divisor and enter the TSO mode in accordance with the present invention, exiting the TSO mode back to die normal PLAY mode without any servo or audio disturbance is significandy more difficult.
  • TSO is initiated as follows. Immediately prior to the TSO operation, the pulse generation circuits are locked to d e CNENT SYNC signal. However, in the TSO mode, the resets of the line counter 1100 and LS counter 152 are switched off because output pulses can now be varied in frequency by virtue of the variable horizontal control signal produced by the counter 112.
  • both die line segment counter 152 and the line counter 1100 have their resets inhibited by a command signal from the system processor 120 via the data bus 121.
  • a pulse of the frame reset (FRAME RESET) signal produced by die output gating logic 1630 will be at some unknown phase relative to a pulse of the frame reference (FRAME REF) signal produced by the CNENT SYNC decoder 800.
  • die foregoing situation is avoided by precisely controlling a phase-locked return from the TSO mode into a normal PLAY mode.
  • Reversion to normal play only occurs when the phase of the pulses in the frame reset (FRAME RESET) signal and die frame reference (FRAME REF) signal are identical.
  • FRAME RESET frame reset
  • FRAME REF die frame reference
  • This is achieved by measuring the phase of these signals a short time before the TSO mode is ended such tiiat the speed of die TSO mode can be controlled in small increments until the frame reset (FRAME RESET) signal and the frame reference (FRAME REF) signal are phase-locked.
  • the TSO speed can be reset to a normal play speed prior to the measurement, although this is not essential if compensation for the speed is made to die measurement.
  • die FIG. 1 ASIC includes a multiplied frame reset (10X FRAME RESET) signal 170 and multiplied frame reference (10X FRAME REF) signal 178.
  • phase measurement can be performed at either a field rate or at a multiplied (for example, ten times or 10 x) frame rate.
  • multiplied frame reset 10X FRAME RESET
  • 10X FRAME REF multiplied frame reference
  • the horizontal reference presence detector 173 and die frame reference presence detector 174 can, in an exemplary embodiment, be implemented as digital retriggerable one- shots. Outputs 175, 176 from these one-shots can be used to illuminate LEDs on a printed wiring assembly and to provide a warning to the system processor 120 via the data bus 121 that a properly decoded CNENT SYNC signal is not detected.
  • the horizontal reference presence detector 173 can also be used to switch the control voltage input to the VCO 111 output such that in the absence of a reference CNENT SYNC input, the VCO control voltage is set to a fixed reference voltage to provide the 27 MHz frequency.

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Abstract

Procédé de commande de modification de la vitesse de défilement d'une bande par lequel on fait varier la fréquence d'un signal de référence servo, en même temps que sont générées des horloges audio variant proportionnellement à la référence servo. Le système présente également la possibilité de mesurer la différence de phase entre des signaux générés en mode de fonctionnement modifié (quand la vitesse est nominale) et les signaux de référence, sur lesquels ces signaux seraient synchronisés en mode lecture normal. Ceci de telle sorte qu'un système à unité centrale est capable de réduire à zéro l'erreur de phase entre les signaux générés et les signaux de référence, permettant ainsi le rétablissement du mode normal verrouillé.
PCT/US1993/008415 1992-12-23 1993-09-08 Systeme de commande de modification de la vitesse de defilement d'une bande comprenant la generation d'une reference servo et d'une horloge audio WO1994015336A1 (fr)

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US07/996,002 1992-12-23

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106500A2 (fr) * 1982-09-17 1984-04-25 Ampex Corporation Servo-circuit de cabestan avec verrouillage de la prédominance de vitesse de bande sur une valeur de référence pour un enregistreur à bande vidéo
US4716473A (en) * 1982-08-09 1987-12-29 Nec Corporation Device for modifying program duration on a tape player
EP0337582A2 (fr) * 1982-09-17 1989-10-18 Ampex Systems Corporation Système d'asservissement pour enregistreur vidéo pouvant se verrouiller à grande vitesse sur une piste de commande
EP0370631A2 (fr) * 1988-11-23 1990-05-30 Ampex Corporation Méthode et appareil pour un fonctionnement à priorité de vitesse de bande lors de la restitution audio hélicoidale
WO1991006101A1 (fr) * 1989-10-23 1991-05-02 Matsushita Electric Industrial Co., Ltd. Dispositif de reproduction de signaux numeriques a vitesse variable

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4716473A (en) * 1982-08-09 1987-12-29 Nec Corporation Device for modifying program duration on a tape player
EP0106500A2 (fr) * 1982-09-17 1984-04-25 Ampex Corporation Servo-circuit de cabestan avec verrouillage de la prédominance de vitesse de bande sur une valeur de référence pour un enregistreur à bande vidéo
EP0337582A2 (fr) * 1982-09-17 1989-10-18 Ampex Systems Corporation Système d'asservissement pour enregistreur vidéo pouvant se verrouiller à grande vitesse sur une piste de commande
EP0370631A2 (fr) * 1988-11-23 1990-05-30 Ampex Corporation Méthode et appareil pour un fonctionnement à priorité de vitesse de bande lors de la restitution audio hélicoidale
WO1991006101A1 (fr) * 1989-10-23 1991-05-02 Matsushita Electric Industrial Co., Ltd. Dispositif de reproduction de signaux numeriques a vitesse variable
EP0548359A1 (fr) * 1989-10-23 1993-06-30 Matsushita Electric Industrial Co., Ltd. Dispositif de reproduction de signaux numeriques a vitesse variable

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