WO1993021365A3 - Procede de realisation d'un reseau de discontinuites a la surface d'un substrat cristallin - Google Patents

Procede de realisation d'un reseau de discontinuites a la surface d'un substrat cristallin Download PDF

Info

Publication number
WO1993021365A3
WO1993021365A3 PCT/FR1993/000377 FR9300377W WO9321365A3 WO 1993021365 A3 WO1993021365 A3 WO 1993021365A3 FR 9300377 W FR9300377 W FR 9300377W WO 9321365 A3 WO9321365 A3 WO 9321365A3
Authority
WO
WIPO (PCT)
Prior art keywords
discontinuity
lattice
making
substrate
crystalline substrate
Prior art date
Application number
PCT/FR1993/000377
Other languages
English (en)
Other versions
WO1993021365A2 (fr
Inventor
Jean-Pierre Peyrade
Francoise Voillot
Michel Goiran
Original Assignee
Centre Nat Rech Scient
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre Nat Rech Scient filed Critical Centre Nat Rech Scient
Publication of WO1993021365A2 publication Critical patent/WO1993021365A2/fr
Publication of WO1993021365A3 publication Critical patent/WO1993021365A3/fr

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Composite Materials (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

La présente invention concerne un procédé de réalisation d'un réseau de discontinuités, à une ou deux dimensions, dans ou à la surface d'un substrat cristallin. Le procédé selon l'invention consiste à utiliser ou créer des zones favorables au développement de sources de dislocations dans ou à la surface d'un substrat, puis à activer des systèmes de cisaillement en soumettant le substrat à des champs de contraintes. Lorsqu'un ou deux champs de contraintes sont appliqués, on réalise respectivement un réseau de discontinuités à une ou deux dimensions. On obtient ainsi des réseaux dont chaque élément (fils ou boîtes) a soit deux, soit trois dimensions de l'ordre du nanomètre. Les réseaux de discontinuités obtenus peuvent servir de zones actives pour des composants micro-électroniques, ou servir de support pour la croissance contrôlée de matériaux destinés à réaliser des fils ou des boîtes quantiques par exemple.
PCT/FR1993/000377 1992-04-14 1993-04-14 Procede de realisation d'un reseau de discontinuites a la surface d'un substrat cristallin WO1993021365A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR92/04874 1992-04-14
FR9204874A FR2689912A1 (fr) 1992-04-14 1992-04-14 Procédé de réalisation d'un réseau de discontinuités à une ou deux dimensions à la surface d'un substrat cristallin ou dans une structure complexe comportant un tel substrat.

Publications (2)

Publication Number Publication Date
WO1993021365A2 WO1993021365A2 (fr) 1993-10-28
WO1993021365A3 true WO1993021365A3 (fr) 1993-12-23

Family

ID=9429080

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR1993/000377 WO1993021365A2 (fr) 1992-04-14 1993-04-14 Procede de realisation d'un reseau de discontinuites a la surface d'un substrat cristallin

Country Status (2)

Country Link
FR (1) FR2689912A1 (fr)
WO (1) WO1993021365A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2839505B1 (fr) * 2002-05-07 2005-07-15 Univ Claude Bernard Lyon Procede pour modifier les proprietes d'une couche mince et substrat faisant application du procede

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0232082A2 (fr) * 1986-01-24 1987-08-12 University of Illinois Procédé de dépôt d'un matériau semi-conducteur et dispositif formé par ce procédé
JPH01138200A (ja) * 1987-11-26 1989-05-31 Nec Corp 転位制御方法
JPH02134887A (ja) * 1988-11-16 1990-05-23 Hitachi Ltd 半導体レーザ素子及びその製造方法
GB2247346A (en) * 1990-08-24 1992-02-26 Gen Electric Co Plc A method of forming a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0232082A2 (fr) * 1986-01-24 1987-08-12 University of Illinois Procédé de dépôt d'un matériau semi-conducteur et dispositif formé par ce procédé
JPH01138200A (ja) * 1987-11-26 1989-05-31 Nec Corp 転位制御方法
JPH02134887A (ja) * 1988-11-16 1990-05-23 Hitachi Ltd 半導体レーザ素子及びその製造方法
GB2247346A (en) * 1990-08-24 1992-02-26 Gen Electric Co Plc A method of forming a semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 13, no. 394 (C - 631)<3742> 31 August 1989 (1989-08-31) *
PATENT ABSTRACTS OF JAPAN vol. 14, no. 371 (E - 963) 10 August 1990 (1990-08-10) *

Also Published As

Publication number Publication date
FR2689912A1 (fr) 1993-10-15
WO1993021365A2 (fr) 1993-10-28

Similar Documents

Publication Publication Date Title
EP0328405A3 (fr) Structure semi-conductrice et méthode de fabrication
CA2097472A1 (fr) Procede de production de gros monocristaux
EP0399483A3 (fr) Procédé de production de monocristaux d&#39;un matériau à phase haute-pression
CA2051154A1 (fr) Methode de fabrication de composants electroniques, electro-optiques et optiques
EP0178673A3 (en) Epitaxial layer structure grown on graded substrate and epitaxial layer structure grown on graded substrate and method of growing the same method of growing the same
CA2107174A1 (fr) Oxyde de magnesium epitaxial utilise comme couche tampon sur des semiconducteurs tetrahedraux
GB2080271B (en) Molecular beam deposition using gaseous source of group v element
EP0352472A3 (fr) Hétéroépitaxie de matériaux semiconducteurs à résaux inégaux
EP0909841A4 (fr) Procede de cristallogenese, element solide et dispositif de cristallogenese utilises dans ledit procede
CA2030825A1 (fr) Methode de formage d&#39;une diode shottky
EP0253611A3 (fr) Procédé pour la croissance épitaxiale de l&#39;arséniure de gallium sur le silicium
SG47931A1 (en) Semiconductor structures and a method of manufacturing semiconductor structures
CA2084272A1 (fr) Methode de fabrication pour dispositif a jonction de josephson ayant un lien faible creer a la limite de grains artificiels
EP0363554A3 (en) Process and apparatus for producing epitaxially and/or highly texturally grown, high tc-oxide superconductor films, lacking in foreign phases, on substrates
MY112348A (en) Iii-v/ii-vi semiconductor interface fabrication method
EP0177903A3 (en) Semiconductor device having a gallium arsenide crystal layer grown on a silicon substrate and method for producing it
WO1993021365A3 (fr) Procede de realisation d&#39;un reseau de discontinuites a la surface d&#39;un substrat cristallin
Schowalter Heteroepitaxy and strain: applications to electronic and optoelectronic materials
EP0203578A3 (fr) Dispositif semi-conducteur à couche isolante épitaxiale et son procédé de fabrication
GB2202371B (en) Semiconductor device
EP0630994A4 (fr) Procede de synthese de diamant en phase vapeur.
JPS57128092A (en) Imbedded type semiconductor laser device
GB2146259B (en) Method of growing ingaasp on inp substrate with corrugation
ATE190649T1 (de) Verfahren zum züchten einer zellart im kokulturverfahren mit leberzellen
CA2038601A1 (fr) Procede de fabrication de pellicule supraconductrice a base d&#39;oxyde

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

AK Designated states

Kind code of ref document: A3

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase