WO1993016535A1 - Procede de suppression du sautillement de l'indicateur dans un desynchronisateur - Google Patents

Procede de suppression du sautillement de l'indicateur dans un desynchronisateur Download PDF

Info

Publication number
WO1993016535A1
WO1993016535A1 PCT/FI1993/000045 FI9300045W WO9316535A1 WO 1993016535 A1 WO1993016535 A1 WO 1993016535A1 FI 9300045 W FI9300045 W FI 9300045W WO 9316535 A1 WO9316535 A1 WO 9316535A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
pointer
occurrence
desynchronizer
voltage
Prior art date
Application number
PCT/FI1993/000045
Other languages
English (en)
Inventor
Reino Urala
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to DE4390463T priority Critical patent/DE4390463T1/de
Priority to GB9416172A priority patent/GB2279522B/en
Publication of WO1993016535A1 publication Critical patent/WO1993016535A1/fr
Priority to SE9402708A priority patent/SE518361C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET

Definitions

  • the invention relates to an arrangement for suppressing pointer justification jitter in a de ⁇ synchronizer in a digital transmission system, the desynchronizer comprising a data buffer means; a data buffer write address counter controlled by a write clock; a data buffer read address counter controlled by a read clock; and a phase-locked loop comprising a phase comparator means, a loop filter means and a voltage-controlled oscillator means for adjusting said read clock on the basis of the phase difference between the read and write clocks.
  • the CCITT recommendations G.707, G.708 and G.709 specify a synchronous digital hierarchy SDH, which enables the multiplexing of the signals of e.g. existing PCM systems, such as 2, 8, 34 and 140 Mbit/s, into a synchronous frame of 155 Mbit/s called STM-1 (synchronous transfer module).
  • STM-1 synchronous transfer module
  • the structure of the STM-1 frame is illustrated in Figure 1.
  • the frame is usually shown as a unit comprising nine lines each having 270 bytes.
  • the first nine bytes on each line contain a section overhead and AU pointer bytes.
  • the remaining portion of the transfer frame STM-1 con ⁇ tains one or more administration units AU.
  • the transfer frame STM-1 may contain several lower-level administration units AU in each one of which a corresponding virtual container VC of the lowest level is placed.
  • the VC-4 comprises a 1-byte path overhead POH and a 240-byte information bit group at the start of both of which a special control byte is placed. Some of the control bytes are used e.g.
  • mapping of the information signal into the transfer frame STM-1 is described e.g. in the patent applications AU-B-34639/89 and FI-914746.
  • Each byte in the unit AU-4 has a position number.
  • the above-mentioned AU pointer contains the position of the first byte of the container VC-4 in the unit AU-4.
  • so-called positive or negative pointer justifications can be performed at different locations in the SDH network. If a VC having a certain clock frequency is applied to a network node operating at a clock fre ⁇ quency lower than the above-mentioned clock frequency of the VC, the data buffer will be filled up. This requires negative justification: one byte is trans ⁇ ferred from the received VC into the overhead section while the pointer value is decreased by one.
  • the data buffer tends to be emptied, which calls for positive justification in which a stuff byte is added to the VC and the pointer value is incremented by one.
  • Bit justification used in mapping as well as pointer justification cause phase jitter, which should be compensated for by the desynchronizer on leaving the SDH network.
  • Phase jitter and its compensation are described e.g. in Simulation Results and Field Trial Experience of Justification Jitter, Ralph Urbansky, 6th World Tele ⁇ communication Forum, Geneva, 10-15 October 1991, International Telecommunication Union, Part 2, Vol III, p. 45 to 49.
  • the prior art desynchronizers comprise a data buffer with an associated analog phase-locked loop (P L) which phase-locks the read clock of the data buffer to the write clock.
  • P L phase-locked loop
  • the PLL operates in the same way as a lowpass filter, it removes jitter except for the most low-frequency jitter components.
  • the pointer justi ⁇ fication of the SDH typically generates much more intensive jitter components than bit justification as individual phase discontinuities in the pointer jus ⁇ tification are e.g. 8 or 24 frame intervals UI and as the frequency of occurrence of phase discontinuities induced by pointer justifications may represent a very low frequency difficult to filter in the PLL of the desynchronizer.
  • FIGS. 2 and 3 show how the jitter peaks induced by two pointer justifications of 24 UI (measured from the output of the desynchronizer through a measuring filter spe ⁇ cified by the CCITT) can be reduced to an acceptable maximum level of about 0.2 UI by drastic filtering when the bandwidth of the PLL at e.g. 140 Mbit/s is about 2 Hz.
  • no pointer justifications are needed in normal operation, and only interface bit justifications are active.
  • the dimen ⁇ sioning of the PLL of the desynchronizer on the basis of pointer justifications is unreasonable as the bandwidth of the PLL could be even ten times higher from the viewpoint of bit justification.
  • the locking of the PLL would thereby also be more reliable and the locking time would be substantially shorter.
  • bit leaking in which pointer induced phase discontinu ⁇ ities are removed by a non-linear process (in the time domain), whereby incoming data bits are process ⁇ ed by a separate serial buffer so that the phase of the write clock and data applied to the buffer of the desynchronizer is advanced (or retarded) periodical ⁇ ly, and so a stepwise phase shift is converted into a linear phase shift taking place over a longer period of time.
  • the pointer justifications are thereby pro ⁇ Termind separately by a bit leaking buffer so that the bandwidth of the phase-locked loop of the desynchron ⁇ izer itself can be increased so as to meet the re ⁇ quirements of the bit justifications.
  • bit leaking is the bit-level serial data processing and the relatively complicated logic. It is further to be noted that it is not adequate that one pointer at a time can be processed but, in the worst case, the logic should be able to operate with tens of overlapping pointer justifications at different decay stages. Therefore the use of this technique in a high-rate 140 Mbit/s desynchronizer is not advisable due to the increased power consumption, for instance.
  • the object of the invention is to provide a simple and economical arrangement for suppressing pointer jitter peaks, which is also suitable for the rate of 140 Mbit/s and even higher rates.
  • an arrangement according to the invention which is characterized in that the arrangement comprises means for positively con- trolling the phase-locked loop so as to limit, in synchronization with the time of occurrence of each pointer justification, the maximum amplitude of the phase jitter induced in an output signal of the de- synchronizer by said pointer justification.
  • the basic idea of the invention is that a com ⁇ pensation adjustment timed to coincide with the pointer justification is performed in the phase- locked loop itself so as to limit the abrupt phase jitter amplitude induced by the pointer justification and to "spread" the jitter.
  • the compensation adjustment is performed by summing a voltage pulse the front edge of which is coincident with the pointer justification with the input signal of the loop filter or with the control voltage of the loop oscillator.
  • the compens ⁇ ating voltage pulse is preferably integrated so that its front edge is coincident with but opposite to the voltage change caused by the pointer justification, whereas the back edge of the pulse falls slowly, e.g. exponentially.
  • the rising (or falling) front edge of the compensating pulse limits efficiently the abrupt jitter amplitude while the long exponentially falling (or rising) back edge "spreads" the phase jitter in- cuted by the phase discontinuity over a longer period of time, e.g. over 1 second.
  • the phase-locked loop comprises means for limiting the amplitude of the control voltage of the voltage- controlled oscillator for a predetermined period of time beginning from the time of occurrence of each pointer justification.
  • the limiting of amplitude level also inherently involves limiting the maximum amplitude of the pointer jitter at the output of the desynchronizer within predetermined maximum values.
  • a further embodiment of the invention comprises means for reducing the open loop gain of the phase- locked loop for a predetermined period of time beginning from the time of occurrence of each pointer. Due to the reduction of the gain the closed- loop bandwidth is instantaneously limited to such a low value that the phase jitter induced by the pointer justification is removed adequately.
  • the arrangement also performs the compensa ⁇ tion of phase discontinuities induced by bit justi ⁇ fication. In one embodiment of the invention, this is carried out by summing to the phase-locked loop a compensation pulse timed to coincide with each bit justification and similar to but shorter than the compensation pulse used in pointer justification.
  • FIG 1 illustrates the transfer frame STM-1 of the SDH system
  • Figures 2 and 3 illustrate a phase discontinu- ity occurring in the input of a prior art desynchron ⁇ izer and phase jitter present in the output, respectively, when the bandwidth of the phase-locked loop is about 2 Hz;
  • Figure 4 shows the schematic diagram of a desynchronizer according to the invention
  • Figures 5 and 6 are signal diagrams illustrat ⁇ ing a phase discontinuity at the input of the de ⁇ synchronizer of Figure 4 and a corresponding phase jitter at the output of the desynchronizer; and
  • Figure 7 is a schematic diagram illustrating two alternative ways of connecting the compensation signal to the phase-locked loop.
  • the frame structure STM-1 of the SDH system, the framing and the pointer and bit justifications were described above with reference to Figure 1.
  • the above-mentioned CCITT recommendations, the above-mentioned article by Ralph Urbansky, and the patent applications FI-914746 and AU-B-34639/89 are referred to.
  • the SONET system is described e.g. in To Know Your Sonet , Know Your VTs by Stephen Fleming, TE&M, June 15, 1989, p. 62 to 75.
  • FIG. 4 shows a desynchronizer according to the invention.
  • a digital serial synchronous signal such as an SDH signal consisting of STM-1 frames, is received at the input of a buffer memory 1, from where it is written byte by byte in accordance with addresses generated by a write address counter 2 to the buffer memory 1, and further read byte by byte in accordance with addresses generated by a read address counter 3 out of the buffer 1 so that a digital serial output signal DATA OUT with a desired trans ⁇ mission rate, e.g. 140 Mbit/s, is obtained from the desynchronizer.
  • the write address counter 2 generates write addresses in synchronization with a write clock CLK1.
  • the read address counter 3 generates read addresses in synchronization with a read clock CLK2.
  • the read clock CLK2 is phase-locked to the write clock CLK1 by a phase-locked loop (PLL) comprising a phase detector, a loop filter and a voltage-controlled oscillator.
  • PLL phase-locked loop
  • Signals CLK1/N and CLK2/N proportional to the write and read clocks are applied to the phase detector 4 from the counters 2 and 3, where N is a divisor dimensioned in accordance with the length of the buffer and the active range of the phase detector.
  • the phase detector 4 produces a voltage signal V : proportional to the phase difference between the signals CLK1/N and CLK2/N, and this volt ⁇ age signal is applied through a resistor R3 to an operational amplifier Al.
  • the operational amplifier Al with associated resistors R3, R5, R6, R7, C3 and condenser C4 forms a loop filter which determines the loop gain of the phase-locked loop.
  • the loop gain is selected so that an appropriate bandwidth is obtained.
  • the operational amplifier Al generates a control voltage V 3 applied to the control input of the voltage-controlled oscillator 5 so as to determine the frequency of the read clock CLK2 generated by the oscillator 5.
  • the phase-locked loop tends to adjust the frequency of the read clock CLK2 so that the phase difference between the clocks CLK1 and CLK2 is sufficiently small.
  • a desynchronizer circuit of this type and different variations thereof are well-known to one skilled in the art.
  • phase-locked loop (PLL) of the desynchron ⁇ izer shown in Figure 4 is not as such able to sufficiently suppress phase discontinuities, called pointer justifications herein, induced by the pointer justifications occurring in the incoming digital signal DATA IN.
  • pointer justifications phase discontinuities
  • the pointer jitter in the output of the desynchronizer can be suppressed satisfactorily by limiting the bandwidth of the PLL but the speed and reliability of the locking of the PLL are deteriorated at the same time.
  • the desynchronizer comprises a suppression circuit according to the invention, which positively controls the PLL in synchronization with the time of occurrence of each pointer justification so that the PLL limits the maximum amplitude of the phase jitter induced by said pointer justification, in the output signal of the desynchronizer.
  • the digital section of the desynchronizer produces signals indicating the times of occurrence and directions of the pointer justifications for its internal use, and these signals can also be utilized in the control of the compensation connection accord ⁇ ing to the invention.
  • Figure 4 shows the preferred embodiment of the invention, in which the CMOS logic of the desynchron ⁇ izer generates a three-level compensation pulse volt- age V 4 in which the front edges of the pulses coincide with the pointer justifications.
  • the positive pulse of the voltage V 4 corresponds to the positive pointer justification and the negative pulse corresponds to the negative pointer justification.
  • the pulse voltage V 4 is integrated by an AC-coupled integrator com ⁇ prising an operational amplifier A2 with associated external components Rl, R2, Cl and C2.
  • the integrator A2 integrates and inverts each pulse of the voltage V 4 , thus forming an exponential pulse having a rapidly rising front edge timed to coincide with the time of occurrence of the pointer justification but opposite in direction in relation to it, and a slowly exponen ⁇ tially falling back edge.
  • the output voltage V 2 of the integrator is summed by a resistor R4 with a voltage V x at the input of the lowpass filter Al .
  • the voltage V 2 can also be applied to some other point in the phase-locked loop, such as the control voltage V 3 of the VCO, as shown by the broken line 6.
  • the compensation has to be done so as to limit the rate of change of the voltage V 3 over a predetermined period of time.
  • the shape of the pulse V 2 has to be adapted to the output voltage of the filter Al at each specific point of addition.
  • FIG. 5 illustrates the effect of the jitter compensation ac ⁇ cording to the invention on the desynchronizer of Figure 4.
  • UI time intervals
  • the same pointer justification causes a concurrent positive pulse to occur in the voltage V 4 , which is integrated and added to the input of the filter Al as a voltage pulse V 2 opposite in direction in relation to the change of the voltage V-, so that the voltage pulse limits the maximum amplitude of the change of the control voltage V 3 of the oscillator means 5 caused by said pointer justification and thus also the jitter amplitude in the output signal of the desynchronizer measured through a measuring filter specified by the CCITT, as illustrated in the simulation of Figure 6.
  • the maximum amplitude of the phase jitter at the output at the time of occurrence of the pointer justification is clearly lower than e.g. in the case of Figure 3.
  • the long exponen- tially falling back edge of the compensation pulse V 2 "stretches" the phase jitter over a long period of time.
  • T 400 ms
  • this second pointer justification also occurs as phase jitter of opposite direction.
  • the rate of the desynchronizer is 140 Mbit/s
  • the bandwidth of the phase lock is about 10 Hz
  • the pulse length of the voltage V 4 is 250 ms.
  • the AC coupling of the integrator A2 is accomplished by a serial capacitor C2 in order that the dynamic range of the data buffer 1 would not be exceeded due to a plurality of successive pointers (for instance, one of the elements of the SDH network utilizes a local standby clock and thereby produces tens of pointer justifications per second).
  • the time constant of the AC coupling also shortens the total time constant to some extent.
  • the justification frequency in bit justifica ⁇ tion may represent the worst possible jitter fre ⁇ quency passing through the phase-locked loop, but as the duration of the phase discontinuities in bit justification is only one time interval, the low phase jitter induced by them has been insignificant as compared with the pointer jitter.
  • the pointer jitter is suppressed, and so the jitter caused by bit justification may also become problem- atic.
  • the circuit of Figures 4 and 6 may also be used for compensating the jitter induced by bit justifica ⁇ tion.
  • the CMOS logic would thereby provide not only pointer compensation pulses corresponding to the pointer justifications but also bit compensation pulses timed to coincide with bit justifications and having a duration precisely 1/8 or 1/24 of the pointer compensation pulses ( 8-bit or 24-bit pointer justification) .
  • Figure 7 shows another embodiment of the inven- tion, in which the phase-locked loop contains a clamping circuit positioned between the amplifier Al and the voltage-controlled oscillator 5.
  • the clamping circuit is controlled by the voltage V 4 so as to limit the control voltage V 3 between predetermined limit values for a predetermined period of time beginning from the time of occurrence of each pointer justification.
  • the open loop gain of the phase- locked loop can be decreased for a predetermined period of time beginning from the time of occurrence of each pointer justification.
  • the block 71 in Figure 7 may thereby be an amplifier or an attenuator the gain of which is adjusted by the voltage V 4 in syn ⁇ chronization with the occurrence of pointer justifications.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

L'invention concerne un agencement pour supprimer le sautillement de la justification de l'indicateur dans un désynchronisateur d'un système de transmission numérique, le désynchronisateur comprenant un tampon de données (1); un compteur d'adresses d'écriture (2) du tampon de données commandé par une horloge d'écriture (CLK1); un compteur d'adresses de lecture (3) du tampon de données commandé par une horloge de lecture (CLK2); et une boucle à verrouillage de phase comprenant un comparateur de phases (4), un filtre à boucle (A1) et un oscillateur contrôlé en tension (5) pour régler ladite horloge de lecture sur la base de la différence de phase entre les horloges d'écriture et de lecture. Selon l'invention, l'agencement comprend un moyen (A2, 71, 81) de commande directe de la boucle à verrouillage de phase permettant de limiter, d'une manière synchronisée avec le temps d'apparition de chaque justification de l'indicateur, l'amplitude maximum du sautillement de phase induit dans un signal de sortie (SORTIE DONNEES) du désynchronisateur par ladite justification de l'indicateur.
PCT/FI1993/000045 1992-02-14 1993-02-12 Procede de suppression du sautillement de l'indicateur dans un desynchronisateur WO1993016535A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE4390463T DE4390463T1 (de) 1992-02-14 1993-02-12 Unterdrückung von Pointerjitter in einem Desynchronisierer
GB9416172A GB2279522B (en) 1992-02-14 1993-02-12 Pointer jitter suppression in a desynchronizer
SE9402708A SE518361C2 (sv) 1992-02-14 1994-08-12 Dämpning av pekarjitter i en desynkronisator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI920643A FI90709C (fi) 1992-02-14 1992-02-14 Järjestely osoitinvärinän vaimentamiseksi desynkronisaattorissa
FI920643 1992-02-14

Publications (1)

Publication Number Publication Date
WO1993016535A1 true WO1993016535A1 (fr) 1993-08-19

Family

ID=8534632

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI1993/000045 WO1993016535A1 (fr) 1992-02-14 1993-02-12 Procede de suppression du sautillement de l'indicateur dans un desynchronisateur

Country Status (6)

Country Link
AU (1) AU3500693A (fr)
DE (1) DE4390463T1 (fr)
FI (1) FI90709C (fr)
GB (1) GB2279522B (fr)
SE (1) SE518361C2 (fr)
WO (1) WO1993016535A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995015042A1 (fr) * 1993-11-29 1995-06-01 Dsc Communications Corporation Appareil et procede pour l'elimination des sautillements de mappage
ES2102938A1 (es) * 1994-03-28 1997-08-01 Alcatel Standard Electrica Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.
WO1997050189A1 (fr) * 1996-06-25 1997-12-31 Telefonaktiebolaget Lm Ericsson Dispositif et procede de traitement de signaux redondants et systeme de telecommunications comprenant ce dispositif
WO1998028850A1 (fr) * 1996-12-20 1998-07-02 Siemens Aktiengesellschaft Procede et systeme de reconstitution du rythme a partir d'un signal numerique
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
US6587533B1 (en) 1996-12-17 2003-07-01 Nokia Corporation Method for attenuating transients caused by aligning in a desynchronizer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996698A (en) * 1989-10-23 1991-02-26 Rockwell International Corporation Clock signal resynchronizing apparatus
EP0435383A2 (fr) * 1989-12-23 1991-07-03 Philips Patentverwaltung GmbH Circuit d'adaptation de débit binaire
WO1991012678A1 (fr) * 1990-02-16 1991-08-22 Siemens Aktiengesellschaft Procede et dispositif de recuperation du rythme
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
EP0450269A2 (fr) * 1990-03-14 1991-10-09 Alcatel N.V. Dispositif de boucle de verrouillage de phase
EP0491054A1 (fr) * 1990-07-04 1992-06-24 Fujitsu Limited Circuit d'extraction de signaux asynchrones

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996698A (en) * 1989-10-23 1991-02-26 Rockwell International Corporation Clock signal resynchronizing apparatus
EP0435383A2 (fr) * 1989-12-23 1991-07-03 Philips Patentverwaltung GmbH Circuit d'adaptation de débit binaire
WO1991012678A1 (fr) * 1990-02-16 1991-08-22 Siemens Aktiengesellschaft Procede et dispositif de recuperation du rythme
EP0450269A2 (fr) * 1990-03-14 1991-10-09 Alcatel N.V. Dispositif de boucle de verrouillage de phase
EP0491054A1 (fr) * 1990-07-04 1992-06-24 Fujitsu Limited Circuit d'extraction de signaux asynchrones
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995015042A1 (fr) * 1993-11-29 1995-06-01 Dsc Communications Corporation Appareil et procede pour l'elimination des sautillements de mappage
ES2102938A1 (es) * 1994-03-28 1997-08-01 Alcatel Standard Electrica Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
WO1997050189A1 (fr) * 1996-06-25 1997-12-31 Telefonaktiebolaget Lm Ericsson Dispositif et procede de traitement de signaux redondants et systeme de telecommunications comprenant ce dispositif
US6463069B1 (en) 1996-06-25 2002-10-08 Telefonaktiebolaget Lm Ericsson Arrangement and method relating to a telecommunications system handling redundant signals
US6587533B1 (en) 1996-12-17 2003-07-01 Nokia Corporation Method for attenuating transients caused by aligning in a desynchronizer
WO1998028850A1 (fr) * 1996-12-20 1998-07-02 Siemens Aktiengesellschaft Procede et systeme de reconstitution du rythme a partir d'un signal numerique

Also Published As

Publication number Publication date
FI920643A (fi) 1993-08-15
SE9402708L (sv) 1994-08-12
GB2279522B (en) 1995-10-25
FI90709B (fi) 1993-11-30
FI920643A0 (fi) 1992-02-14
FI90709C (fi) 1994-03-10
DE4390463T1 (de) 1995-01-26
GB2279522A (en) 1995-01-04
SE9402708D0 (sv) 1994-08-12
SE518361C2 (sv) 2002-10-01
AU3500693A (en) 1993-09-03
GB9416172D0 (en) 1994-10-05

Similar Documents

Publication Publication Date Title
EP0626117B1 (fr) Desynchronisateur et procede pour supprimer le sautillement de l'indicateur dans un desynchronisateur
US5268936A (en) Synchronous digital signal to asynchronous digital signal desynchronizer
US5404380A (en) Desynchronizer for adjusting the read data rate of payload data received over a digital communication network transmitting payload data within frames
US5367545A (en) Asynchronous signal extracting circuit
EP0549125B1 (fr) Désynchroniseur de signaux numériques synchrones vers des signaux numériques asynchrones
US5457717A (en) Apparatus and method for eliminating mapping jitter
JP3092352B2 (ja) Ｓｏｎｅｔをｄｓ−ｎ信号に対して非同期化する装置及び方法
EP0473338B1 (fr) Synchronisation de bit à mémoire élastique
US5200982A (en) In-line piece-wise linear desynchronizer
US6415006B2 (en) Reducing waiting time jitter
US5796796A (en) Pointer adjustment jitter cancellation processor utilizing phase hopping and phase leaking techniques
EP0450269B1 (fr) Dispositif de boucle à verrouillage de phase
US6463111B1 (en) Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload
US20020186719A1 (en) Pointer adjustment wander and jitter reduction apparatus for a desynchronizer
US6658074B1 (en) Method and apparatus for reproducing clock signal of low order group signal
WO1993016535A1 (fr) Procede de suppression du sautillement de l'indicateur dans un desynchronisateur
US5499274A (en) Fractional bit-leaking clock signal resynchronizer for a high-speed digital communications system
US7440533B2 (en) Modulated jitter attenuation filter
JPH07226760A (ja) ポインタ調整イベント漏れ制御方法および装置
CA2063930C (fr) Desynchronisateur de conversion de signaux numeriques synchrones en signaux numeriques asynchrones
JP3140285B2 (ja) データレート変換装置
US6587533B1 (en) Method for attenuating transients caused by aligning in a desynchronizer
JPH07202868A (ja) データレート変換装置
Antry et al. Minimization of the accumulated phase change at the input of SDH/SONET desynchronizers
JPH06326694A (ja) データレート変換装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AU DE GB JP SE US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 94027083

Country of ref document: SE

WWP Wipo information: published in national office

Ref document number: 94027083

Country of ref document: SE

RET De translation (de og part 6b)

Ref document number: 4390463

Country of ref document: DE

Date of ref document: 19950126

WWE Wipo information: entry into national phase

Ref document number: 4390463

Country of ref document: DE

122 Ep: pct application non-entry in european phase