WO1993011508A1

WO1993011508A1 - Printer video processor

Info

Publication number: WO1993011508A1
Application number: PCT/JP1992/001557
Authority: WO
Inventors: Derek J. Lentz; Linley M. Young
Original assignee: Seiko Epson Corporation
Priority date: 1991-11-27
Filing date: 1992-11-27
Publication date: 1993-06-10
Also published as: JP3429296B2; JP2003335007A; JPH07501498A; JP3506335B2; JP3310287B2; JP2002358294A

Abstract

A video processor is provided for a printer controller to be situated locally to a printer. A microprocessor in the printer controller executes instructions and performs image processing, while the video processor provides for scan data fetches, serialization, and print engine synchronization as well as scan status and interrupt generation. The video processor accesses data in an external page memory, also called a frame buffer, by submitting requests to an I/O interface. Each request comprises an address with a corresponding data size. After the scan data request, the video processor updates the address and data size for the next request. Upon receipt of the requested data, the video processor sends the scan data serially to a printer engine. In order to supply an uninterrupted stream of scan data to the printer engine, the printer video processor must queue enough scan data to offset the latencies involved in processing the data requests to the page memory.

Description

D E S C R I P T I O N

Title of the Invention: PRINTER VIDEO PROCESSOR

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to a pending patent application entitled, "Single Chip Page Printer Controller", Serial No. 07/726,929 filed July 8, 1991, which is incorporated by reference as set forth in full hereinbelow.

BACKGROUNDOFTHEINVENTION

I. Field of the Invention

The present invention relates generally to controllers for peripheral printers, such as laser printers, and more particularly, to the printer video processor for synchronizing scan data to a printer engine.

II. Related Art

As shown in Figure 1, a page printer system typically has an instruction microprocessor 102, a printer video processor (PVP) 104, a page memory 106 (also known as a "frame buffer"), a serial communications interface 108, and a printer engine 110. Generally, the instruction microprocessor 102 executes a set of instructions to thereby generate data to be printed on a page of paper. The generated data is sent to the page memory 106, where it is retrieved by the printer video processor 104. The instruction microprocessor 102 also exchanges status signals with the printer video processor 104, as indicated by the bidirectional arrow 116.

The printer video processor 104 and printer engine 110 communicate via handshake control signals and clocks in order to control the frequency and timing of the scan data sent from the printer video processor 104 to the printer engine 110. The serial communications interface 108, such as a universal asynchronous receiver transmitter (UART), allows the instruction microprocessor 102 to directly communicate status information to the printer engine 110. In a copending application entitled "Single Chip Page Printer Controller" with

Serial No. 07/726,929, a page printer controller in the form of a very large scale integrated circuit (VLSIC) semiconductor chip was suggested for the control of the printer engine 110. As shown in Figure 2, the page printer controller 202 is situated in close proximity to the printer engine 110 in a location remote from a host computer system 203. Generally, the page printer controller 202 is designed to

TE SHEET access the scan data stored in system memory 204 and send the data to the printer engine 110 for actual printing.

The VLSIC page printer controller 202 has the instruction microprocessor

102, the printer video processor 104, the serial communications interface 108, an I/O interface 206, and a memory system 208. The instruction microprocessor 102 can implement coordinate transformation, clipping, scaling, and rasterization of the scan data, as well as run diagnostics. The I O interface 206 essentially serves as an interface for all of the internal components of the page printer controller 202, as indicated by the various arrows 210-216, as well as an interface for all of the external peripherals connected to the I/O bus network 217. Furthermore, the memory system 208 comprises high speed caches which are loaded with data from the page memory 106 in system memory 204.

In operation, the printer video processor 104 accesses data in the external page memory 106 by submitting requests to the I/O interface 206. For each request, the printer video processor 104 sends to the I/O interface 206 an address location within the external page memory 106 and a data size. After the request, the printer video processor 104 updates the address and data size for the next request.

In the meantime, the I/O interface 206 stores the address and data size until ready to be used by the memory system 208. The memory system 208 uses this information to access the correct scan data from the external page memory 106 and return data to the printer video processor 104. The printer video processor 104 then stores the data and sends the data serially to the printer engine 110. The serial communication is synchronous with the clock of the printer engine 110. In order to supply an uninterrupted stream of scan data to the printer engine 110, the printer video processor 104 must queue enough scan data to offset the latencies involved in processing the data requests to the page memory 106.

Using the page printer controller 202 has many significant advantages. The page printer controller 202 can provide for direct memory access (DMA) of scan data firom the page memory 106. After data is accessed, it can be manipulated, if desired, by the instruction microprocessor 102 situated external to the system memory 204, thereby reducing the processing burden on the computer system 203. Furthermore, the instruction microprocessor 102 as well as the processor(s) associated with the computer system 203 may exhibit a reduced instruction set computer (RISC) architecture, which has only a limited number of instructions. Such a configuration further enhances performance.

SUMMARY OF THE INVENTION

A novel video processor for a printer and methods thereof are envisioned by the present invention. The video processor is associated locally with a printer and communicates wit an instruct on processor and memory. The video processor generates timing signals and performs scan data fetches, serialization, and printer synchronization.

The video processor has a register file means, an adder/subtracter means, serializing means, and controlling means. The register file means stores frame buffer addresses and format constants.

The adder means performs arithmetic operations on the frame buffer addresses and the format constants in order to generate memory addresses and printer control signals. The serializing means receives parallel data from the memory and serializes the data to the printer.

Finally, the controlling means receives control signals from the instruction processor. It accesses the register file means. Moreover, it controls the adder means and the serializing means.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention, as defined in the claims, can be better understood with reference to the following drawings. FIGURE 1 is a block diagram of a typical page printer system;

FIGURE 2 illustrates a specific implementation of a page printer system wherein a page printer controller is situated remote from a computer system, but in close proximity to a printer engine, and wherein the page printer controller includes peripheral components for performing image manipulations so as to minimize the processing burden on the computer system;

FIGURE 3 is a high level block diagram of the printer video processor shown in FIGURE 2;

FIGURE 4 is a low level block diagram of a controller 1 shown in FIGURE 3; FIGURE 5 is a low level block diagram of a controller 2 shown in FIGURE 3; FIGURE 6 is a low level block diagram of a video data queue shown in

FIGURE 3;

FIGURE 7 is a low level block diagram of a clock divider shown in FIGURE 3; FIGURES 8-14 illustrate the methodology implemented by the state machine within the controller 1 shown in Figure 3; FIGURE 15 illustrates an example of I/O addressing generated by the printer video processor for the front page mode; and

FIGURE 16 illustrates an example of I/O addressing generated by the printer video processor for the back page mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT t oug t e pre erre em o ment o t e present nvention is escr e in detail below, those skilled in the art will readily appreciate the many additional modifications that are possible without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims.

I. Architecture

The architecture for a printer video processor 300 in accordance with the present invention is illustrated in FIGURE 3. The printer video processor 300 provides for fetching of scan data from memory, serialization of scan data to the printer, synchronization with the printer, generation of scan status signals, and interrupt generation. Generally, the printer video processor 300 can be divided into two subsystems. A first subsystem communicates with the I/O interface 206 and the printer engine 110, and a second subsystem communicates with the memory system 208 and the printer engine 110.

With reference to FIGURE 3, the first subsystem has a PVP-IOU Interface 302, a pixel counter 304, a register file 306, a read only memory (ROM) 308, an adder 310, an address latch 312, command/status/mode registers 314, and a controller 316. The PVP-IOU interface 302 has tristate buffers to control the flow of the I/O address and I/O data buses. The pixel counter 304 is utilized for counting the dot clocks in the left margin and in the pixel scan pertaining to printed text. The register file 306 is a one-write/two-read port register file which contains information on the frame buffer addresses and formats, which are used to generate timing and memory addresses. The registers contained in the register file 306 are shown below in TABLE A.

In addition, two other registers, not included in the register file 306, for reasons of space conservation, are used for timing computations. These registers are indicated in TABLE B below, and are situated in the pixel counter 304 in the preferred embodiment.

Closely associated with the register file 306, the read only memory (ROM) 308 comprises a set of format constants. In the preferred embodiment, the ROM 308 comprises the following constants: 0,1,4,8, and 16.

The adder 310 performs arithmetic operations on the register file data and/or ROM constants. The results of the computations, which may be written back into the register file 306, are used by the controller 316 to generate addresses, control, and status signals. Specifically, the adder 310 generates "carry out" flags and "zero" flags which are used by the controller 316 for magnitude comparisons. The "carry out" flag indicates whether the magnitude of a first operand is either greater than or less than the magnitude of a second operand. The "zero" flag indicates whether the magnitudes of a first operand is the same as the magnitude of a second operand. For example, a zero flag is sent to the controller 316 by the adder 310 when a current address is identical to the previous address.

The address latch 312 stores the current address. The current address in the address latch 312 is transferred to the PVP-IOU interface 302 during a memory read/write request. The address latch 312 is necessary in reducing the number of cycles that the controller 316 has mastership over the I/O address bus. During a memory rea wr te request, or per ormance reasons, t e contro er 316 ena es a tristate buffer to allow the current address in the address latch 312 onto the I/O address bus, rather than reading the current address from the register file 306. The command/status/mode registers, collectively represented by reference numeral 314, may be read or written to by the instruction microprocessor 102 in order to provide for software control of scan conversion, software monitoring of scan conversion, and software control of PVP interrupts. The instruction microprocessor 102 can implement coordinate transformation, clipping, scaling, and rasterization of the scan data, as well as run diagnostics. In operation, the controller 316 sequences the printer video processor 300 under the control of the command register 314. The instruction microprocessor 102 loads a scan command by setting the start frame bit of the command register 314, which informs the controller 316 to start scanning. The controller 316 initializes the scan and sequences through the page. The controller 316 performs a series of computations to generate memory addresses to load the seriahzer and timing for the print engine 110, until the page is complete. When the page is complete, it restarts with a new address if the scan pending bit of the command register 314 has been reset.

The mode register 314 is a read/write register which is programmed prior to the start of an page operation, as will be discussed below in regard to the command register 314. The mode register 314 is not double buffered. Moreover, dynamic programming of the mode register 314 while the PVP 300 is operative is not permitted in the preferred embodiment. The contents of the mode register 314 are set forth below in TABLE C:

A "Timing mode" bit and a "JBMS" bit together select whether the PVP 300 will operate in a mode I, II, or HI, each corresponding to a different type of conventional printer having different interactive characteristics. In other words, the printer video processor 300 in accordance with the present invention is a flexible w n erac w one o ree ypes o conventional printers.

More specifically, in the type of conventional printer operating in mode I as defined herein, the software setting of the vertical synchronization (NSync) bit of the status register 314 triggers the page operations. Moreover, the printer clock is free running at a very high rate. Note that a VSync signal is generated by software in response to an FSync signal from the printer engine 110. In the type of conventional printer operating in mode II as defined herein, the printer's FSync signal triggers the printer video processor 300 to begin page operations. Further, the printer clock is free running. Finally, in the type of conventional printer operating in mode HI as defined herein, the printer's FSync signal triggers the printer video processor 300 to begin page operations. Also, the printer clock is not free running.

In the preferred embodiment, the decoding scheme for the JBMS and TMDE bits is shown in TABLE D below. It should be appreciated that many other decoding schemes are possible and that more than three types of printer modes can be defined and encoded.

In the case when the printer video processor 300 is programmed to operate in mode I, as defined by the JBMS and TMDE bits, a DIV bit informs the PVP clock generator (reference numerals 408,410 of Figure 4) to divide the video input clock by 8, if 0, or to divide the input clock by 16, if 1. In the case when the printer video processor 300 is programmed to operate in mode II or III, the PVP clock generator does not d vide the video input clock.

Furthermore, in the preferred embodiment, a "band buffer mode" can be implemented thereby allowing for flexibility in terms of memory management. Band buffer mode is selected if a BBE bit is at a logic high ("1"); otherwise, the normal full page mode is selected. In the context of this document, the band buffer mode is a mode of operation wherein the printer video processor 300 alternates between different frame buffers within page memory in order to print a page of text. Each band buffer is a memory block of ό size scan lines. The first address pertaining to the first band buffer is referred to as a "base" address. The first address pertaining to any other band buffer thereafter is referred to as a "pbase" address. Also in mode register 314, CINT, VINT, PRDY and VSREQ bits represent interrupt enables for the respective interrupt sources. If any of these bits are set to a logic high, then the associated interrupt source is enabled to generate the par cu ar n errup . ore an one n errup may e ac ve a a t me n e preferred embodiment.

When the PRDY bit in the mode register 314 is set at a logic high, if the printer ready (PRDY) signal from the printer engine 1 0 transitions from inactive to active, an interrupt is posted. Furthermore, when the video scan request (VSREQ) bit in the mode register 314 is at a logic high, if the VSREQ signal from the printer engine 110 transitions from inactive to active, an interrupt is posted.

The BLV bit indicates either a "white level" or a "black level" of operation by either a logic high or a logic low, respectively. The foregoing levels relate to the inversion of the scan data in accordance with another feature permitted by the printer video processor 300 of the present invention. Normally, a logic low ("0") sent to the printer engine 110 corresponds to the white on a page, while a logic high ("1") corresponds to black on a page. The black level is the default level in the preferred embodiment. If inversion is selected, a logic low corresponds to black, while a logic high corresponds to white, excepting the margins which are always maintained white. Scan data is said to be "blanked" in the margins, as discussed in detail later below in regard to FIGURE 6 (black level signal 634 and blank signal 636 fed to logic 347).

The reserved bits as indicated in TABLE C must be programmed to zero to avoid potential adverse side effects. These bits are provided for implementing production test features or future enhancements.

The command register 314 is a write only register which receives commands fi-om the controlling software within the instruction microprocessor 102. The contents may be read through the status register 314. The contents of the command register 314 are indicated below in TABLE E:

The command register 314 is used to initiate PVP operations and to support some testing functions. No operations are initiated other than through the command register 314. The command register 314 is double buffered for performance reasons and flexibility. The first loading of the command register 314 enables a frame to be generated by the PVP 300. If the command register 314 is loaded a second time, then a second frame will commence after the completion of the first frame, unless the second frame is a reset (RSET) or a testing function. If, subsequently, the command register 314 is loaded a third time, prior to the comp et on o t e rst rame, t e resu ts may e unpre cta e un ess t e it is set, in which case all operations are aborted.

An STF bit in TABLE E, which corresponds to "start frame" command, initiates the timing and DMA operations which the PVP 300 performs during normal system operations. The command register 314 is cleared and all operations are halted if the printer controller reset signal is asserted. All operations may also be abruptly halted by setting the RSET bit of the command register 314. Essentially, the RSET bit overrides the other bits in the command register 314.

A BKRL bit indicates whether "back side printing" is to be performed. In the case where back side printing is set, a page is scanned in reverse order, i.e. , from bottom to top and from right to left.

An ERASE bit indicates whether the frame buffer is to erased after printing. More specifically, after a memory word is read by the printer video processor 300 for printing, the memory word can be erased. This feature provides for higher performance.

The reserved bits indicated in TABLE E must be programmed to zero in order to avoid potential adverse side effects. These bits may be used for implementing production test features or future enhancements.

The status register 314 holds pertinent information for the control and monitoring of the PVP 300. The status register 314 is a read/write register whose contents are indicated below in TABLE F.

The FTP it in icates that a frame has been started, but has not yet been completed. The FPD bit indicates that a second frame has been loaded, but has not yet started, except in the case of a reset command, which will halt all operations and clear these bits. State transition bits, CINTA, VINTA, BBIA, PRDYA, VSREQA, indicate that their associated event has occurred, and that they have not yet been cleared. If their associated interrupt enable has been set, then they generate interrupts when active. The interrupts are cleared when the status register state bits are cleared by setting them to a logic high. Writing a logic low to these bits leaves them unchanged in the preferred embodiment. Once set by the hardware, the associated state bit is not reset except as described above, when the RSET bit of the PVP 300 is active, or the PVP reset command is executed.

The pin level bits hold the levels of the I O pins. The LSYNC, FSYNC, PRDY and PPRDY bits are all inputs (therefore, read only), while the VSYNC, PRNT and CPRDY bits are outputs. The VSYNC, PRNT and CPRDY bits are cleared to logic low by reset operations and are dynamically programmable to any level by processor writes to the status register 314.

The TMDE, BBE and interrupt enable bits hold the values last programmed into the mode register 314. Some bits are provided exclusively for testing. As examples, consider the following bits. The MREQ status bit indicates whether the PVP 300 has one or more outstanding memory requests which have not yet been completed. The BLANK bit indicates that horizontal blanking is currently occurring. The FIFO status bits hold various FIFO control states for the scan data queue 344 of Figure 3. In order to reset interrupts in the PVP 300, a reset instruction is sent to the

PVP command register 314, or alternatively, the individual interrupt bits are reset in the status register 314.

When the V_int register is loaded, it is decremented on each fine reset (when

X_current is loaded from X_max). When V_int becomes less than 0, the VTNTA status bit is set. An interrupt is sent to the instruction microprocessor 102 if the

VINT interrupt enable bit is set. V_int is generated after the data in the scan line pointed to has been sent to the printer engine 110.

The CINT (print complete interrupt) bit is set after the last scan of data has been sent to the printer engine 110. The print complete interrupt is posted if both the status and interrupt enable are set.

The PRDY interrupt is set when the PRDY bit transitions from inactive to active (PRDYAP transition bit is set in status register 314) if the PRDY interrupt is enabled. The PRDY interrupt is also set when the PRDY bit transitions from active to inactive (PRDYAN transition bit is set in status register 314) if the PRDY interrupt is enabled. The BBI interrupt is set when the PVP 300 is in band buffer mode, the BBI interrupt is enabled, the current buffer has been printed (the BBI status bit is set), and the base registers have been swapped. When band buffer mode is not selected, the BBI status bit is always cleared. FIGURE 4 shows the preferred embodiment of the controller 316. The controller 316 comprises a decoder 402, a state machine 404, a logic/buffer 406, a clock divider 408, a clock buffer 410, an interrupt logic 412, and a decoder/mux 414. It should be emphasized that many other circuit configurations are conceivable by one of skill in the art to accomplish the functionality as set forth hereafter. The decoder 402 decodes the I/O address, read write signal, chip select, and address strobe in order to generate read and write enables for the latches and/or registers inside the printer video processor 300. The decoder 402 also generates the handshake control signals to the PVP-IOU interface 302. In the preferred embodiment, the handshake control signals include "ready" and "read/write" signals. The logic/buffer 406 produces the size of the memory read write request which is transferred to the PVP-IOU interface 302 at the same time that the current address is sent out to the I/O address bus by the address latch 312. In addition, the logic/buffer 406 is controlled by the state machine 404 to mask off the last four bits of the adder output for end of scan line computations. Moreover, the logic/buffer 406 is controlled by the state machine 404 to mask off two bits in the current address during a memory write request if two scan lines overlap, and the clock generator produces the dot clock from the printer clock. The foregoing operation is necessary for the clear function provided by the present invention.

The clock buffer 410 provides a video clock to the printer video processor 300 synchronously with the printer clock from the printer engine 110. The clock divider 408 takes the printer clock from the clock buffer 414 and divides the printer clock frequency by either 8 or 16, or alternatively, performs no division at all, in accordance with another feature of the present invention. The divide option can be selected through the mode register 314. The interrupt logic 412 performs combinational logic on the status register's event bits and the mode register's interrupt enable bits in order to generate an interrupt signal which can be used for monitoring the state of the printer video processor 300. In the preferred embodiment, there are five interrupts: (1) a vertical interrupt when a particular scan line is reached; (2) a band buffer interrupt indicating the termination of a band buffer; (3) an interrupt for indicating completion of a page; (4) a frame synch interrupt from the print engine 110 for provoking the printer video processor 300 to start a new page; (5) an interrupt acknowledging the ready signal from the printer engine 110.

The decoder/mux 414 decodes the I/O addresses from the PVP-IOU interface 206 into register file write addresses and enables. The decoder/mux 414 selects either the I/O or printer video processor addresses and enables the register file write signals.

The state machine 404 controls the order of computations involving the register file 306 and constants in the ROM 308. The order of computations depends upon the timing signals from the printer engine 110 and the command/status/mode register bits for the sequencing and triggering of events contained within the registers 314. The sequence of events which occurs in the printer video processor and the algorithms carried out by the state machine 404 are described hereafter in regard to Figures 7-13. Referring back to FIGURE 3, the second subsystem of the printer video processor 300 in accordance with the present invention communicates with the memory system 208 and the printer engine 110, As shown in FIGURE 3, the second subsyste comprises a PVP-MCU interface 342, an scan data queue (FIFO) 344, a parallel-to-serial shift register (seriahzer) 345, and a controller 346. The PVP-MCU interface 342 includes latches for storing data from the MCU bus.

The scan data queue 344, which is essentially a FIFO buffer, is loaded with the data from the PVP-MCU interface 342 whenever space is available. Together with the PVP-MCU interface 342, the scan data queue's storage of scan data while a page is in progress allows for an uninterrupted stream of video bits to the printer engine 110. Specifically, the scan data queue 344 sends full and empty signals to the controller 346. In response, the controller 346 controls the flow of data to prevent the loss of data or the emptying of the queue 344 prior to the end of a scan. The depth of the queue 344 is implementation dependent and is set by the expected worst case latency in the memory system and the intended maximum video clock rate, but is a τm^*n-fτm.τπ of 8 words in the preferred embodiment.

The seriahzer 345 is loaded with scan data bytes from the scan data queue 344. These scan data bytes can be manipulated by the controller 346 via logic 347, which will be discussed in detail later in this document, before being sent on to the printer engine 110. In the preferred embodiment, the seriahzer 345 outputs data in a serial manner at 1 bit per dot clock (DCLK) from 8 bits of data. The printer video data 370 which is outputted from the PVP 300 to the printer engine 110 is designated as WDATA in this document.

FIGURE 5 illustrates a low-level block diagram of the controller 346 shown in FIGURE 3. With reference to FIGURE 5, the controller 346 includes a counter 502, latches logic 504, and logic 506 for asserting the proper latch enable when the MCU bus data is valid. The foregoing hardware provides for compatibility with both front and back page modes, as well as the out-of-order return of data from the memory system 208, in accordance with another feature of the present invention. s men one prev ous y, e scan a a queue s s orage o scan ata w e a page is in progress allows for an uninterrupted stream of video bits to the printer engine 110. As shown in FIGURE 5, logic 508 in the controller 346 generates the video queue's write signal. Moreover, the logic 508 selects the PVP-MCU interface data to be written into the scan data queue 344.

With respect to the loading of the parallel-to-serial shift register 346, a counter 514 and a decoder 516 generate a byte select for the scan data queue 344. The counter 514 is an up/down counter in order to provide for compatibility with both front and back page modes. In the front page mode, the byte selects must occur in increasing byte addresses, whereas in the back page mode, the byte selects must occur in decreasing byte addresses.

Latches/logic 520, counter 522, and decoder 524 generate the bit select for the scan data to the printer engine 110. Like counter 514, counter 522 is also an up/down counter, for providing compatibility with both front and back page modes. In the front page mode, the least significant bits are serialized first. In contrast, in the back page mode, the most significant bits are serialized first. After all bytes within a word in the scan data queue have been loaded into the seriahzer 345, the scan data queue 344 must be purged of that word to allow for a new word to be serialized.

The controller 346 further includes a synchronizer/logic 526. The synchronizer/logic 526 when operating in the front page mode detects that the most significant byte has been loaded into the seriahzer 345 and generates the read signal to the scan data queue 344. The synchronizer/logic 526 in the back page mode detects that the least significant byte has been loaded into the seriahzer 345 and generates the read signal to the scan data queue 344.

Another significant feature of the present invention is that data sent to the printer engine 110 is serialized starting at a byte, rather than at a word address. Each time that the current address is initialized with each scan line starting address, the least significant three bits of the current address are preloaded into the counter 514 of FIGURE 5. Thus, decoder 516 of FIGURE 5 can select any scan data byte in the scan data queue 344 as the starting byte in each scan line.

FIGURE 6 shows a low level block diagram of the FIFO block 380 shown with phantom lines in FIGURE 3. The FIFO block 308 comprises the PVP-MCU interface 342, the video data queue 344, the seriahzer 345, and the logic 347.

As shown in FIGURE 6, the preferred embodiment of the PVP-MCU interface 342 includes four 32-bit registers 602-608 for ordering data into a 64*4 bit first-in-first-out (FIFO) buffer 610 contained within the video data queue 344. The interface 342 also includes a 64-bit multiplexer (mux) 612 for selecting which pair of the registers (either 602, 604, or 606,608) is to be loaded into the FIFO buffer 610. A 2-bit up counter 614 in conjunction with decode logic (DEC) 616 provides enable signals to the registers 602-608. Furthermore, decode logic (DEC) 620 in combination with flip flops 622-626 generate the FIFO push signal after the last register 602-608 has been preloaded. An 8-input mux 628 at the output of the FIFO buffer 610 selects which of the

8 bytes from the FIFO buffer 610 is to be loaded into the shift register (seriahzer) 345. A 3-bit up/down counter 630 in combination with decode (DEC) 632 generate select signals to the mux 628. Moreover, the bidirectional 8-bit shift register 345 serializes the printer video data. It should be noted that dot clock (DCLK) 656, which is used to clock the printer engine 110, may be asynchronous to PVP system clock (SCLK). However, the pop instructions to the FIFO block 380 are synchronous to DCLK 656 and are resynchronized with the PVP system clock (SCLK) 655 via logic 640 and decode 642, as shown in FIGURE 6. The FIFO buffer 610 is 64 bits wide and 4 bits deep. However, the FIFO buffer 610 must accommodate both the 32-bit and 64-bit MCU switch modes as well as both the front and back page modes, in accordance with the present invention. When the system operates in the 32-bit mode, data provided externally for input to the FIFO buffer 610 will come in 32-bit blocks, whereas when the system operates in the 64-bit mode, data comes in 64-bit blocks. Moreover, the order in which the FIFO data is loaded is different for the front page mode and the back page mode. The reason is that the front page mode requires a page scan from left to right wherein addresses are increasing. In contrast, the back page mode requires a page scan from right to left wherein address are decreasing. Hence, in order to provide for both the 32-bit mode and 64-bit mode as well as both the front page mode and the back page mode, the circuitry shown in FIGURE 6 must go through a series of FIFO loading procedures whenever a memory request is performed.

For the 32-bit mode, the 2-bit up counter 614 is preloaded as indicated in TABLE G shown below.

For the 64-bit mode, the 2-bit up counter 614 is preloaded as indicated in TABLE H shown below.

The following discussion will explain the loading procedures for the FIFO block 380 by individually analyzing each of the four possible operational scenarios, specifically: (l)32-bit mode/front page mode (left to right scan); (2)32-bit mode/back page mode (right to left scan); (3) 64-bit mode/front page mode (left to right scan); and 64-bit mode/back page mode (right to left scan). In the following discussion, assume that DO, Dl, D2 and D3 are the data words returned to the FIFO block 380 and that DO is the lowest order address while D3 is the highest order address.

For operational scenario (1), i.e. , 32-bit mode and front page mode (left to right scan), the registers 602-608 are loaded in the manner indicated in TABLEs I through K, hereafter, for a given starting byte STB[1:0] and counter 614 state.

One FIFO push signals generated: PUSH 1: {R1,R0}

One FIFO push signals generated: PUSH 1: (Rl,xx)

For operational scenario (2), i.e., a 32-bit mode and back page mode (right to left scan), the registers 602-608 are loaded in the manner indicated in TABLEs L through N, hereafter, for a given STB[1:0] and counter 614 state.

One FIFO push signals generated: PUSH 1: {R3,R2}

One FIFO push signals generated: PUSH 1: {R3,xx}

For operational scenario (3), i.e. , 64-bit mode and front page mode (left to right scan), the registers 602-608 are loaded in the manner indicated in TABLEs 0 through Q, hereafter, for a given STB[1:0] and counter 614 state.

One FIFO push signals generated: PUSH 1: {R3.R2} PUSH 2: {R1,R0}

One FIFO push signals generated: PUSH 1: {R1,R0}

One FIFO push signals generated: PUSH 1: {R3,R2}

For operational scenario (4), i.e. , 64-bit mode and back page mode (right to left scan), the registers 602-608 are loaded in the manner indicated in TABLEs R through T, hereafter, for a given STB[1:0] and counter 614 state.

One FIFO push signals generated: PUSH 1: {R3,R2} PUSH 2: {R1,R0}

One FIFO push signals generated: PUSH 1: {R3.R2}

As mentioned previously, the logic which selects one of eight bytes to be read from the FIFO buffer 610 into the shift register 345 includes the 3-bit up/down counter 630. The up/down counter 630 is loaded only at the beginning of each scan line with bits CURRENT[2:0]. These bits CURRENT[2:0] determine the starting byte STB[1:0] of the scan. The output of the up/down counter 630 provides the selects for the mux 628 and is clocked whenever the shift register 345 is loaded. The byte sequence corresponding to the states of counter 630 in the preferred embodiment is indicated in TABLE U hereafter.

For the front page mode (left to right scan), the counter 630 is an up counter, and the shift register 345 shifts right (LSB first). Whenever CTR= 111, a FIFO "pop", or trigger, signal is generated. This condition must complete before the shift register 345 shifts out all its data in the last byte.

For the back page mode (right to left scan), the counter 630 is a down counter, and the shift register 345 shifts left (MSB first). A FIFO pop signal is generated whenever CTR=000.

Furthermore, a black level (BLV) signal 634, which is fed to the logic 347, determines whether printer video data (WDATA) 370 corresponds to either black or white. If BLV = 0 in the mode register 314 of FIGURE 3, then WDATA= 1 corresponds to black. If BLV= 1, then WDATA=0 corresponds to black.

In addition, whenever a BLANK signal 636 is asserted to the logic 347, then the printer video data (WDATA) is white (0 if BLV=0, 1 if BLV= 1) to accommodate for page margins.

As mentioned previously, multiple types of printers may also be utilized in accordance with the present invention. Bits within the mode register 314 are initialized to se ect one o t ree types of printer engines 110 with which the printer video processor 300 will interface. In the type of conventional printer operating in mode I herein, the software setting of the status register's frame synchronization (VSync) bit triggers the page operations. Moreover, the printer clock is free running at a very high rate. In the type of conventional printer operating in mode II herein, the printer's FSync signal triggers the printer video processor 300 to begin page operations. Further, the printer clock is free running. Finally, in the type of conventional printer operating in mode III herein, the printer's FSync signal triggers the printer video processor 300 to begin page operations. Also, the printer clock is not free running.

In order to provide for the foregoing three modes of operation, the clock divider 408 of FIGURE 4 is implemented in the preferred embodiment as shown in FIGURE 7 described below.

FIGURE 7 shows a low level block diagram of the divider 408 of FIGURE 4. With reference to FIGURE 7, the output of the divider 408, called the "dot clock", essentially clocks out data to the printer engine 110. A line synch (lsync) signal is provided by the printer engine 110, notwithstanding the printer type. When an lsync signal is received, an edge detector 702 detects the leading edge of the lsync and causes a flag 704 to go to a logic high. At a logic high, the flag 704 will cause the divider 408 to generate dot clock. A synchronizer 706 causes the outputted dot clock to operate synchronously with the inputted printer clock. Logic 708 forms an AND function between the output of the synchronizer 706 and the inputted printer clock to provide an input signal 710 to a multiplexer (mux) 712. The foregoing signal is permitted to travel through the mux 712 in the case of mode II or mode III as controlled by signals 714 and 716.

A divider 718 is provided for permitting proper operation with mode I printers. The divider 718 divides the printer clock by either 8 or 16 and feeds the divided signal into the logic 708. The logic 708 performs an AND function on the printer clock and the divided signal in order to produce an input signal 720 to the mux 712. In the event that the divider 408 is operating in mode I, the mux 712 will permit the signal 720 to produce the outputted dot clock pursuant to the control 722.

When the printer engine 110 reaches the end of a scan line, a blank signal as shown is inputted to a latch 724. The blank signal causes the flag 704 to go to a logic low, thereby terminating the output of a dot clock by the divider 408.

II. Operation

The sequence of events which occurs in the printer video processor 300 is set forth hereafter. 1. The parameters of the video register file 306 of Figure 3 are pre-loaded, including the base register. The foregoing operation is normally done during the initialization of the printer and associated peripherals, unless the page size, frame buffer address, or margins are changed dynamically during operation. 2. The printer engine 110 asserts to the PVP 300 that it is ready for data.

3. A print signal is asserted to the printer engine 110 by the controlling software in the instruction microprocessor 102.

4. A print command is loaded by the controlling software of the instruction microprocessor 102 into the command register 314 of the PVP 300. - 5. An FSync signal is asserted by the printer to the PVP 300. The FSync signal is asserted to the state machine 404, shown in Figure 4.

6. The state machine 404 begins to time the top margin. A "top margin count algorithm" used by the state machine 404 to time the top margin when the PVP 300 operates in the front page mode is set forth in detail in FIGURE 8 and FIGURE 9. In the alternative, when the PVP 300 operates in the back page mode, a top margin count algorithm used by the state machine 404 to time the top margin is set forth in detail in FIGURE 9 and FIGURE 12.

7. When the top margin timer (programmed by register "T_margin") completes its count, the pixel counter 304 waits for an LSync signal fro the printer engine 110.

8. When the LSync input is received by the PVP 300, the pixel counter 304 begins the left margin timer (programmed by register "L_margin") and the serializer 345 fetches the first frame buffer data to be sent to the printer engine 110. 9. When the left margin timer L_margin completes, scan data begins to pass out of the controller 346 of the PVP 300 synchronously with the printer clock. A "serialization algorithm" used by the state machine 404 to serialize scan data when the PVP 300 operates in the frontpage mode is set forth in detail in FIGURE 10. In the alternative, when the PVP 300 operates in the back page mode, a serialization algorithm used by the state machine 404 to serialize scan data is set forth in detail in FIGURE 13. The end of the scan is determined by the L_margin counter, but using the X_MAX register data.

10. At the end of each scan line, the pixel counter 304 is forced to wait for the LSync and L_margin timer, until the last scan of the image frame is completed. A "post scan line algorithm" used by the state machine 404 at the end of each scan line, i.e. , in the right margin of a page, when the PVP 300 operates in the front page mode is set forth in detail in FIGURE 11. In the alternative, when the PVP 300 operates in the back page mode, a post scan line algorithm used by the state machine 404 at the end of a scan line is set forth in detail in FIGURE 14. 11. When t e last scan of the image frame is complete, the PVP 300 awaits the next print command from the command register 314. If a pending print command is present, a new frame is immediately started.

III. Features and Advantages

In conclusion, the present invention provides for many features and advantages. By way of example, some of the features are discussed hereafter. The printer video processor 300 provides for efficient and speedy direct memory access (DMA).

The printer video processor 300 provides for byte alignment of data at the beginning and end of each scan line. In other words, data can be serialized starting at a byte address, rather than at a word address.

The present invention provides for a band buffer mode in which the printer video processor alternates between different frame buffers within page memory in order to print a page. Specifically, in the band buffer mode, the data corresponding to the base and pbase addresses are swapped in top-of-page operations as well as in blank operations. The printer video processor 300 alternates between band buffers of 6 size scan lines starting at a base or pbase address. If only two band buffer addresses are needed for a page scan, the base and pbase registers are initialized only once prior to a page scan. However, if more than two band buffer addresses are needed, the printer video processor 300 provides an interrupt signal and a status bit indicating the completion of a band buffer so that the base or pbase address may be dynamically modified. The printer video processor provides the ability to operate in either front and back page modes.

Yet another feature of the present invention is that the printer video processor 300 can invert scan data outputted to the printer engine, thereby inverting the image to be physically printed on a paper page. Clearing portions of the frame buffer during a page scan is still another feature provided by the printer video processor 300 of the present invention. More specifically, the printer video processor 300 usually submits a memory write request after each memory read request. The read and write request sizes are usually the same except for the request for data bytes near the end or at the beginning of a scan line. After each memory request, while data is being serialized to the printer engine 110 by the PVP 300, the state machine 404 of the PVP 300 determines via adder 310 if the next requested bytes will also be in the next scan line. If so, the printer video processor 300 sets a overlap flag which disallows writing of those bytes in the next scan line. When the first memory read request is submitted for the next scan line, the overlap flag can also cause masking of the requested address and data size to allow for complete clearing of a word.

Finally, the printer video processor 300 is compatible with multiple types of printers. Bits within the mode register of the printer video processor can be initiahzed to select one of three types of conventional printers, each having different operational characteristics.

Further features and advantages of the present invention will become apparent to one skilled in the art upon examination of the drawings and the text contained herein. It is intended that any additional features and advantages be incorporated herein.

IV. Examples

FIGURE 15 and FIGURE 16 show examples of I O addressing generated by the printer video processor for the front page mode and the back page mode, respectively. These examples illustrates the nature of many of the features and advantages of the present invention. Because the layout of the examples in these figures is substantially similar, only the example shown in FIGURE 15 will be discussed hereafter; however, the following discussion is equally applicable to FIGURE 16.

With reference to FIGURE 15, a legend block 1502 indicates the initial values of various parameters within the register file 306. These parameters are shown and described in regard to TABLE A hereinbefore. In summary, the parameters in block 1502 serve the following functions. The y_max is the number of scan lines in the hypothetical page shown in FIGURE 15. The base is the first byte address. The pbase refers to the address of the next band buffer. The bsize is the band buffer size corresponding to the base address. Because bsize is set to 3 in this instance, a band buffer interrupt will occur after the third scan line 1540. The x_max is used to determine when a scan fine is completed. The ystep is used to indicate which address to start at on each scan hne. The x_maxl is equal to the number of bytes minus one byte. x_maxl is used to determine when the scan data is serialized. As shown in FIGURE 15, an FSync signal 1504 is sent from the printer engine 110 to indicate when to start a page. A blank signal 1506 indicates when data is blanked. When data is blanked, the printer engine 110 will not print anything on the page, i.e. , the page will be white.

Initially, x_current equals x_max. x_current is a flag used by the PVP 300 to determine when the current address in the register file 306 should be compared to the starting address (base_current) of the next scan line. If x_current is less than or equal to zero, then the PVP 300 checks for overlap. x_max represents t e maximum number of bytes permitted in a scan line. Essentially, x_max is set to a particular value and, then, as bytes are sent to the printer engine 110, the value is decremented so as to operate like a counter. In the preferred embodiment, x_max is set at 96 bytes (60h). However, in actuality, a scan line has no more than 89 bytes, but x_max is rounded up to the nearest multiple of 8 bytes.

Memory read requests are sent to memory by the PVP 300, while the printing mechanism (not shown) in the printer engine 110 is scanning in the top margin. At a reference numeral 1510, FIGURE 15 shows that a base address 7fHfddh (suffix "h" means hexadecimal), which is the current address stored in the register file 306, is sent to memory as an I/O address 7ffffdch. Essentially, the I/O address sent to memory is the current address with the last two bits masked with zeros. Thus, all I/O addresses sent to memory by the PVP 300 are word addresses instead of a byte addresses. In accordance with another feature of the present invention, when the I/O addresses are written to memory, a write signal can be sent after each read request by command of the ERASE bit in the command register 314. The read request causes the data to be sent from memory to the PVP 300. The subsequent write signal essentially clears that memory location in memory by informing memory to write zeros in that location.

As a result of the memory read request directed at the foregoing address 7flffdch, a word (4 bytes), for example, is loaded into the scan data queue 344. The amount of data requested by the PVP 300 is determined by the particular I/O address sent to memory. Next, the retrieved data is cleared in memory, as indicated in the column 1510. Moreover, because 1 word was loaded into the PVP 300, which word comprises 4 bytes, x_max is decremented from 60h, which represents 96 bytes, to 5ch, which represents 92 bytes.

The column denoted by reference numeral 1512 represents another read request sent from the PVP 300 to memory. The current address in the register file 306 is 7ffffelh. The last two bits are masked to zeros so as to generate an I/O address 7-fiffeOh. As a result of the memory read request directed at the I O address 7fHFe0h, 4 words, for example, are loaded into the scan data queue 344. The same 4 words are cleared in memory, as indicated in the column designated by reference numeral 1512. Moreover, because 4 words are loaded into the PVP 300, which 4 words comprise 16 bytes, xjmax is decremented from 5ch, which represents 92 bytes, to 4ch, which represents 76 bytes.

The column represented by reference numeral 1514 represents another read request which is to be sent from the PVP 300 to memory after pixel serialization commences. The current address within the register file 306 is 7ffifflh, and the related I/O address is 7fFffϊ0h. No more words are presently loaded into the scan data queue 344, because the scan data queue (FIFO) 344 in the preferred embodiment only stores 32 bytes. Because no words are not loaded into the scan data queue 344, no clearing function occurs. However, x_current is decremented to 3ch. Because the scan data queue 344 already has data to print when the blank signal is deasserted, the PVP 300 can immediately serialize data to the printer engine 110. The printer engine 110 is able to print 3 bytes from the addresses sent in column 1510, as indicated in the first scan line 1516. Furthermore, the printer engine 110 is able to print another 16 bytes from the addresses sent in column 1512, as further indicated in the first scan hne 1516.

When the scan data queue 344 gets low on data, it sends out more read requests to memory, as indicated by a column 1518, in order to get more data.

Moreover, the clearing of words in memory may not occur at the end of a scan line (when the blank signal is reasserted). Consider the column 1520 of FIGURE 15. The 4 words retrieved are not cleared because the next set of addresses, in column 1522, overlap. Specifically, 80000036h overlaps with 80000030h. As shown, three memory read requests can be performed before the printer engine 110 is ready to print the next scan line 1528.

Claims

CLAIMSThe inventors claim the following:

1. A video processor associated with a printer and communicating with an instruction processor and memory, the video processor for performing scan data fetches, serialization, and printer synchronization, comprising: a register file means for storing frame buffer addresses and format constants; adder means for performing arithmetic operations on said frame buffer addresses and said format constants in order to generate memory addresses and printer control signals; serializing means for receiving parallel scan data from said memory and for serializing said scan data to said printer; and a controlling means for receiving control signals from said instruction processor, for accessing said register file means, and for controlling said adder means and said serializing means.

2. The video processor of claim 1, further comprising an address latching means for temporarily storing said memory addresses before access to said memory.

3. The video processor of claim 1, wherein said serializing means comprises a first-in-first-out data buffer configured to store scan data received from said memory until said scan data is serialized to said printer.

4. The video processor of claim 1, wherein said controlling means comprises a state machine for controlling said arithmetic computations in response to printer timing signals and said control signals from said instruction processor.

5. The video processor of claim 1, wherein said controlling means comprises a clock means for serializing scan data synchronously with said printer, said clock means for having the ability to reduce the printer clock frequency so as to enable compatibility of said video processor with various types of said printer.

6. The video processor of claim 1, further comprising means associated with said register file means for transforming a memory address directed to a data byte into an I/O address directed to a data word via masking the least significant two bits of said data byte with zeros.

7. The video processor of claim 3, further comprising a controlling means for generating byte selects for said data buffer in either increasing byte address order or decreasing byte address order to thereby provide for operation in a back page mode or front page mode, respectively.

8. A method for a video processor associated with a printer and communicating with an instruction processor and memory, the method for performing scan data fetches, serialization, and printer synchronization, comprising the steps of: - - storing frame buffer addresses and format constants; performing arithmetic operations on said frame buffer addresses and said format constants in order to generate memory addresses and printer control signals;

receiving parallel scan data from said memory; and serializing said scan data to said printer.

9. The method of claim 8, further comprising the step of clearing said scan data in the frame buffer during a page scan.

10. The method of claim 8, further comprising the step of inverting said scan data to said printer.

11. The method of claim 8, further comprising the step of addressing noncontiguous band buffers in said memory when retrieving said scan data.

12. The method of claim 8, further comprising the step of initializing said video processor to operate compatibly with one of a set of predefined printers.

13. The method of claim 8, further comprising the steps of: providing said video processor with a memory address directed to a data byte; transforming said memory address at said video processor into an I O address directed to a data word; requesting said memory for transfer of said data word; and extracting said data byte from said data word at said video processor.

14. The method of claim 8, further comprising the step of masking the least significant two bits of said data byte with zeros so as to transform said data byte into said data word.

15. A met o or a video processor associated with a printer and communicating with an instruction processor and memory, the method for performing scan data fetches, serialization, and printer synchronization, comprising the steps of: storing frame buffer addresses and format constants in a file register; informing said video processor via said printer that said printer is ready for printing data; indicating to said printer via the controlling software of said instruction processor that data is to be printed; loading a print command into a command register associated with said video processor via said controlhng software; asserting a frame synchronization signal via said printer to said video processor; timing the top margin of a page; waiting for a line synchronization signal from said printer; timing the left margin of said page; fetching at said video processor an image frame to be sent to said printer; serializing into scan lines said image frame to said printer, synchronously with the clock of said printer; and at the end of each scan hne, waiting for a line synchronization signal and a queue that said left margin is timed out, until the last scan of said image frame is completed.